A SYSTEMATIC STUDY OF LAYOUT PROXIMITY EFFECTS FOR 28NM

POLY/SION LOGIC TECHNOLOGY

Ruoyuan Li*, Jiajia Tao, Tao Yang, Zicheng Pan, Yuejiao Pu, Hong Wu, Shaofeng Yu, Falong Zhou,
Yongping Deng, Ling Sun, Longyi Yue, Fengying He, Weizhong Xu, Bin Ye, TzuChiang Yu
Technology R&D Center, SMIC
18 Zhangjiang Road, Pudong New Area, Shanghai, P.R. China 201203
E-mail: Nikki_Li@smics.com

ABSTRACT in LPEs schematics. To investigate the LPEs, various test

As CMOS scaling extends into 28nm technology, structures with channel width/length of 1umlO.03um are

transistor behavior depends not only on its channel length and studied. The LPE trends are analyzed by the threshold voltage

width, but also on other layout geometric parameters and the (Vtsat) and saturated drive current (Idsat). For PMOS, we used

surrounding neighborhood. In this paper, a systematic study the absolute value of these two parameters.

was conducted on the layout proximity effects (LPEs) of 28nm WELL

Poly/SiON logic transistors, which includes length of oxide
diffusion (LOD) effect, dummy poly spacing (DPS) effect,
active area spacing effect (ASE), and well proximity effect
(WPE). We explored the mechanisms behind these LPEs and
proposed physical models that can explain the LPEs' impacts
on transistor electrical behavior. We found that the changes in
dopant distribution and stress/dopant induced mobility at Cl Active area
different transistor geometric parameters are the two major · Poly
factors that cause LPEs.
Fig. 1 : Illustration ofLPE dimension definition
INTRODUCTION
Chip size has been continuously shrinking for the purpose
RESULTS AND DISCUSSIONS
Length of oxide diffusion effect
of cost reduction and performance enhancement. The increase
Fig.l shows that for different LODs, that is, different SA or
of density is achieved by pushing the device size and the
SB, device electrical parameters may change, which is called
shrinking the dimensions of patterns. As CMOS scaling
LOD effect. In our study, SA has the same value as SB.
extends into 28nm technology, a transistor is no longer
Fig.2 shows N/PMOS electrical parameters and SA size
adequately characterized by its width and length, but further
correlation. With the reduction of SA, for NMOS Idsat
depends on other layout geometric parameters and the
decreases and Vtsat increases while for PMOS both Idsat and
surrounding neighborhood [1]-[3]. So layout proximity effects
Vtsat drop. Conventionally, LOD effect on device performance
(LPEs) become a serious concern and cannot been ignored. In
is explained by the shallow trench isolation (STI) stress. The
addition, embedded SiGe (eSiGe) on the source and drain (SID)
STI stress is the mechanic stress caused by the difference of
region is used to improve hole mobility in PMOS devices,
thermal expansion coefficients between Si and Si02.The STI
which increases the complexity of PMOS LPEs [3]-[6].
used by 28nm Poly/SiON exerts tensile stress to the active area
In this paper, a systematic study was conducted on the
(AA) which is preferred by NMOS but not desired for PMOS
LPEs of 28nm Poly/SiON logic transistors, which include
along the channel length direction. And it is beneficial for both
length of oxide diffusion (LOD) effect, dummy poly spacing
NMOS and PMOS Idsat along channel width direction. With
effect (DPS), active area spacing effect (ASE), and well
the reduction of SA size, STI tensile stress has a stronger
proximity effect (WPE). We explored the mechanisms behind
influence on the channel. As a result, NMOS Idsat should
these LPEs and proposed physical models that can explain the
increase and PMOS Idsat should decrease. But our silicon data
LPEs' impacts on transistor electrical behavior. We found that
do not reflect the trend and the STI stress cannot exactly
the changes in dopant distribution and mobility are the two
explain it.
major factors that cause LPEs.

c
EXPERIMENTS 1 z

The MOSFET samples in this paper were fabricated by {:

28nm Poly/SiON CMOS process on P-type (100) silicon
1:
substrates. After STI process, the poly silicon gate with dual .... � ,-]
gate oxide and offset spacer were fonned, followed by the
.00 .. .00
selective deposition of in situ boron-doped SiGe on PMOS SAlarbltrlryunh)

source/drain. The nickel silicide and Cu backend is applied to (a) (b)

complete the process Fig.2: N/PMOS LaD trend. (a) ldsat and SA correlation
As shown in Fig.l, LOD, DPS, ASE and WPE are defined (b) Vtsat and SA correlation
 There should be other mechanisms. NMOS LOD trend is
likely due to dopant distribution. The species we used in
source/drain implantation is easy to diffuse out at the AA edge.
With the reduction of SA, Phosphorous loss at AA edge has a
larger impact on the channel, which results in smaller Idsat and
larger Vtsat.
PMOS LOD effect is more complicated than NMOS,
because eSiGe is used on source/drain to improve the hole
mobility and device performance. For PMOS LOD trend, both
Vtsat and Idsat decrease with the reduction of SA size, which
cannot be explained only by STI stress and dopant loss like
NMOS. eSiGe plays a significant role in the PMOS LOD trend.
When SA decreases, AA shrinks along channel direction,
which brings three results. First, the eSiGe volume becomes
less and compressive stress is weaker. As a result, PMOS
device performance has degraded and Idsat drops. Second,
with the reduction of SA size, eSiGe profile has changed. Fig.3
shows the PMOS eSiGe cross-section pictures of TCAD
simulation as to small SA and large SA device. The pictures
show that eSiGe profile of small SA device is more tapered
than large SA device. The more tapered eSiGe leads to deeper
source/drain implantation and worse short channel effect. As a
result, Vtsat drops and Idsat increases quickly. Finally, the
weaker compressive stress and worse short channel effect from
eSiGe make both Idsat and Vtsat drop with the reduction of
PMOS SA size, as shown in LOD trend. In addition, they make
PMOS performance of small SA device degraded compared
with large SA device, as shown in FigA.
The LOD trends also show that only the first two SA
devices have a big difference, whether it is for NMOS or for
PMOS. From the third SA size, the trend is almost flat. It is
because the stress and dopant distribution have little effects on
the channel when STI edge has a large space to the channel
gate.
(a) (b)
Fig. 3: PMOS eSiGe cross-section pictures of
simulation. (a) small SA device (b) large SA device
1.E+03 ,------,
• channel length or channel width direction, electrical parameters
"§ 1.E+02
� . � •
.�
-e
"
� ...
..
.
� 1.E+Ol
. correlation. The data show that with the reduction of AA
" .. �
• .small SA_PMOS
• large SA_PMOS
1.'.00 +---�����----I
10 II 12 13 H 15 16
IOSAT (arbitrary unit)
17 18 19 20
Fig.4: PMOS ldsat vs. loff plot of small SA and large SA
device
Dummy poly spacing effect
As shown in Fig.l, for different poly spacing, device
electrical parameters may change, which is called DPS effect.
In this paper, we focus on studying the first dummy poly and
gate poly spacing. In addition, the dummy poly of two sides of
the gate is symmetrical.
Fig.5 shows N/PMOS electrical parameters and DPS
correlation. With the reduction of DPS, NMOS Idsat decreases
and Vtsat increases. PMOS has the similar trend with NMOS,
but the trend is very weak compared with NMOS.
The study focuses on small SA device and the first dummy
poly stands on STI instead of the AA. With the reduction of
DPS, STI stress has no obvious change. So NMOS DPS trend is
likely caused by stress memorization technique (SMT) and
contact etch stop layers (CESL). It is well known that SMT and
CESL are two general methods to improve NMOS device
performance. SMT is a method to introduce a tensile stress
layer to NMOS transistors. The stress is transferred into the
underlying source/drain regions after the thermal anneal [I].
Another common source engineered stress is CESL which has
usually tensile stress. When poly spacing is reduced, tensile
stress from both SMT and CESL tends to decrease, which
degrades the NMOS Idsat and performance.
(a) (b)
Fig.5: PMOS electrical parameters and DPS correlation.
(a) ldsat and DPS correlation. (b) Vtsat and DPS
For PMOS, it is hard to explain the similar DPS trend with
NMOS. But the Idsat gap of different poly spacing is very small
and trend is very weak, so does Vtsat. It further indicates eSiGe
is a crucial factor for the PMOS LPE trends. When poly
spacing is reduced, AA has not changed for small SA transistor,
which keeps eSiGe volume and profile same. As a result, the
trend for different DPS is not obvious.
In addition, dopant redistribution should be considered.
Poly height shadowing effect and photo resist shadowing effect
should have influence on DPS trend. But they should be
reAD
secondary effects.
Active area spacing effect
As shown in Fig.l, for different AA spacing whether along
may change, which is called ASE.
Fig.6 shows N/PMOS electrical parameters and ASE
spacing, NMOS Idsat decreases and Vtsat increases, but PMOS
Idsat and Vtsat decrease whether along channel length or along
channel width direction.
NMOS ASE trend should be caused by STI stress. When
AA spacing is reduced, STI volume becomes less and tensile
stress is weakened, which is bad for NMOS whether along
channel length or channel width direction. It results in Idsat called well proximity effect (WPE).
decrease and device performance degradation, as shown in Fig.8 shows N/PMOS electrical parameters and WPE
Fig.6 and Fig.7. correlation. With the reduction of well to AA edge spacing,
NMOS Vtsat increases and Idsat decreases. It can be explained
by the mechanism of WPE as shown in Fig.9. Well implant ions
scattering at the well photo resist edge introduce extra dopant
atoms in the silicon near the well edge. As the well edge
approaches the MOSFET AA, the dopant concentration will
increase, which causes an increase of threshold voltage and a
reduction of Idsat [7]-[9]. In addition, extra dopant atoms will
lead to mobility degradation, which results in worse device
(a) (b) performance, as shown in Fig.IO.
1.5 -------,

10 100 10 100
ASE.lon,ctt.nn.lwldthdlr.ctlon (.rbltl'lryunlt)

(c) (d)
Fig 6: N/PMOS electrical parameters and ASE (a) (b)
correlation. (a) idsat and ASE correlation along channel Fig8:NMOS electrical parameters and WPE correlation.
length direction. (b) Vtsat and ASE correlation along (a) Jdsat and WPE correlation, (b) Vtsat and WPE
channel length direction. (c) idsat and ASE correlation correlation

.
along channel width direction. (d) Vtsat and ASE

JUll1u\
correlation along width direction.

.�'
1£.02 __________-,
-

. �. :-:
� - .
II ... , .
.
. -
�
• �mOlIl AA �clr�LNMOS
.IOIf8� AA �KinLNMOS Active area
" ...
10 1) 12 13 U 15 16 17 18 19 20
IOSAT (.rbltrtry unh)

Fig 7: NMOS idsat vs. JojJ plot of AA spacing along

. ·
channel width direction Fig9: mechanism ofWPE
I.'''' --------,
When AA spacing is reduced, weaker STI tensile stress is
bad along channel length direction and is good along channel • -
width direction for PMOS. But in fact, PMOS ASE trends are '§ 1.E+02 •• • !111-
..

similar for the two directions. The root cause is that the
dominant factor of PMOS ASE is not STI stress, but likely the
i� 1.£+01
• •
• �r ·
eSiGe stress. We suspect that with the reduction of AA spacing, • small well toM edgE' spacinlLNMOS
• large well to AA edge SpaCinlLNMOS
AA has a larger pattern density within the same area. I.E.oo
10 11 12 13 H 15 16 17 IS 19 :::.'0
Consequently, eSiGe has a larger pattern density, which brings IOSAT(arbitrary unit)

two results. The first one is less eSiGe volume which leads to
weaker compressive stress. The second one is the more tapered
eSiGe profIle in smaller SA transistor which leads to deeper
source/drain implantation and worse short channel effect, as
mentioned before. The weaker compressive stress makes Idsat
decrease. The worse short channel effect makes Vtsat drop and
Idsat increase. Finally, both Vtsat and Idsat drop as shown in
Fig.6.
Well proximity effect
As shown in Fig.I, for the different well to AA edge
spacing, whether along channel length or along channel width
direction, device electrical parameters may change, which is
Fig] 0: NMOS Jdsat vs. JojJ plot ofdifferent well to AA edge
spacing
Compared to NMOS, PMOS WPE trend is weaker. This
could be due to less scattering of well and Vt implantation
species and/or less impact on carrier mobility in PMOS.
SUMMARY
Layout proximity effects for 28nm PolySiON have been
studied systematically, including LOD, DPS, ASE and WPE
effects. We explored the mechanisms behind these LPEs and
proposed physical models that can explain the LPEs' impacts
on transistor electrical behavior. We found that for NMOS, the
change of dopant distribution and mobility at different
transistor geometric parameters are the two major factors that
cause LPEs. For PMOS, although dopant distribution and STI
stress still have influence on the electrical parameters, eSiGe
stressor plays a more important role in LOD and ASE effects.
When the eSiGe volume decreases, compressive stress
becomes weaker. As a result, Idsat decreases and device
performance degrades. When the eSiGe profile becomes
tapered, PMOS source/drain implantation gets deeper. It leads
to worse short channel effect and Vtsat drop. If the eSiGe
process and the related junction engineering can be improved,
PMOS LPE trends should be more flat.

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