SJBIT

Analog and Digital Electronics 15CS32
Analog and Digital Electronics

[As per Choice Based Credit System (CBCS) scheme]
(Effective from the academic year 2015 -2016)
SEMESTER – III
Subject Code 15CS32 IA Marks 20

Number of Lecture Hours/Week 04 Exam Marks 80
Total Number of Lecture Hours 50 Exam Hours 03
CREDITS - 04
Course objectives:
This course will enable students to
- Recall and Recognize construction and characteristics of JFETs and MOSFETs.
- Describe, Differentiate and Apply JFETs and MOSFETs
- Define, Demonstrate and Analyse Operational Amplifier circuits and their applications
- Describe, Illustrate and Analyse Combinational Logic circuits, Simplification of Algebraic
Equations using Karnaugh Maps and Quine McClusky Techniques.
- Define, Describe and Design Decoders, Encoders, Digital multiplexers, Adders and
Subtractors,Binary comparators, Latches and Master-Slave Flip-Flops.
- Describe, Demonstrate, Analyse and Design Synchronous and Asynchronous Sequential
Circuits, State diagrams, Registers and Counters, A/D and D/A converters.
Module -1
Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences between
JFETs and MOSFETs, Biasing MOSFETs, FET Applications, CMOS Devices. Wave-
Shaping Circuits: Integrated Circuit(IC) Multivibrators. Introduction to Operational
Amplifier: Ideal v/s practical Opamp, Performance Parameters, Operational Amplifier
Application Circuits:Peak Detector Circuit, Comparator, Active Filters, Non-Linear
Amplifier, Relaxation Oscillator, Current-To-Voltage Converter, Voltage-To-Current
Converter.
Dept .of CSE, SJBIT Page 1

Module -2
The Basic Gates: Review of Basic Logic gates, Positive and Negative Logic, Introduction to
HDL. Combinational Logic Circuits: Sum-of-Products Method, Truth Table to Karnaugh
Map, Pairs Quads, and Octets, Karnaugh Simplifications, Don‟t-care Conditions, Product-of-
sums Method, Product-ofsums simplifications, Simplification by Quine-McCluskyMethod,
Hazards and Hazard covers, HDL Implementation Models.
Module – 3
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD to Decimal

Decoders, Seven Segment Decoders, Encoders, Exclusive-OR Gates, Parity Generators and
Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays,
HDL Implementation of Data Processing Circuits. Arithmetic Building Blocks, Arithmetic
Logic Unit Flip-Flops: RS Flip-Flops, Gated Flip-Flops, Edge-triggered RS FLIP-FLOP,
Edgetriggered D FLIP-FLOPs, Edge-triggered JK FLIP-FLOPs.
Module-4
Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce

Circuits, Various Representation of FLIP-FLOPs, HDL Implementation of FLIP-FLOP.
Registers: Types of Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In -
Serial Out, Parallel In - Parallel Out, Universal Shift Register, Applications of Shift
Registers, Register implementation in HDL.Counters: Asynchronous Counters, Decoding
Gates, Synchronous Counters, Changing the Counter Modulus.
Module-5
Counters: Decade Counters, Pre settable Counters, Counter Design as a Synthesis problem,
A Digital Clock, Counter Design using HDL. D/A Conversion and A/D Conversion:
Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A Accuracy and
Resolution, A/D Converter- Simultaneous Conversion, A/D Converter-Counter Method,

Continuous A/D Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy
and Resolution.
Text Books:
1. Anil K Maini, VarshaAgarwal: Electronic Devices and Circuits, Wiley, 2012.

2. Donald P Leach, Albert Paul Malvino&GoutamSaha: Digital Principles and Applications,
7th Edition, Tata McGraw Hill, 2014
Course outcomes:
After studying this course, students will be able to:
· Acquire knowledge of - JFETs and MOSFETs , Operational Amplifier circuits and their
applications
- Combinational Logic, Simplification Techniques using Karnaugh Maps, Quine McClusky
Technique.
- Operation of Decoders, Encoders, Multiplexers, Adders and Subtractors.
- Working of Latches, Flip-Flops, Designing Registers, Counters, A/D and D/A Converters
· Analyse the performance of - JFETs and MOSFETs , Operational Amplifier circuits
- Simplification Techniques using Karnaugh Maps, Quine McClusky Technique.
- Synchronous and Asynchronous Sequential Circuits.
· Apply the knowledge gained in the design of Counters, Registers and A/D & D/A
converters
Reference Books:
1. Stephen Brown, ZvonkoVranesic: Fundamentals of Digital Logic Design with VHDL,

2nd Edition,Tata McGraw Hill, 2005.
2. R D Sudhaker Samuel: Illustrative Approach to Logic Design, Sanguine-Pearson,
2010.
3. M Morris Mano: Digital Logic and Computer Design, 10th Edition, Pearson, 2008.

Table of contents
Module -1
1.1 Field Effect Transistors: 8 - 42

1.1.1 Junction Field Effect Transistors
1.1.2 MOSFETs
1.1.3 Differences between JFETs and MOSFETs
1.1.4 Biasing MOSFETs
1.1.5 FET Applications
1.1.6 CMOS Devices.
1.2. Wave-Shaping Circuits:
1.2.1 Integrated Circuit(IC) Multivibrators
1.3 Introduction to Operational Amplifier:
1.3.1 Ideal v/s practical Opamp, Performance Parameters
1.4. Operational Amplifier Application Circuits:
1.4.1 Peak Detector Circuit
1.4.2 Comparator
1.4.3 Active Filters
1.4.4 Non-Linear Amplifier
1.4.5 Relaxation Oscillator
1.4.6 Current-To-Voltage Converter
1.4.7 Voltages-To-Current Converter
Module -2
2.1 The Basic Gates: 43 - 65

2.1.1 Review of Basic Logic gates
2.1.2 Positive and Negative Logic
2.1.3 Introduction to HDL
2.2 Combinational Logic Circuits:
2.2.1 Sum-of-Products Method
2.2.2 Truth Table to Karnaugh Map
2.2.3 Pairs Quads, and Octets, Karnaugh Simplifications

2.2.4 Don‟t-care Conditions, Product-of-sums Method

2.2.5 Product-ofsums simplifications
2.2.6 Simplification by Quine-McCluskyMethod
2.2.7Hazards and Hazard covers
2.2.8 HDL Implementation Models
Module – 3
3.1 Data-Processing Circuits: 66 - 89

3.1.1 Multiplexers, Demultiplexers
3.1.2 1-of-16 Decoder
3.1.3 BCD to Decimal Decoders
3.1.4 Seven Segment Decoders
3.1.5 Encoders
3.1.6 Exclusive-OR Gates
3.1.7 Parity Generators and Checkers
3.1.8 Magnitude Comparator
3.1.9 Programmable Array Logic
3.1.10 Programmable Logic Arrays
3.1.11 HDL Implementation of Data Processing Circuits
3.1.12 Arithmetic Building Blocks
3.1.13 Arithmetic Logic Unit
3.2 Flip-Flops:
3.2.1 RS Flip-Flops
3.2.2 Gated Flip-Flops
3.2.3 Edge-triggered RS FLIP-FLOP
3.2.4 Edge triggered D FLIP-FLOPs
3.2.5 Edge-triggered JK FLIP-FLOPs

Module-4
4.1 Flip- Flops: 90 - 109

4.1.1. FLIP-FLOP Timing
4.1.2 JK Master-slave FLIP-FLOP
4.1.3 Switch Contact Bounce Circuits
4.1.4 Various Representation of FLIP-FLOPs
4.1.5 HDL Implementation of FLIP-FLOP
4.2 Registers:
4.2.1 Types of Registers
4.2.2 Serial In - Serial Out
4.2.3 Serial In - Parallel out
4.2.4 Parallel In - Serial Out
4.2.5 Parallel In - Parallel Out
4.2.6 Universal Shift Register
4.2.7 Applications of Shift Registers
4.2.8 Register implementation in HDL
4.3 Counters:
4.3.1 Asynchronous Counters
4.3.2 Decoding Gates
4.3.3 Synchronous Counters
4.3.4 Changing the Counter Modulus
Module-5
5.1 Counters: 110-124
5.1.1 Decade Counters
5.1.2 Pre settable Counters
5.1.3 Counter Design as a Synthesis problem
5.1.4 A Digital Clock, Counter
5.1.5 Design using HDL
5.2 D/A Conversion and A/D Conversion:
5.2.1 Variable, Resistor Networks
5.2.2 Binary Ladders

5.2.3 D/A Converters

5.2.4 D/A Accuracy and Resolution
5.2.5 A/D Converter- Simultaneous Conversion
5.2.6 A/D Converter-Counter Method
5.2.7 Continuous A/D Conversion
5.2.8 A/D Techniques
5.2.9 Dual-slope A/D Conversion
5.2.10 A/D Accuracy and Resolution

Module -1
1.1 Field Effect Transistors:
In the Bipolar Junction Transistor tutorials, we saw that the output Collector current of
the transistor is proportional to input current flowing into the Base terminal of the device,
thereby making the bipolar transistor a "CURRENT" operated device (Beta model). The
Field Effect Transistor, or simply FET however, uses the voltage that is applied to their
input terminal, called the Gate to control the current flowing through them resulting in the
output current being proportional to the input voltage. As their operation relies on an electric
field (hence the name field effect) generated by the input Gate voltage, this then makes the
Field Effect Transistor a "VOLTAGE" operated device.
Typical Field Effect Transistor
The Field Effect Transistor is a three terminal unipolar semiconductor device that has very
similar characteristics to those of their Bipolar Transistor counterparts ie, high efficiency,
instant operation, robust and cheap and can be used in most electronic circuit applications to
replace their equivalent bipolar junction transistors (BJT) cousins.
Field effect transistors can be made much smaller than an equivalent BJT transistor and along
with their low power consumption and power dissipation makes them ideal for use in
integrated circuits such as the CMOS range of digital logic chips.
We remember from the previous tutorials that there are two basic types of Bipolar Transistor
construction, NPN and PNP, which basically describes the physical arrangement of the P-
type and N-type semiconductor materials from which they are made. This is also true of

FET's as there are also two basic classifications of Field Effect Transistor, called the N-
channel FET and the P-channel FET.
The field effect transistor is a three terminal device that is constructed with no PN-junctions
within the main current carrying path between the Drain and the Source terminals, which
correspond in function to the Collector and the Emitter respectively of the bipolar transistor.
The current path between these two terminals is called the "channel" which may be made of
either a P-type or an N-type semiconductor material. The control of current flowing in this
channel is achieved by varying the voltage applied to the Gate. As their name implies,
Bipolar Transistors are "Bipolar" devices because they operate with both types of charge
carriers, Holes and Electrons. The Field Effect Transistor on the other hand is a "Unipolar"
device that depends only on the conduction of electrons (N-channel) or holes (P-channel).
The Field Effect Transistor has one major advantage over its standard bipolar transistor
cousins, in that their input impedance, ( Rin ) is very high, (thousands of Ohms), while the
BJT is comparatively low. This very high input impedance makes them very sensitive to
input voltage signals, but the price of this high sensitivity also means that they can be easily
damaged by static electricity. There are two main types of field effect transistor, the Junction
Field Effect Transistor or JFET and the Insulated-gate Field Effect Transistor or
IGFET), which is more commonly known as the standard Metal Oxide Semiconductor
Field Effect Transistor or MOSFET for short.
1.1.1 Junction Field Effect Transistors
The Junction Field Effect Transistor (JUGFET or JFET) has no PN-junctions but instead
has a narrow piece of high-resistivity semiconductor material forming a "Channel" of either
N-type or P-type silicon for the majority carriers to flow through with two ohmic electrical
connections at either end commonly called the Drain and the Source respectively.
There are two basic configurations of junction field effect transistor, the N-channel JFET and
the P-channel JFET. The N-channel JFET's channel is doped with donor impurities meaning
that the flow of current through the channel is negative (hence the term N-channel) in the
form of electrons. Likewise, the P-channel JFET's channel is doped with acceptor impurities
meaning that the flow of current through the channel is positive (hence the term P-channel) in
the form of holes. N-channel JFET's have a greater channel conductivity (lower resistance)

than their equivalent P-channel types, since electrons have a higher mobility through a
conductor compared to holes. This makes the N-channel JFET's a more efficient conductor
compared to their P-channel counterparts.
We have said previously that there are two ohmic electrical connections at either end of the
channel called the Drain and the Source. But within this channel there is a third electrical
connection which is called the Gate terminal and this can also be a P-type or N-type material
forming a PN-junction with the main channel. The relationship between the connections of a
junction field effect transistor and a bipolar junction transistor are compared below.
Comparison of connections between a JFET and a BJT
Bipolar Transistor Field Effect Transistor

Emitter - (E) >> Source - (S)
Base - (B) >> Gate - (G)
Collector - (C) >> Drain - (D)
The symbols and basic construction for both configurations of JFETs are shown below.
The semiconductor "channel" of the Junction Field Effect Transistor is a resistive path
through which a voltage VDS causes a current ID to flow. The JFET can conduct current
equally well in either direction. A voltage gradient is thus formed down the length of the
channel with this voltage becoming less positive as we go from the Drain terminal to the
Source terminal. The PN-junction therefore has a high reverse bias at the Drain terminal and

a lower reverse bias at the Source terminal. This bias causes a "depletion layer" to be formed
within the channel and whose width increases with the bias.
The magnitude of the current flowing through the channel between the Drain and the Source
terminals is controlled by a voltage applied to the Gate terminal, which is a reverse-biased. In
an N-channel JFET this Gate voltage is negative while for a P-channel JFET the Gate voltage
is positive. The main difference between the JFET and a BJT device is that when the JFET
junction is reverse-biased the Gate current is practically zero, whereas the Base current of the
BJT is always some value greater than zero.
The cross sectional diagram above shows an N-type semiconductor channel with a P-type
region called the Gate diffused into the N-type channel forming a reverse biased PN-junction
and it is this junction which forms the depletion region around the Gate area when no external
voltages are applied. JFETs are therefore known as depletion mode devices. This depletion
region produces a potential gradient which is of varying thickness around the PN-junction
and restrict the current flow through the channel by reducing its effective width and thus
increasing the overall resistance of the channel itself. The most-depleted portion of the
depletion region is in between the Gate and the Drain, while the least-depleted area is
between the Gate and the Source. Then the JFET's channel conducts with zero bias voltage
applied (i.e. the depletion region has near zero width).
With no external Gate voltage ( VG = 0 ), and a small voltage ( VDS ) applied between the
Drain and the Source, maximum saturation current ( IDSS ) will flow through the channel from
the Drain to the Source restricted only by the small depletion region around the junctions.

If a small negative voltage ( -VGS ) is now applied to the Gate the size of the depletion region
begins to increase reducing the overall effective area of the channel and thus reducing the
current flowing through it, a sort of "squeezing" effect takes place. So by applying a reverse
bias voltage increases the width of the depletion region which in turn reduces the conduction
of the channel. Since the PN-junction is reverse biased, little current will flow into the gate
connection. As the Gate voltage ( -VGS ) is made more negative, the width of the channel
decreases until no more current flows between the Drain and the Source and the FET is said
to be "pinched-off" (similar to the cut-off region for a BJT). The voltage at which the channel
closes is called the "pinch-off voltage", ( VP ).
JFET Channel Pinched-off
In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little
or no effect.
JFET Model
The result is that the FET acts more like a voltage controlled resistor which has zero
resistance when VGS = 0 and maximum "ON" resistance ( RDS ) when the Gate voltage is very
negative. Under normal operating conditions, the JFET gate is always negatively biased
relative to the source.

It is essential that the Gate voltage is never positive since if it is all the channel current will
flow to the Gate and not to the Source, the result is damage to the JFET. Then to close the
channel:
 No Gate voltage ( VGS ) and VDS is increased from zero.

 No VDS and Gate control is decreased negatively from zero.
 VDS and VGS varying.
The P-channel Junction Field Effect Transistor operates the same as the N-channel above,
with the following exceptions: 1). Channel current is positive due to holes, 2). The polarity of
the biasing voltage needs to be reversed.
The output characteristics of an N-channel JFET with the gate short-circuited to the source is
given as
Output characteristic V-I curves of a typical junction FET

The voltage VGS applied to the Gate controls the current flowing between the Drain and the
Source terminals. VGS refers to the voltage applied between the Gate and the Source while
VDS refers to the voltage applied between the Drain and the Source. Because a Junction
Field Effect Transistor is a voltage controlled device, "NO current flows into the gate!" then
the Source current ( IS ) flowing out of the device equals the Drain current flowing into it and
therefore ( ID = IS ).
The characteristics curves example shown above, shows the four different regions of
operation for a JFET and these are given as:
 Ohmic Region - When VGS = 0 the depletion layer of the channel is very small and the
JFET acts like a voltage controlled resistor.
 Cut-off Region - This is also known as the pinch-off region were the Gate voltage, VGS is
sufficient to cause the JFET to act as an open circuit as the channel resistance is at
maximum.
 Saturation or Active Region - The JFET becomes a good conductor and is controlled by
the Gate-Source voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no
effect.
 Breakdown Region - The voltage between the Drain and the Source, ( VDS ) is high
enough to causes the JFET's resistive channel to break down and pass uncontrolled
maximum current.
The characteristics curves for a P-channel junction field effect transistor are the same as those
above, except that the Drain current ID decreases with an increasing positive Gate-Source
voltage, VGS.
The Drain current is zero when VGS = VP. For normal operation, VGS is biased to be
somewhere between VP and 0. Then we can calculate the Drain current, ID for any given bias
point in the saturation or active region as follows:
Drain current in the active region.

Note that the value of the Drain current will be between zero (pinch-off) and IDSS (maximum
current). By knowing the Drain current ID and the Drain-Source voltage VDS the resistance of
the channel ( ID ) is given as:
Drain-Source channel resistance.
Where: gm is the "transconductance gain" since the JFET is a voltage controlled device and
which represents the rate of change of the Drain current with respect to the change in Gate-
Source voltage.
1.1.2 MOSFETs
The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET
in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main
semiconductor n-channel or p-channel by a very thin layer of insulating material usually
silicon dioxide, commonly known as glass.
This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor.
The isolation of the controlling Gate makes the input resistance of the MOSFET extremely
high way up in the Mega-ohms ( MΩ ) region thereby making it almost infinite.
As the Gate terminal is isolated from the main current carrying channel “NO current flows
into the gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor
were the current flowing through the main channel between the Drain and Source is
proportional to the input voltage. Also like the JFET, the MOSFETs very high input
resistance can easily accumulate large amounts of static charge resulting in the MOSFET
becoming easily damaged unless carefully handled or protected.
Like the previous JFET tutorial, MOSFETs are three terminal devices with a Gate, Drain and
Source and both P-channel (PMOS) and N-channel (NMOS) MOSFETs are available. The
main difference this time is that MOSFETs are available in two basic forms:
 Depletion Type – the transistor requires the Gate-Source voltage, ( VGS ) to switch
the device “OFF”. The depletion mode MOSFET is equivalent to a “Normally
Closed” switch.

 Enhancement Type – the transistor requires a Gate-Source voltage, ( VGS ) to

switch the device “ON”. The enhancement mode MOSFET is equivalent to a
“Normally Open” switch.
The symbols and basic construction for both configurations of MOSFETs are shown
below.
The four MOSFET symbols above show an additional terminal called the Substrate and is not
normally used as either an input or an output connection but instead it is used for grounding
the substrate. It connects to the main semiconductive channel through a diode junction to the
body or metal tab of the MOSFET. Usually in discrete type MOSFETs, this substrate lead is
connected internally to the source terminal. When this is the case, as in enhancement types it
is omitted from the symbol for clarification.
The line between the drain and source connections represents the semiconductive channel. If
this is a solid unbroken line then this represents a “Depletion” (normally-ON) type MOSFET

as drain current can flow with zero gate potential. If the channel line is shown dotted or
broken it is an “Enhancement” (normally-OFF) type MOSFET as zero drain current flows
with zero gate potential. The direction of the arrow indicates whether the conductive channel
is a p-type or an n-type semiconductor device.
Basic MOSFET Structure and Symbol
The construction of the Metal Oxide Semiconductor FET is very different to that of the
Junction FET. Both the Depletion and Enhancement type MOSFETs use an electrical field
produced by a gate voltage to alter the flow of charge carriers, electrons for n-channel or
holes for P-channel, through the semiconductive drain-source channel. The gate electrode is
placed on top of a very thin insulating layer and there are a pair of small n-type regions just
under the drain and source electrodes.
that the gate of a junction field effect transistor, JFET must be biased in such a way as to
reverse-bias the pn-junction. With a insulated gate MOSFET device no such limitations apply
so it is possible to bias the gate of a MOSFET in either polarity, positive (+ve) or negative (-
ve).
This makes the MOSFET device especially valuable as electronic switches or to make logic
gates because with no bias they are normally non-conducting and this high gate input
resistance means that very little or no control current is needed as MOSFETs are voltage
controlled devices. Both the p-channel and the n-channel MOSFETs are available in two
basic forms, the Enhancement type and the Depletion type.

Depletion-mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement mode types is
normally switched “ON” (conducting) without the application of a gate bias voltage. That is
the channel conducts when VGS = 0 making it a “normally-closed” device. The circuit symbol
shown above for a depletion MOS transistor uses a solid channel line to signify a normally
closed conductive channel.
For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will deplete
(hence its name) the conductive channel of its free electrons switching the transistor “OFF”.
Likewise for a p-channel depletion MOS transistor a positive gate-source voltage, +VGS will
deplete the channel of its free holes turning it “OFF”.
In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and
more current. While a -VGS means less electrons and less current. The opposite is also true for
the p-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed”
switch.
Depletion-mode N-Channel MOSFET and circuit Symbols

The depletion-mode MOSFET is constructed in a similar way to their JFET transistor

counterparts were the drain-source channel is inherently conductive with the electrons and
holes already present within the n-type or p-type channel. This doping of the channel
produces a conducting path of low resistance between the Drain and Source with zero Gate
bias.
Enhancement-mode MOSFET
The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the
depletion-mode type. Here the conducting channel is lightly doped or even undoped making
it non-conductive. This results in the device being normally “OFF” (non-conducting) when
the gate bias voltage, VGS is equal to zero. The circuit symbol shown above for an
enhancement MOS transistor uses a broken channel line to signify a normally open non-
conducting channel.
For the n-channel enhancement MOS transistor a drain current will only flow when a gate
voltage ( VGS ) is applied to the gate terminal greater than the threshold voltage ( V TH ) level
in which conductance takes place making it a transconductance device.
The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons
towards the oxide layer around the gate thereby increasing or enhancing (hence its name) the
thickness of the channel allowing more current to flow. This is why this kind of transistor is
called an enhancement mode device as the application of a gate voltage enhances the channel.
Increasing this positive gate voltage will cause the channel resistance to decrease further
causing an increase in the drain current, ID through the channel. In other words, for an n-
channel enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS
turns the transistor “OFF”. Then, the enhancement-mode MOSFET is equivalent to a
“normally-open” switch.

The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device
is “OFF” and the channel is open. The application of a negative (-ve) gate voltage to the p-
type eMOSFET enhances the channels conductivity turning it “ON”. Then for an p-channel
enhancement mode MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the
transistor “ON”.
Enhancement-mode N-Channel MOSFET and Circuit Symbols
Enhancement-mode MOSFETs make excellent electronics switches due to their low “ON”
resistance and extremely high “OFF” resistance as well as their infinitely high input
resistance due to their isolated gate. Enhancement-mode MOSFETs are used in integrated
circuits to produce CMOS type Logic Gates and power switching circuits in the form of as

PMOS (P-channel) and NMOS (N-channel) gates. CMOS actually stands for Complementary
MOS meaning that the logic device has both PMOS and NMOS within its design.
The MOSFET Amplifier
Just like the previous Junction Field Effect transistor, MOSFETs can be used to make single
stage class “A” amplifier circuits with the enhancement mode n-channel MOSFET common
source amplifier being the most popular circuit. The depletion mode MOSFET amplifiers are
very similar to the JFET amplifiers, except that the MOSFET has a much higher input
impedance.
This high input impedance is controlled by the gate biasing resistive network formed by R1
and R2. Also, the output signal for the enhancement mode common source MOSFET
amplifier is inverted because when VG is low the transistor is switched “OFF” and VD (Vout)
is high. When VG is high the transistor is switched “ON” and VD (Vout) is low as shown.
Enhancement-mode N-Channel MOSFET Amplifier
The DC biasing of this common source (CS) MOSFET amplifier circuit is virtually identical
to the JFET amplifier. The MOSFET circuit is biased in class A mode by the voltage divider
network formed by resistors R1 and R2. The AC input resistance is given as
RIN = RG = 1MΩ.
Metal Oxide Semiconductor Field Effect Transistors are three terminal active devices made
from different semiconductor materials that can act as either an insulator or a conductor by
the application of a small signal voltage. The MOSFETs ability to change between these two
states enables it to have two basic functions: “switching” (digital electronics) or

“amplification” (analogue electronics). Then MOSFETs have the ability to operate within
three different regions:
 Cut-off Region – with VGS < Vthreshold the gate-source voltage is lower than the
threshold voltage so the MOSFET transistor is switched “fully-OFF” and IDS = 0, the
transistor acts as an open circuit
 Linear (Ohmic) Region – with VGS > Vthreshold and VDS < VGS the transistor is in its
constant resistance region and behaves as a voltage-controlled resistor whose resistive
value is determined by the gate voltage, VGS
 Saturation Region – with VGS > Vthreshold the transistor is in its constant current
region and is switched “fully-ON”. The current IDS = maximum as the transistor acts
as a closed circuit
MOSFET Summary
The Metal Oxide Semiconductor Field Effect Transistor, or MOSFET for short, has an
extremely high input gate resistance with the current flowing through the channel between
the source and drain being controlled by the gate voltage. Because of this high input
impedance and gain, MOSFETs can be easily damaged by static electricity if not carefully
protected or handled.
MOSFET‟s are ideal for use as electronic switches or as common-source amplifiers as their
power consumption is very small. Typical applications for metal oxide semiconductor field
effect transistors are in Microprocessors, Memories, Calculators and Logic CMOS Gates etc.
Also, notice that a dotted or broken line within the symbol indicates a normally “OFF”
enhancement type showing that “NO” current can flow through the channel when zero gate-
source voltage VGS is applied.
. For p-channel types the symbols are exactly the same for both types except that the arrow
points outwards. This can be summarised in the following switching table.
VGS = VGS = VGS =

MOSFET type
+ve 0 -ve
N-Channel Depletion ON ON OFF
N-Channel Enhancement ON OFF OFF
P-Channel Depletion OFF ON ON
P-Channel Enhancement OFF OFF ON

1.1.3 Differences between JFETs and MOSFETs
1. Comparing to the JFET, MOSFETs are easier to fabricate.

2. JFETs are operated only in the depletion mode. The depletion type MOSFET may be
operated in both depletion and enhancement mode.
3. The output characteristics of JFET is flatter than the MOSFET. because the drain
resistance in the JFET (1 MΩ) is higher than the MOSFET (50kΩ)
4. The gate leakage current of JFET is of the order of 10-9A. For MOSFET, the gate
leakage current will be of the order of 10-12A.
5. The input resistance of JFET is in the range of 108Ω. For MOSFET, the input
resistance will be in the range of 1010 to 1015Ω.
6. Because of their advantages, MOSFETs are widely used in VLSI circuits than
JFET. As the MOSFET is susceptible to overload voltages, special care should be
taken during installation.
7. MOSFET has zero offset voltage. The source and drain terminals can be interchanged
(so it is called as symmetrical device). Because of these two characteristics the
MOSFET is widely used in analog signal switching.
8. In JFET, the transverse electric field across the reverse biased PN junction controls
the conductivity of the channel. In MOSFET, the transverse electric field induced
across an insulating layer deposited on the semiconductor material controls the
conductivity of the channel.
1.1.4 Biasing MOSFETs

Biasing: Creating the circuit to establish the desired DC voltages and currents for the
operation of the amplifier
Four common ways:
1. Biasing by fixing VGS
2. Biasing by fixing VG and connecting a resistance in the Source
3. Biasing using a Drain-to-Gate Feedback Resistor
4. Biasing Using a Constant-Current Source

1.1.5 FET Applications
FET has a very high input impedance (100 Mega ohm in case of JFETs and 10 4 to 109 Mega
Ohm in case of MOSFETs), the major shortcomings of an ordinary transistor i.e. low input
impedance with consequent of loading of signal source is eliminated in FET. Hence FET is
an ideal device for use in almost every application in which transistors can be used. FETs are
widely used as input amplifiers in oscilloscopes, electronic voltmeters and other measuring
and testing equipment because of their high input impedance.
 As a FET chip occupies very small space as compared to BJT chip, FETs are widely
used in ICs.
 FETs are used as voltage-variable resistors (WRs) in operational amplifiers (op-amps)
and tone controls etc, for mixer operation on FM and TV receivers and in logic
circuits.
 FETs are generally used in digital switching circuits though their operating speed is
lower.
Applications of FET:
1. Low Noise Amplifier. Noise is an undesirable disturbance super-imposed on a useful

signal. Noise interferes with the information contained in the signal; the greater the noise, the
less the information. For instance, the noise in radio-receivers develops crackling and hissing
which sometimes completely masks the voice or music. Similarly, the noise in TV receivers
produces small white or black spots on the picture; a severe
noise may wipe out the picture. Noise is independent of the signal strength because it exists
even when the signal is off.
Every electronic device produces certain amount of noise but FET is a device which causes
very little noise. This is especially important near the front-end of the receivers and other
electronic equipment because the subsequent stages amplify front-end noise along with the
signal. If FET is used at the front-end, we get less amplified noise (disturbance) at the final
output.

2. Buffer Amplifier.
A buffer amplifier is a stage of amplification that isolates the preceding stage from the
following stage. Source follower (common drain) is. used as a buffer amplifier. Because of
the high input impedance and low output impedance a FET acts an excellent buffer amplifier,
as shown in figure. Owing to high input impedance almost all the output voltage of the
preceding stage appears at the input of the buffer amplifier and owing to low output
impedance all the output voltage from the buffer amplifier reaches the input of the following
stage, even there may be a small load resistance.
3. Cascode Amplifier. Circuit diagram for a cascode amplifier using FET is shown in
figure. A common source amplifier drives a common gate amplifier in it.
Cascode amplifier circuit

The cascode amplifier has the same voltage gain as a common source (CS) amplifier. The
main advantage of cascode connection is its low input capacitance which is considerably less
than the input capacitance of a CS amplifier. It has high input resistance which is also a
desirable feature.
4. Analog Switch. FET as an analog switch is shown in figure. When no gate voltage is
applied to the FET i.e. VGS = 0, FET becomes saturated and it behaves like a small resistance
usually of the value of less than 100 ohm and, therefore, output voltage becomes equal to
VOUT = {RDS/ (RD + RDS (ON))}* Vin
Since RD is very large in comparison to RDS 0N), so Vout can be taken equal to zero.When a
negative voltage equal to VGS (OFF) is applied to the gate, the FET operates in the cut-off
region and it acts like a very high resistance usually of some mega ohms. Hence output
voltage becomes nearly equal to input voltage.
5. Chopper. A direct-coupled amplifier can be built by leaving out the coupling and bypass
capacitors and connecting the output of each stage directly to the input of next stage. Thus
direct current is coupled, as well as alternating current. The major drawback of this method is
occurrence of drift, a slow shift in the final output voltage produced by supply transistor, and
temperature variations.
The drift problem can be overcome by employing chopper amplifier as illustrated in figure.

Chopper Amplifier
(a). Here input dc voltage is chopped by a switching circuit. The output of chopper is a square
wave ac signal having peak value equal to that of input dc voltage, VDC. This ac signal can be
amplified by a conventional ac amplifier without any problem of drift. Amplified output can
then be „peak detected‟ to recover the amplified dc signal.
Square wave is applied to the gate of a FET analog switch to make it operate like a chopper,
as illustrated in other figure. The gate square wave is negative-going swing from 0 V to at
least VGS (off)- This alternately saturates and cuts-off the JFET. Thus output voltage is a
square wave varying from +VDC to zero volt alternately.
If the input signal is a low-frequency ac signal, it gets chopped into the ac waveform as
shown in last figure (c). This chopped signal can now be amplified by an ac amplifier that is
drift free. The amplified signal can then be peak-detected to recover the original input low
frequency ac signal. Thus both dc and low frequency ac signals can be amplified by using a
chopper amplifier.
6. Multiplexer.

FET multiplexer
An analog multiplexer, a circuit that steers one of the input signals to the output line, is
shown in figure. In this circuit each JFET acts as a single-pole single-throw switch. When the
control signals (Vv V2 and V3) are more negative than VGS(0FF) all input signals are blocked.
By making any control voltage equal to zero, one of the inputs can be transmitted to the
output. For instance, when Vx is zero, the signal obtained at the output will be sinusoidal.
Similarly when V2 is zero, the signal obtained at the output will be triangular and when V3 is
zero, the output signal will be square-wave one. Normally, only one of the control signals is
zero.
7. Current Limiter.
JFET current Limiter
JFET current limiting circuit is shown in figure. Almost all the supply voltage therefore
appears across the load. When the load current tries to increase to an excessive level (may be
due to short-circuit or any other reason), the excessive load current forces the JFET into
active region, where it limits the current to 8 mA. The JFET now acts as a current source and
prevents excessive load current.

A manufacturer can tie the gate to the source and package the JFET as a two terminal device.
This is how constant-current diodes are made. Such diodes are also called current-regulator
diodes.
8. Phase Shift Oscillators.
FET-phase shift oscillator
JFET can incorporate the amplifying action as well as feedback action. It, therefore, acts well
as a phase shift oscillator. The high input impedance of FET is especially very valuable in
phase-shift oscillators in order to minimize the loading effect. A typical phase shift oscillator
employing N-channel JFET is shown in figure.
1.1.6 CMOS Devices.
Complementary Metal-Oxide-Silicon circuits require an nMOS and pMOS transistor

technology on the same substrate. To this end, an n-type well is provided in the p-type

substrate. Alternatively one can use a p-well or both an n-type and p-type well in a low-doped
substrate. The gate oxide, poly-silicon gate and source-drain contact metal are typically
shared between the pMOS and nMOS technology, while the source-drain implants must be
done separately. Since CMOS circuits contain pMOS devices, which are affected by the
lower hole mobility, CMOS circuits are not faster than their all-nMOS counter parts. Even
when scaling the size of the pMOS devices so that they provide the same current, the larger
pMOS device has a higher capacitance.
The CMOS advantage is that the output of a CMOS inverter can be as high as the power
supply voltage and as low as ground. This large voltage swing and the steep transition
between logic levels yield large operation margins and therefore also a high circuit yield. In
addition, there is no power dissipation in either logic state. Instead the power dissipation
occurs only when a transition is made between logic states. CMOS circuits are therefore not
faster than nMOS circuits but are more suited for very/ultra large-scale integration
(VLSI/ULSI).
CMOS circuits have one property, which is very undesirable, namely latchup. Latchup occurs
when four alternating p-type and n-type regions are brought in close proximity. Together they
form two bipolar transistors, one npn and one pnp transistor. The base of each transistor is
connected to the collector of the other, forming a cross-coupled thyristor-like combination.
As a current is applied to the base of one transistor, the current is amplified by the transistor
and provided as the base current of the other one. If the product of the current gain of both
transistors is larger than unity, the current through both devices increases until the series
resistances of the circuit limits the current. Latchup therefore results in excessive power
dissipation and faulty logic levels in the gates affected. In principle, this effect can be
eliminated by separating the n-type and p-type device. A more effective and less space-
consuming solution is the use of trenches, which block the minority carrier flow. A deep and
narrow trench is etched between all n-type and p-type wells, passivated and refilled with an
insulating layer.

1.2. Wave-Shaping Circuits:
Electronic circuits used to create or modify specified time-varying electrical voltage or

current waveforms using combinations of active electronic devices, such as transistors or
analog or digital integrated circuits, and resistors, capacitors, and inductors. Most wave-
shaping circuits are used to generate periodic waveforms. See Integrated circuits, Transistor
The common periodic waveforms include the square wave, the sine and rectified sine waves,
the sawtooth and triangular waves, and the periodic arbitrary wave. The arbitrary wave can be
made to conform to any shape during the duration of one period. This shape then is followed
for each successive cycle.
A number of traditional electronic and electromechanical circuits are used to generate these
waveforms. Sine-wave generators and LC, RC, and beat-frequency oscillators are used to
generate sine waves; rectifiers, consisting of diode combinations interposed between sine-
wave sources and resistive loads, produce rectified sine waves; multivibrators can generate
square waves; electronic integrating circuits operating on square waves create triangular
waves; and electronic relaxation oscillators can produce sawtooth waves. See Alternating
current, Diode, Multivibrator, Operational amplifier, Oscillator, Rectifier
In many applications, generation of these standard waveforms is now implemented using

digital circuits. Digital logic or microprocessors generate a sequence of numbers which
represent the desired waveform mathematically. These numerical values then are converted to
continuous-time waveforms by passing them through a digital-to-analog converter. Digital

waveform generation methods have the ability to generate waveforms of arbitrary shape, a
capability lacking in the traditional approaches. See Circuit (electronics), Logic circuits
1.2.1 Integrated Circuit(IC) Multivibrators.
A monostable multivibrator (MMV) often called a one-shot multivibrator, is a pulse

generator circuit in which the duration of the pulse is determined by the R-C
network,connected externally to the 555 timer. In such a vibrator, one state of output is stable
while the other is quasi-stable (unstable). For auto-triggering of output from quasi-stable state
to stable state energy is stored by an externally connected capacitor C to a reference level.
The time taken in storage determines the pulse width. The transition of output from stable
state to quasi-stable state is accomplished by external triggering. The schematic of a 555
timer in monostable mode of operation is shown in figure.
555-timer-monostable-multivibrator
Monostable Multivibrator Circuit details
Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of output this input
is kept at + VCC. To obtain transition of output from stable state to quasi-stable state, a
negative-going pulse of narrow width (a width smaller than expected pulse width of output
waveform) and amplitude of greater than + 2/3 VCC is applied to pin 2. Output is taken from
pin 3. Pin 4 is usually connected to + VCC to avoid accidental reset. Pin 5 is grounded through
a 0.01 u F capacitor to avoid noise problem. Pin 6 (threshold) is shorted to pin 7. A resistor

RA is connected between pins 6 and 8. At pins 7 a discharge capacitor is connected while pin
8 is connected to supply VCC.
555 IC Monostable Multivibrator Operation.
555 monostable-multivibrator-operation
For explaining the operation of timer 555 as a monostable multivibrator, necessary internal
circuitry with external connections are shown in figure.
The operation of the circuit is explained below:
Initially, when the output at pin 3 is low i.e. the circuit is in a stable state, the transistor is on
and capacitor- C is shorted to ground. When a negative pulse is applied to pin 2, the trigger
input falls below +1/3 VCC, the output of comparator goes high which resets the flip-flop and
consequently the transistor turns off and the output at pin 3 goes high. This is the transition of
the output from stable to quasi-stable state, as shown in figure. As the discharge transistor is
cutoff, the capacitor C begins charging toward +VCC through resistance RA with a time
constant equal to RAC. When the increasing capacitor voltage becomes slightly greater than
+2/3 VCC, the output of comparator 1 goes high, which sets the flip-flop. The transistor goes
to saturation, thereby discharging the capacitor C and the output of the timer goes low, as
illustrated in figure.
Thus the output returns back to stable state from quasi-stable state.

The output of the Monostable Multivibrator remains low until a trigger pulse is again applied.
Then the cycle repeats. Trigger input, output voltage and capacitor voltage waveforms are
shown in figure.
Monostable Multivibrator Design Using 555 timer IC
The capacitor C has to charge through resistance RA. The larger the time constant RAC, the
longer it takes for the capacitor voltage to reach +2/3VCC.
In other words, the RC time constant controls the width of the output pulse. The time during
which the timer output remains high is given as
tp=1.0986RAC
where RA is in ohms and C is in farads. The above relation is derived as below. Voltage
across the capacitor at any instant during charging period is given as
vc = VCC (1- e-t/RAC)
Substituting vc = 2/3 VCC in above equation we get the time taken by the capacitor to charge
from 0 to +2/3VCC.
So +2/3VCC. = VCC. (1 – e–t/RAC) or t – RAC loge 3 = 1.0986 RAC
So pulse width, tP = 1.0986 RAC s 1.1 RAC
The pulse width of the circuit may range from micro-seconds to many seconds. This circuit is
widely used in industry for many different timing applications.
1.3 Introduction to Operational Amplifier:
The operational amplifier is arguably the most useful single device in analog electronic
circuitry. With only a handful of external components, it can be made to perform a wide
variety of analog signal processing tasks. It is also quite affordable, most general-purpose
amplifiers selling for under a dollar apiece. Modern designs have been engineered with
durability in mind as well: several “op-amps” are manufactured that can sustain direct short-
circuits on their outputs without damage.

One key to the usefulness of these little circuits is in the engineering principle of feedback,
particularly negative feedback, which constitutes the foundation of almost all automatic
control processes.
1.3.1 Ideal v/s practical Opamp, Performance Parameters,
Ideal operational amplifier are characterized by
 Infinite gain
 Infinite input resistance
 Zero output resistance (order of 10‟s of ohms)
 Infinite bandwidth (practically restricted by slew rate)
 Linear irrespective of entire analog signal range No offsets
Practically it is of the order of 10^5 and is a function of frequency. Gain decreases linearly
with slope of 6db/octave, exhibits the characteristic of low pass filter with gain.
 Input resistance is of the of mega ohm Order due to differential stage at the front end
 Output resistance order of tens of ohms.
 Practically bandwidth of Opamp restricted by slew rate.
 Practical Opamp exhibits offsets and non linearity
1.4. Operational Amplifier Application Circuits:
1.4.1 Peak Detector Circuit

A conventional ac voltmeter cannot be used to measure the rms value of the pure sine wave.
One possible solution for this problem is to measure the peak values of the non-sinusoidal

wave forms.
1.4.2 Comparator
An operational amplifier (op-amp) has a well balanced difference input and a very high gain.
This parallels the characteristics of comparators and can be substituted in applications with
low-performance requirements
a standard op-amp operating in open-loop configuration (without negative feedback) may be

used as a low-performance comparator. When the non-inverting input (V+) is at a higher
voltage than the inverting input (V-), the high gain of the op-amp causes the output to
saturate at the highest positive voltage it can output. When the non-inverting input (V+) drops
below the inverting input (V-), the output saturates at the most negative voltage it can output.
The op-amp's output voltage is limited by the supply voltage. An op-amp operating in a linear
mode with negative feedback, using a balanced, split-voltage power supply, (powered by ±
VS) has its transfer function typically written as: . However, this equation may not be
applicable to a comparator circuit which is non-linear and operates open-loop (no negative
feedback)

1.4.3 Active Filters
The most common and easily understood active filter is the Active Low Pass Filter. Its
principle of operation and frequency response is exactly the same as those for the previously
seen passive filter, the only difference this time is that it uses an op-amp for amplification and
gain control. The simplest form of a low pass active filter is to connect an inverting or non-
inverting amplifier, the same as those discussed in the Op-amp tutorial, to the basic RC low
pass filter circuit as shown.
First Order Low Pass Filter
This first-order low pass active filter, consists simply of a passive RC filter stage providing a
low frequency path to the input of a non-inverting operational amplifier. The amplifier is
configured as a voltage-follower (Buffer) giving it a DC gain of one, Av = +1 or unity gain as
opposed to the previous passive RC filter which has a DC gain of less than unity.
The advantage of this configuration is that the op-amps high input impedance prevents
excessive loading on the filters output while its low output impedance prevents the filters cut-
off frequency point from being affected by changes in the impedance of the load.
While this configuration provides good stability to the filter, its main disadvantage is that it
has no voltage gain above one. However, although the voltage gain is unity the power gain is
very high as its output impedance is much lower than its input impedance. If a voltage gain
greater than one is required we can use the following filter circuit.

Active Low Pass Filter with Amplification
The frequency response of the circuit will be the same as that for the passive RC filter,
except that the amplitude of the output is increased by the pass band gain, AF of the amplifier.
For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given
as a function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 )
value and is given as:
Therefore, the gain of an active low pass filter as a function of frequency will be:
Gain of a first-order low pass filter
Where:
 AF = the pass band gain of the filter, (1 + R2/R1)

 ƒ = the frequency of the input signal in Hertz, (Hz)
 ƒc = the cut-off frequency in Hertz, (Hz)

Thus, the operation of a low pass active filter can be verified from the frequency gain
equation above as:
 At very low frequencies, ƒ < ƒc
 At the cut-off frequency, ƒ = ƒc
 At very high frequencies, ƒ > ƒc
Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high frequency cut-
off point, ƒC. At ƒC the gain is 0.707AF, and after ƒC it decreases at a constant rate as the
frequency increases. That is, when the frequency is increased tenfold (one decade), the
voltage gain is divided by 10.
1.4.4 Non-Linear Amplifier,
the voltage drop VF across the forward biased diode in the circuit of a passive rectifier is
undesired. In this active version, the problem is solved by connecting the diode in the
negative feedback loop. The op-amp compares the output voltage across the load with the
input voltage and increases its own output voltage with the value of VF. As a result, the
voltage drop VF is compensated and the circuit behaves very nearly as an ideal (super) diode
with VF = 0 V.
The circuit has speed limitations at high frequency because of the slow negative feedback and
due to the low slew rate of many non-ideal op-amps.

1.4.5 Relaxation Oscillator
Alternatively, when the capacitor reaches each threshold, the charging source can be switched
from the positive power supply to the negative power supply or vice versa. This case is
shown in the comparator-based implementation here.
This relaxation oscillator is a hysteretic oscillator, named this way because of the hysteresis
created by the positive feedback loop implemented with the comparator (similar to, but
different from, an op-amp). A circuit that implements this form of hysteretic switching is
known as a Schmitt trigger. Alone, the trigger is a bistable multivibrator. However, the slow
negative feedback added to the trigger by the RC circuit causes the circuit to oscillate
automatically. That is, the addition of the RC circuit turns the hysteretic bistable
multivibrator into an astable multivibrator.
1.4.6 Current-To-Voltage Converter
A current to voltage converter will produce a voltage proportional to the given current. This
circuit is required if your measuring instrument is capable only of measuring voltages and
you need to measure the current output.
If your instrument or data acquisition module (DAQ) has a input impedance that is several
orders larger than the converting resistor, a simple resistor circuit can be used to do the
conversion. However, if the input impedance of your instrument is low compared to the
converting resistor then the following opamp circuit should be used.

To analyse the current to voltage converter by inspection,
 if we apply KCL to the node at V- (the inverting input) and let the input current to the
inverting input be I-, then
Vout−V−Rf=Ip+I−(1) Vout=IpRf(3)
One example of such an application is using the photodiode sensor to measure light intensity.
The output of the photodiode sensor is a current which changes proportional to the light
intensity. Another advantage of the opamp circuit is that the voltage across the photodiode
(current source) is kept constant at 0V.
1.4.7 Voltages-To-Current Converter.
In this circuit the load is grounded and the current through the load can be calculated as
follows.


Module -2
2.1 The Basic Gates:

A digital circuit having one or more input signals but only one output signal is called a gate.
The most basic gates are – the AND gate, OR gate and the NOT gate (inverter). Connecting
the basic gates in different ways makes it possible to produce circuits that perform arithmetic
and other functions. Gates are often called logic circuits.
2.1.1 Review of Basic Logic gates
Basic Gates
These three logic circuits can be used to produce any digital system. The symbolic
representation of these basic gates and their truth table is given below.
2.1.2 Positive and Negative Logic
Positive and Negative Logic

The binary signals at the inputs or outputs of any gate may be one of two values, except
during transitions. One signal value represents logic 1, and the other is logic 0.
For a positive logic system, the most positive voltage level represents logic 1 state or HIGH
level (H) and the lowest voltage level represents logic 0 state or LOW level (L).
For a negative logic system, the most positive voltage level represents logic 0 state and the
lowest voltage level represents logic 1 state.

The effect of changing one logic system to another logic system is equivalent to
complementing the logic function.
2.1.3 Introduction to HDL.

HDL stands for Hardware description language. This is a textual description of a digital
circuit. The advantage of HDL, is to be able to
(i) describe a large complex design requiring hundreds of logic gates in a convenient
manner, in a smaller space
(ii) Use software test-bench to detect functional error, if any and correct it (called
simulation) and finally
(iii) Get hardware implementation details (called synthesis). Hardware Description
Language, more popular with its acronym HDL is an answer for that.
Currently, there are two widely used HDLs – Verilog and VHDL (Very High speed
integrated circuit Hardware Description Language). Verilog is considered simpler of the two
and is more popular. However, both share lot of common features and it is not too difficult to
switch from one to the other.
2.2 Combinational Logic Circuits:
Boolean Laws and Theorems

Binary logic deals with variables that have two discrete values: 1 for TRUE and 0 for
FALSE. A simple switching circuit containing active elements such as a diode and transistor
can demonstrate the binary logic, which can either be ON (switch closed) or OFF (switch
open).
The switching functions can be expressed with Boolean equations. Complex Boolean
equations can be simplified by a new kind of algebra, which is popularly called Switching
algebra or Boolean algebra, invented by the mathematician George Boole in 1854.
There are two fundamental approaches in logic design: the sum-of-products method and the
product of sums method. Either method produces a logic circuit corresponding to a given
truth table.
The Commutative Law
A+B=B+A
AB = BA

These two equations indicate that the order of a logical operation is unimportant because the
same answer is arrived at either way.
The Associative Law
A + (B + C) = (A + B) + C
A (BC) = (AB) C
These laws show that the order of combining variables has no effect on the final answer.
The Distributive Law
A (B + C) = AB + AC
The distributive law gives you a hint about the value of Boolean algebra. If you can rearrange
a Boolean expression, the corresponding logic circuit may be simpler.
We can use these laws to simplify complicated Boolean expressions and arrive at simpler
logic circuits. But before you begin, we have to learn other Boolean laws and theorems.
OR Operations
The next four Boolean relations are about OR operations. Here is the first:
A+0=A
This says that a variable ORed with 0 equals the variable. If you think about it, makes perfect
sense.
When A is 0,
0+0=0
And when A is 1,
1+0=1
In either case, the equation A + 0 = A is true.
Another Boolean relation is,
A+A=A
Again, you can see right through this by substituting the two possible values of A. First when
A = 0, the above equation gives
0+0=0
This is true. Next, A = 1 results in
1+1=1
This is also true because 1 ORed with 1 produces 1. Therefore, any variable ORed with itself
equals the variable.
Another Boolean rule worth knowing is
A+1=1
Why is this valid? When A = 0, the above equation gives
0+1=1
This is true. Also A = 1 gives
1+1=1
This is correct because the plus sign implies OR addition, not ordinary addition. In summary,
it says this, if one input to an OR gate is high, the output is high no matter what the other
input.
Finally, we have
A + A‟ = 1
You should see this in a flash. If A is 0, A‟ is 1 and the equation is true. Conversely, if A is 1,
A‟ is 0 and the equation still agrees. In short, a variable ORed with its complement always
equals 1.
2.2.1 Sum-of-Products Method

Canonical and Standard Forms
Logical functions are generally expressed in terms of different combinations of logical
variables with their true forms as well as the complement forms. Binary logic values obtained
by the logical functions and logic variables are in binary form. An arbitrary logic function can
be expressed in the following forms.
1. Sum of the Products (SOP)

2. Product of the Sums (POS)
Product Term: In Boolean algebra, the logical product of several variables on which a
function depends is considered to be a product term. In other words, the AND function is
referred to as a product term or standard product. The variables in a product term can be
either in true form or in complemented form. For example, ABC‟ is a product term.
Sum Term: An OR function is referred to as a sum term. The logical sum of several
variables on which a function depends is considered to be a sum term. Variables in a sum
term can also be either in true form or in complemented form. For example, A + B + C‟ is a
sum term.

Sum of Products (SOP): The logical sum of two or more logical product terms is referred to
as a sum of products expression. It is basically an OR operation on AND operated variables.
For example, Y = AB + BC + AC or Y = A‟B + BC + AC‟ are sum of products expressions.
Product of Sums (POS): Similarly, the logical product of two or more logical sum terms is
called a product of sums expression. It is an AND operation on OR operated variables. For
example, Y = (A + B + C)(A + B‟ + C)(A + B + C‟) or Y = (A + B + C)(A‟ + B‟ + C‟) are
product of sums expressions.
Standard form: The standard form of the Boolean function is when it is expressed in sum of
the products or product of the sums fashion. The examples stated above, like Y = AB + BC +
AC or Y = (A + B + C)(A + B‟ + C)(A + B + C‟) are the standard forms.
However, Boolean functions are also sometimes expressed in nonstandard forms like F = (AB
+ CD)(A‟B‟ + C‟D‟), which is neither a sum of products form nor a product of sums form.
However, the same expression can be converted to a standard form with help of various
Boolean properties, as
F = (AB + CD)(A‟B‟ + C‟D‟) = A‟B‟CD + ABC‟D‟
Minterm
A product term containing all n variables of the function in either true or complemented form
is called the minterm. Each minterm is obtained by an AND operation of the variables in their
true form or complemented form. For a two-variable function, four different combinations are
possible, such as, A‟B‟, A‟B, AB‟, and AB. These product terms are called the fundamental
products or standard products or minterms. In the minterm, a variable will possess the value 1
if it is in true or uncomplemented form, whereas, it contains the value 0 if it is in
complemented form. For three variables function, eight minterms are possible as listed in the
following table.

So, if the number of variables is n, then the possible number of minterms is 2n. The main
property of a minterm is that it possesses the value of 1 for only one combination of n input
variables and the rest of the 2n – 1 combination have the logic value of 0. This means, for the
above three variables example, if A = 0, B = 1, C = 1 i.e., for input combination of 011, there
is only one combination A‟BC that has the value 1, the rest of the seven combinations have
the value 0.
Canonical Sum of Product Expression: When a Boolean function is expressed as the

logical sum of all the minterms from the rows of a truth table, for which the value of the
function is 1, it is referred to as the canonical sum of product expression. The same can be
expressed in a compact form by listing the corresponding decimal-equivalent codes of the
minterms containing a function value of 1. For example, if the canonical sum of product form
of a three-variable logic function F has the minterms A‟BC, AB‟C, and ABC‟, this can be
expressed as the sum of the decimal codes corresponding to these minterms as below.
F (A, B, C) = (3,5,6)
= m3 + m5 + m6
= A‟BC + AB‟C + ABC‟
Where, Σ (3, 5, 6) represents the summation of minterms corresponding to decimal codes 3,
5, and 6.
The canonical sum of products form of a logic function can be obtained by using the
following procedure.
1. Check each term in the given logic functions. Retain if it is a minterm, continue to examine
the next term in the same manner.
2. Examine for the variables that are missing in each product which is not a minterm.
If the missing variable in the minterm is X, multiply that minterm with (X+X‟).
3. Multiply all the products and discard the redundant terms.

Here are some examples to explain the above procedure.

Example a) Obtain the canonical sum of product form of the following function.
F (A, B) = A + B
Solution: The given function contains two variables A and B. The variable B is missing from
the first term of the expression and the variable A is missing from the second term of the
expression. Therefore, the first term is to be multiplied by (B + B‟) and the second term is to
be multiplied by (A + A‟) as demonstrated below.
F (A, B) =A+B
= A.1 + B.1
= A (B + B‟) + B (A + A‟)
= AB + AB‟ + AB + A‟B
= AB + AB‟ + A‟B (as AB + AB = AB)
Hence the canonical sum of the product expression of the given function is
F (A, B) = AB + AB‟ + A‟B.
Example b) Obtain the canonical sum of product form of the following function.
F (A, B, C) = A + BC
Solution: Here neither the first term nor the second term is minterm. The given function
contains three variables A, B, and C. The variables B and C are missing from the first term of
the expression and the variable A is missing from the second term of the expression.
Therefore, the first term is to be multiplied by (B + B‟) and (C + C‟). The second term is tobe
multiplied by (A + A‟). This is demonstrated below.
F (A, B, C) = A + BC
= A (B + B‟) (C + C‟) + BC (A + A‟)
= (AB + AB‟) (C + C‟) + ABC + A‟BC
= ABC + AB‟C + ABC‟ + AB‟C‟ + ABC + A‟BC
= ABC + AB‟C + ABC‟ + AB‟C‟ + A‟BC (as ABC + ABC = ABC)
Hence the canonical sum of the product expression of the given function is
F (A, B) = ABC + AB‟C + ABC‟ + AB‟C‟ + A‟BC.
Example c) Obtain the canonical sum of product form of the following function.
F (A, B, C, D) = AB + ACD
Solution: F (A, B, C, D) = AB + ACD

= AB (C + C‟) (D + D‟) + ACD (B + B‟)
= (ABC + ABC‟) (D + D‟) + ABCD + AB‟CD
= ABCD + ABCD‟ + ABC‟D + ABC‟D‟ + ABCD + AB‟CD
= ABCD + ABCD‟ + ABC‟D + ABC‟D‟ + AB‟CD
Hence above is the canonical sum of the product expression of the given function.
2.2.2 Truth Table to Karnaugh Map
The Karnaugh map provides a systematic method for simplification and manipulation of a
Boolean expression. The map is a diagram consisting of squares. For n variables on a
Karnaugh map there are 2n numbers of squares. Each square or cell represents one of the
minterms. Since any Boolean function can be expressed as a sum of minterms, it is possible
to recognize a Boolean function graphically in the map from the area enclosed by those
squares whose minterms appear in the function. It is also possible to derive alternative
algebraic expressions or simplify the expression with a minimum number of variables or
literals and sum of products or product of sums terms, by analyzing various patterns. In fact,
the map represents a visual diagram of all possible ways a function can be expressed in a
standard form and the simplest algebraic expression consisting of a sum of products or
product of sums can be selected. Note that the expression is not necessarily unique.
2.2.3 Pairs Quads, and Octets, Karnaugh Simplifications
Pairs, Quads and Octets

Look at Fig (a) below. The map contains a pair of 1s that are horizontally adjacent (next to
each other). The first 1 represents the product ABCD; the second 1 stands for the product
ABCD‟. As we move from the first 1 to the second 1, only one variable goes from
uncomplemented to complemented form (D to D‟); the other variables don‟t change form (A,
B and C remain uncomplemented). Whenever this happens, you can eliminate the variable
that changes form.

Proof
The sum-of-products equation corresponding to Fig (a) is
Y = ABCD + ABCD‟
This factor into,
Y = ABCD (D + D‟)
Since D is ORed with its complement, the equation simplifies to
Y = ABC
In general, pair of horizontally adjacent 1s like those of Fig (a) means the sum-of-products
equation will have a variable and a complement that drop out as shown above.
For easy identification, we will encircle two adjacent 1s as shown in Fig (b). Two adjacent 1s
such as these are called a pair. In this way, we can tell at a glance that one variable and its
complement will drop out of the corresponding Boolean equation. In other words, an
encircled pair of 1s like those of Fig (b) no longer stands for the ORing of two separate
products, ABCD and ABCD‟. Rather, the encircled pair is visualized as representing a single
reduced product ABC.
Quad
A quad is a group of four 1s that are horizontally or vertically adjacent. The 1s may be end-
to-end, as shown in Fig (a), or in the form of a square, as in Fig (b). When you see a quad,
always encircle it because it leads to a simpler product. In fact, a quad eliminates two
variables and their complements.

Here is why a quad eliminates two variables and their complements. Visualize the four 1s of
Fig (a) as two pairs (see Fig (c)). The first pair represents ABC‟; the second pair stands for
ABC. The Boolean equation for these two pairs in
Y = ABC‟ + ABC
This factor into,
Y = AB (C‟ + C)
This reduces to,
Y = AB
So, the quad of Fig (a) represents a product whose two variables and their complements have
dropped out.
A similar proof applies to any quad. You can visualize it as two pairs whose Boolean
equation leads to a single product involving only two variables or their complements. There‟s
no need to go through the algebra each time. Merely step through the different 1s in the quad
and determine which two variables go from complemented to uncomplemented form (or vice
versa); these are the variables that drop out.
The Octet
Besides pairs and quads, there is one more group to adjacent 1s to look for: the octet. This is
a group of eight 1s like those of Fig (a) below. An octet like this eliminates three variables
and their complements. Here‟s why. Visualize the octet as two quads (see Fig (b)). The
equation for these two quads is,
Y = AC‟ + AC
After factoring,
Y = A (C‟ + C)
But this reduces to,
Y=A
So the octet of Fig (a) means three variables and their complements drop out of the
corresponding product.

A similar proof applies to any octet. From now on don‟t bother with the algebra. Merely step
through the 1s of the octet and determine which three variables change form. These are the
variables that drop out.
Karnaugh Simplification
As you know, a pair eliminates one variable and its complement, a quad eliminates two
variables and their complements, and an octet eliminates three variables and their
complements. Because of this, after you draw a Karnaugh map, encircle the octets first, the
quads second, and the pairs last. In this way, the greatest simplification will result.
An Example
Suppose you have translated a truth table into the Karnaugh map shown in Fig (a) below.
First, look for octets. There are none. Next, look for quads. When you find them, encircle
them, finally, look for and encircle pairs. If you do this correctly, you arrive at Fig (b).
The pair represents the simplified product A‟B‟D, the lower quad stands for AC‟, and the
quad on the right represents CD‟. By ORing these simplified products; we get the Boolean
equation corresponding to the entire Karnaugh Map:
Y = A‟B‟D + AC‟ + CD‟
Overlapping Groups
You are allowed to use the same 1 more than once. Fig (a) below illustrates this idea. The 1
representing the fundamental product ABC‟D is part of the pair and part of the octet. The
simplified equation for the overlapping groups is
Y = A + BC‟D
It is valid to encircle the 1s as shown in Fig. 3.17b, but then the isolated 1 result in a more
complicated equation:
Y = A + A‟BC‟D
So, always overlap groups if possible. That is, use the 1s more than once to get the largest
groups you can.

Rolling the Map

Another thing to know about is rolling. Look at Fig (a) below. The pairs result in this
equation:
Y = BC‟D‟ + BCD‟
Visualize picking up the Karnaugh map and rolling it so that the left side touches the right
side. If you are visualizing correctly, you will realize the two pairs actually form a quad. To
indicate this, draw half circles around each pair, as shown in Fig (b). From this viewpoint, the
quad of Fig (b) has the equation
Y = BD‟
Why is rolling valid? Because the Equation Y = BC‟D‟ + BCD‟can be algebraically

simplified to Y = BD‟. The proof starts with
Y = BC‟D‟ + BCD‟
This factor into,
Y = BD‟ (C‟ + C)
This result to,
Y = BD‟
But his final equation is the one that represents a rolled quad like Fig (b). Therefore, 1s on the
edges of a Karnaugh map can be grouped with 1s on opposite edges.
Eliminating Redundant Groups
After you have finished encircling groups, eliminate any redundant group. This is a group
whose 1s are already used by other groups. Here is an example. Given Fig (a), encircle the
quad to get Fig (b). Next, group the remaining 1s into pairs by overlapping (Fig (c)). In Fig

(c), all the 1s of the quad are used by the pairs. Because of this, the quad is redundant and can
be eliminated to get Fig (d). As you see, all the 1s are covered by the pairs. Fig (d) contains
one less product than Fig (c); therefore, Fig (d) is the most efficient way to group the 1s.
2.2.4 Don’t-care Conditions, Product-of-sums Method

In certain digital systems, some input combinations never occur during the process of a
normal operation because those input conditions are guaranteed never to occur. Such input
combinations are called Don‟t-Care Combinations. The function output may be either 1 or 0
and these functions are called incompletely specified functions. These input combinations can
be plotted on the Karnaugh map for further simplification of the function. The don‟t care
combinations are represented by d or x or Φ.
When an incompletely specified function, i.e., a function with don‟t-care combinations is
simplified to obtain minimal SOP expression, the value 1 can be assigned to the selected
don‟t care combinations. This is done to form groups like pairs, quad, octet, etc., for further
simplification. In each case, choice depends only on need to achieve simplification. Similarly,
selected don‟t care combinations may be assumed as 0s to form groups of 0s for obtaining
the POS expression.
Example a) Obtain the minimal sum of the products for the function
F (A, B, C, D) = Σ (1, 3, 7, 11, 15) + Φ(0, 2, 5).
The Karnaugh map for the above function is shown in figure below
In the Karnaugh map of above Figure, the minterm m0 and m2 i.e., A‟B‟C‟D‟ and A‟B‟CD‟, are the
don‟t care terms which have been assumed as 1s, while making a quad.
The simplified SOP expression of above function can be written as
F = A‟B‟ + CD

2.2.5 Product-of sums simplifications

Maxterm
A sum term containing all n variables of the function in either true or complemented form is
called the maxterm. Each maxterm is obtained by an OR operation of the variables in their
true form or complemented form. Four different combinations are possible for a two-variable
function. Such as, A‟ + B‟, A‟ + B, A + B‟, and A + B. These sum terms are called the
standard sums or maxterms. Note that in the maxterm, a variable will possess the value 0, if it
is in true or uncomplemented form, whereas, it contains the value 1, if it is in complemented
form. Like minterms, for a three-variable function, eight maxterms are also possible as listed
in the following table
So, if the number of variables is n, then the possible number of maxterms is 2n. The main
property of a maxterm is that it possesses the value of 0 for only one combination of n input
variables and the rest of the 2n –1 combinations have the logic value of 1. This means, for the
above three variables example, if A = 1, B = 1, C = 0 i.e., for input combination of 110, there
is only one combination A‟ + B‟ + C that has the value 0, the rest of the seven combinations
have the value 1.
Canonical Product of Sum Expression: When a Boolean function is expressed as the

logical product of all the maxterms from the rows of a truth table, for which the value of the
function is 0, it is referred to as the canonical product of sum expression. The same can be
expressed in a compact form by listing the corresponding decimal equivalent codes of the
maxterms containing a function value of 0. For example, if the canonical product of sums
form of a three-variable logic function F has the maxterms A + B + C, A + B‟ + C and A‟ + B

+ C‟, this can be expressed as the product of the decimal codes corresponding to these
maxterms as below,
F (A,B,C) = Π (0,2,5)
= M0 M2 M5
= (A + B + C) (A + B‟ + C) (A‟ + B + C‟)
Where Π (0,2,5) represents the product of maxterms corresponding to decimal codes 0, 2 and
5.
The canonical product of sums form of a logic function can be obtained by using the
following procedure.
1. Check each term in the given logic functions. Retain it if it is a maxterm, continue to
examine the next term in the same manner.
2. Examine for the variables that are missing in each sum term that is not a maxterm.
If the missing variable in the maxterm is X, multiply that maxterm with (X.X‟).
3. Expand the expression using the properties and postulates as described earlier and discard
the redundant terms.
Some examples are given here to explain the above procedure.

Example a) Obtain the canonical product of the sum form of the following function.
F (A, B, C) = (A + B‟) (B + C) (A + C‟)
Solution: In the above three-variable expression, C is missing from the first term, A is
missing from the second term, and B is missing from the third term. Therefore, CC‟ is to be
added with first term, AA‟ is to be added with the second and BB‟ is to be added with the
third term. This is shown below.
F (A, B, C) = (A + B‟) (B + C) (A + C‟)
= (A + B‟ + 0) (B + C + 0) (A + C‟ + 0)
= (A + B‟ + CC‟) (B + C + AA‟) (A + C‟ + BB‟)
= (A + B‟ + C) (A + B‟ + C‟) (A + B + C) (A‟ + B + C) (A + B + C‟)(A
+ B‟ + C‟)
[Using the distributive property, as X + YZ = (X + Y)(X + Z) ]
= (A + B‟ + C) (A + B‟ + C‟) (A + B + C) (A‟ + B + C) (A + B + C‟)
[As (A + B‟ + C‟) (A + B‟ + C‟) = A + B‟ + C‟]
Hence the canonical product of the sum expression for the given function is
F (A, B, C) = (A + B‟ + C) (A + B‟ + C‟) (A + B + C) (A‟ + B + C) (A + B + C‟)
Example b) Obtain the canonical product of the sum form of the following function.
F (A, B, C) = A + B‟C
Solution: In the above three-variable expression, the function is given at sum of the product
form. First, the function needs to be changed to product of the sum form by applying the
distributive law as shown below.
F (A, B, C) = A + B‟C
= (A + B‟) (A + C)
Now, in the above expression, C is missing from the fi rst term and B is missing from the
second term. Hence CC‟ is to be added with the first term and BB‟ is to be added with the
second term as shown below.
F (A, B, C) = (A + B‟) (A + C)
= (A + B‟ + CC‟) (A + C + BB‟)
= (A + B‟ + C) (A + B‟ + C‟) (A + B + C) (A + B‟ + C)
[Using the distributive property, as X + YZ = (X + Y) (X + Z)]
= (A + B‟ + C) (A + B‟ + C‟) (A + B + C)
[As (A + B‟ + C) (A + B‟ + C) = A + B‟ + C]
Hence the canonical product of the sum expression for the given function is
F (A, B, C) = (A + B‟ + C) (A + B‟ + C‟) (A + B + C).
Deriving a Sum of Products (SOP) Expression from a Truth Table

The sum of products (SOP) expression of a Boolean function can be obtained from its truth
table summing or performing OR operation of the product terms corresponding to the
combinations containing a function value of 1. In the product terms the input variables appear
either in true (uncomplemented) form if it contains the value 1, or in complemented form if it
possesses the value 0.
Now, consider the following truth table in figure below, for a three-input function Y. Here the
output Y value is 1 for the input conditions of 010, 100, 101, and 110, and their
corresponding product terms are A‟BC‟, AB‟C‟, AB‟C, and ABC‟ respectively.

The final sum of products expression (SOP) for the output Y is derived by summing or
performing an OR operation of the four product terms as shown below.
Y = A‟BC‟ + AB‟C‟ + AB‟C + ABC‟
In general, the procedure of deriving the output expression in SOP form from a truth table
can be summarized as below.
1. Form a product term for each input combination in the table, containing an output value of
1.
2. Each product term consists of its input variables in either true form or complemented form.
If the input variable is 0, it appears in complemented form and if the input variable is 1, it
appears in true form.
3. To obtain the final SOP expression of the output, all the product terms are OR operated.
Deriving a Product of Sums (POS) Expression from a Truth Table

As explained above, the product of sums (POS) expression of a Boolean function can also be
obtained from its truth table by a similar procedure. Here, an AND operation is performed on
the sum terms corresponding to the combinations containing a function value of 0. In the sum
terms the input variables appear either in true (uncomplemented) form if it contains the value
0, or in complemented form if it possesses the value 1.
Now, consider the same truth table as shown in figure above, for a three-input function Y.
Here the output Y value is 0 for the input conditions of 000, 001, 011, and 111, and their
corresponding product terms are A + B + C, A + B + C‟, A + B‟ + C‟, and A‟ + B‟ + C‟
respectively.

So now, the final product of sums expression (POS) for the output Y is derived by
performing an AND operation of the four sum terms as shown below.
Y = (A + B + C) (A + B + C‟) (A + B‟ + C‟) (A‟ + B‟ + C‟)
In general, the procedure of deriving the output expression in POS form from a truth table
can be summarized as below.
1. Form a sum term for each input combination in the table, containing an output value of 0.
2. Each product term consists of its input variables in either true form or complemented form.
If the input variable is 1, it appears in complemented form and if the input variable is 0, it
appears in true form.
3. To obtain the final POS expression of the output, all the sum terms are AND operated.
2.2.6 Simplification by Quine-McCluskyMethod,

The Karnaugh map method is a very useful and convenient tool for simplification of Boolean
functions as long as the number of variables does not exceed four (at the most six). But if the
number of variables increases, the visualization and selection of patterns of adjacent cells in
the Karnaugh map becomes complicated and difficult. The tabular method, also known as the
Quine-McCluskey method, overcomes this difficulty. It is a specific step-by-step procedure
to achieve guaranteed, simplified standard form of expression for a function.
The following steps are followed for simplification by the tabular or Quine-McCluskey
method.
1. An exhaustive search is done to find the terms that may be included in the simplified
functions. These terms are called prime implicants.
2. Form the set of prime implicants, essential prime implicants are determined by preparing a
prime implicants chart.
3. The minterms that are not covered by the essential prime implicants are taken into
consideration by selecting some more prime implications to obtain an optimized Boolean
expression.
Determination of Prime Implicants
The prime implicants are obtained by the following procedure:
1. Each minterm of the function is expressed by its binary representation.

2. The minterms are arranged according to increasing index (index is defined as the number
of 1s in a minterm). Each set of minterms possessing the same index are separated by lines.
3. Now each of the minterms is compared with the minterms of a higher index. For each pair
of terms that can combine, the new terms are formed. If two minterms are differed by only
one variable, that variable is replaced by a „-‟ (dash) to form the new term with one less
number of literals. A line is drawn in when all the minterms of one set is compared with all
the minterms of a higher index.
4. The same process is repeated for all the groups of minterms. A new list of terms is
obtained after the first stage of elimination is completed.
5. At the next stage of elimination two terms from the new list with the „-‟ of the same
position differing by only one variable are compared and again another new term is formed
with a less number of literals.
6. The process is to be continued until no new match is possible.
7. All the terms that remain unchecked i.e., where no match is found during the process, are
considered to be the prime implicants.
Prime Implicant Chart
1. After obtaining the prime implicants, a chart or table is prepared where rows are
represented by the prime implicants and the columns are represented by the minterms of the
function.
2. Crosses are placed in each row to show the composition of the minterms that makes the
prime implicants.
3. A completed prime implicants table is to be inspected for the columns containing only a
single cross. Prime implicants that cover the minterms with a single cross are called the
essential prime implicants.
The above process to find the prime implicants and preparation of the chart can be illustrated
by the following examples.
Example: Obtain the minimal sum of the products for the function
F (A, B, C, D) = Σ (1, 4, 6, 7, 8, 9, 10, 11, 15).
Solution: The table below shows the step-by-step procedure the Quine-McCluskey method
uses to obtain the simplified expression of the above function.
Column I consists of the decimal equivalent of the function or the minterms and column II is
the corresponding binary representation. They are grouped according to their index i.e.,
number of 1s in the binary equivalents. In column III, two minterms are grouped if they are
differed by only a single variable and equivalent terms are written with a „-‟ in the place
where the variable changes its logic value. As an example, minterms 1 (0001) and 9 (1001)
are grouped and written as 1, 9 (– 001) and so on for the others. Also, the terms of column II,
which are considered to form the group in column III, are marked with „√‟.
The terms which are not marked with „√‟ are the Prime implicants. To express the prime
implicants algebraically, variables are to be considered as true form in place of 1s, as
complemented form in place of 0s, and no variable if „-‟ appears. Here the prime implicants
are B‟C‟D, A‟BD‟, A‟BC, BCD, ACD (from column III), and AB‟ (from column IV). So the
Boolean expression of the given function can be written as
F = AB‟ + B‟C‟D + A‟BD‟ + A‟BC + BCD + ACD
But the above expression may not be of minimized form, as all the prime implicants may not
be necessary. To find out the essential prime implicants, the following steps are carried out. A
table or chart consisting of prime implicants and the decimal equivalent of minterms as given
in the expression, as in figure below is prepared.
In the table, the prime implicants are listed in the 1st column and Xs are placed against the
corresponding minterms. The completed prime implicants table is now inspected for the
columns containing only a single X. As in Figure above, the minterm 1 is represented by only

a single prime implicants B‟C‟D, and only a single X in that column, it should be marked as
well as the corresponding column should be marked. Similarly, the prime implicants AB‟ and
AB‟D‟ are marked. These are the essential prime implicants as they are absolutely necessary
to form the minimized Boolean expression. Now all the other minterms corresponding to
these prime implicants are marked at the end of the columns i.e., the minterms 1, 4, 6, 8, 9,
10, and 11 are marked. Note that the terms A‟BC, BCD, and ACD are not marked. So they
are not the essential prime implicants. However, the minterms 7 and 15 are still unmarked
and both of them are covered by the term BCD and are included in the Boolean expression.
Therefore, the simplified Boolean expression of the given function can be written as
F = AB‟ + B‟C‟D + A‟BD‟ + BCD.
The simplified expressions derived in the preceding example are in the sum of products form.
The Quine-McClusky method can also be adopted to derive the simplified expression in
product of sums form. In the Karnaugh map method the complement of the function was
considered by taking 0s from the initial list of the minterms. Similarly the tabulation method
or Quine-McClusky method may be carried out by considering the 0s of the function to
derive the sum of products form. Finally, by making the complement again, we obtain the
simplified expression in the form of product of sums.
A function with don‟t-care conditions can be simplified by the tabulation method with slight
modification. The don‟t-care conditions are to be included in the list of minterms while
determining the prime implicants. This allows the derivation of prime implicants with the
least number of literals. But the don‟t-care conditions are excluded in the list of minterms
when the prime implicants table is prepared, because these terms do not have to be covered
by the selected prime implicants.
2.2. 7 Hazards and Hazard covers
In digital logic, a hazard in a system is an undesirable effect caused by either a deficiency in

the system or external influences. Logic hazards are manifestations of a problem in which
changes in the input variables do not change the output correctly due to some form of delay
caused by logic elements (NOT, AND, OR gates, etc.) This results in the logic not
performing its function properly. The three different most common kinds of hazards are
usually referred to as static, dynamic and function hazards.

Hazards are a temporary problem, as the logic circuit will eventually settle to the desired
function. Therefore, in synchronous designs, it is standard practice to register the output of a
circuit before it is being used in a different clock domain or routed out of the system, so that
hazards do not cause any problems. If that is not the case, however, it is imperative that
hazards be eliminated as they can have an effect on other connected systems.
A static hazard is the situation where, when one input variable changes, the output changes
momentarily before stabilizing to the correct value. There are two types of static hazards:
 Static-1 Hazard: the output is currently 1 and after the inputs change, the output
momentarily changes to 0 before settling on 1
 Static-0 Hazard: the output is currently 0 and after the inputs change, the output
momentarily changes to 1 before settling on 0
In properly formed two-level AND-OR logic based on a Sum Of Products expression, there
will be no static-0 hazards. Conversely, there will be no static-1 hazards in an OR-AND
implementation of a Product Of Sums expression.
2.2.8 HDL Implementation Models.

Verilog HDL
Writing Module Body: There are three different models of writing module body in Verilog
HDL. Each one has its own advantage and suited for certain kind of design. We start with
structural model by example of two-input OR gate.
module or_gate (A,B,Y);
input A, B; // defines two input port
output Y; // defines one output port
or g1(Y, A, B); /* Gate declaration with predefined keyword or representing logic
OR, g1 is optional user defined gate identifier */
endmodule
Verilog supports predefined gate level primitives such as and, or, not, nand, nor, xor, xnor
etc. The syntax followed above can be extended to other gates and for 4 input OR gate it is as
given next,
or (output, input 1, input 2, input 3, input 4)
For NOT gate, not (Output, input)

Note that, Verilog can take up to 12 inputs for logic gates. Comments when extends to next
line is written within /*… */. Identifiers in Verilog are case sensitive, begin with a letter or
underscore and can be of any length.

Module – 3
3.2Data-Processing Circuits:
3.1.1 Multiplexers, Demultiplexers

The term multiplex means “many into one”. A digital multiplexer is a combinational circuit
that selects binary information from one of the many input channels and transmits to a single
output line. That is why the multiplxers are also called data selectors. The selection of the
particular input channel is controlled by a set of select inputs. A digital multiplexer of 2n
input channels can be controlled by n numbers of select lines and an input line is selected
according to the bit combinations of select lines.
A 4-to-1 line multiplexer is defined as the multiplexer consisting of four input channels and
information of one of the channels can be selected and transmitted to an output line according
to the select inputs combinations. Selection of one of the four input channels is possible by
two selection inputs. The above figure illustrates the truth table. Input channels I0, I1, I2, and
I3 are selected by the combinations of select inputs S1 and S0. The circuit diagram is shown in
below. To demonstrate the operation, let us consider that select input combination S1S0 is 01.
The AND gate associated with I1 will have two of inputs equal to logic 1 and a third input is
connected to I1. Therefore, output of this AND gate is according to the information provided
by channel I1. The other three AND gates have logic 0 to at least one of their inputs which
makes their outputs to logic 0. Hence, OR output (Y) is equal to the data provided by the
channel I1. Thus, information from I1 is available at Y. Normally a multiplexer has an
ENABLE input to also control its operation. The ENABLE input (also called STROBE) is

useful to expand two or more multiplexer ICs to a digital multiplexer with a larger number of
inputs.
A multiplexer is often abbreviated as MUX. Its block diagram is shown below.
Demultiplexers (Data Distributors)

The term “Demultiplexer” means one into many. Demultiplexing is the process that receives
information from one channel and distributes the data over several channels. It is the reverse
operation of the multiplexer. A Demultiplexer is the logic circuit that receives information
through a single input line and transmits the same information over one of the possible 2n
output lines. The selection of a specific output line is controlled by the bit combinations of
the selection lines.
A 1-to-8 Demultiplexer circuit is demonstrated in figure below. The selection input lines A,
B, and C activate an AND gate according to its bit combination. The input line I is common

to one of the inputs of all the AND gates. So information of I passed to the output line is
activated by the particular AND gate. As an example, for the selection input combination
000, input I is transmitted to Y0. A truth table is prepared in figure above to illustrate the
relation of selection inputs and output lines.
The Demultiplexer is symbolized as shown below where S2, S1, and S0 are the selection
inputs.

3.1.2 1-of-16 Decoder
Decoders
In a digital system, discrete quantities of information are represented with binary codes. A
binary code of n bits can represent up to 2n distinct elements of the coded information. A
decoder is a combinational circuit that converts n bits of binary information of input lines to a
maximum of 2n unique output lines. Usually decoders are designated as an n to m lines
decoder, where n is the number of input lines and m (=2n) is the number of output lines.
Decoders have a wide variety of applications in digital systems such as data demultiplexing,
digital display, digital to analog converting, memory addressing, etc. A 3-to-8 line decoder is
illustrated in Figure below.
The 3-to-8 line decoder consists of three input variables and eight output lines. Note that each
of the output lines represents one of the minterms generated from three variables. The
internal combinational circuit is realized with the help of INVERTER gates and AND gates.
The operation of the decoder circuit may be further illustrated from the input output
relationship as given in the table below. Note that the output variables are mutually exclusive
to each other, as only one output is possible to be logic 1 at any one time.
In this section, the 3-to-8 line decoder is illustrated elaborately. However, higher order
decoders like 4 to 16 lines, 5 to 32 lines, etc., are also available in MSI packages, where the
internal circuits are similar to the 3-to-8 line decoder.

1-Of-16 Decoder

3.1.3 BCD to Decimal Decoders

BCD code uses four bits to represent its different numbers from 0 to 9. So the decoder should
have four input lines and ten output lines. By simple method a BCD-to-decimal coder may
use a 4-to-16 line decoder. But at output, six lines are illegal and they are deactivated with the
use of AND gates or any other means. However, a 3-to-8 line decoder may be employed for
this purpose with its intelligent utilization. A partial truth table of a BCD-to-decimal decoder
is shown below.

Since the circuit has ten outputs, ten Karnaugh maps are drawn to simplify each one of the
outputs. However, it would be useful to construct a single map similar to a Karnaugh map
indicating the outputs and don‟t-care conditions as in figure below. It can be seen that pairs
and groups may be formed considering the don‟t-care conditions.
The Boolean expressions of the different outputs may be written as
D0 = A‟B‟C‟D‟
D1 = A‟B‟C‟D D2
= B‟CD‟ D3 =
B‟CD
D4 = BC‟D‟
D5 = BC‟D
D6 = BCD‟
D7 = BCD
D8 = AD‟ D9
= AD
3.1.4 Seven Segment Decoders

A seven-segment decoder-driver is an IC decoder that can be used to drive a seven-segment
indicator. Each decoder has 4 input pin (BCD input) and 7 output pins which will connected
to the seven-segment indicator.
The circuit diagram of the Seven Segment Decoder with display indicator are shown below.

3.1.5 Encoders
An encoder is a combinational network that performs the reverse operation of the decoder.
An encoder has 2n or less numbers of inputs and n output lines. The output lines of an
encoder generate the binary code for the 2n input variables. Figure below illustrates an octal-
to-binary encoder where binary codes are generated at outputs according to the input
conditions.

3.1.6 Exclusive-OR Gates

The exclusive-OR gate has a high output only when an odd number of inputs is high. The
symbol, algebraic function and the truth table of Ex-OR gate is given below.
3.1.7 Parity Generators and Checkers
Even parity means an n-bit input has an even number of 1s.

Odd parity means an n-bit input has an odd number of 1s.
Parity Checker
Ex-OR gates are ideal for checking the parity because they produce an output 1 when the
input has an odd number of 1s. Therefore, an even parity input to an Ex-OR gate produces a
low output, while an odd parity input produces a high output.
The message bits with the parity bit are transmitted to their destination, where they are
applied to a parity checker circuit. The circuit that checks the parity at the receiver side is
called the parity checker. The parity checker circuit produces a check bit and is very similar
to the parity generator circuit. If the check bit is 1, then it is assumed that the received data is
incorrect. The check bit will be 0 if the received data is correct. This is demonstrated by the
table shown below.

Note that the check bit is 0 for all the bit combinations of correct data. For incorrect data the
parity check bit will be another logic value. Parity checker circuits are the same as parity
generator circuits as shown below.
Parity Generator
A parity generator is a combination logic system to generate the parity bit at the transmitting
side.
If the message bit combination is designated as D3D2D1D0, and Pe, Po are the even and odd
parity respectively, then it is obvious from the table below that the Boolean expressions of
even parity and odd parity are

Pe = D3 D2 D1 D0 and
Po = (D3 D2 D1 D0)‟
The logic diagrams of parity generate for the above mentioned case is shown below
3.1.8 Magnitude Comparator

A magnitude comparator is one of the useful combinational logic networks and has wide
applications. It compares two binary numbers and determines if one number is greater than,
less than, or equal to the other number. It is a multiple output combinational logic circuit. If
two binary numbers are considered as X and Y, the magnitude comparator gives three outputs
for X > Y, X < Y and X = Y.
The logical equations for the outputs can be written as follows, where G, L and E stands for
Greater than, Less than and Equal to respectively.

(X > Y): G = XY‟

(X < Y): L = X‟Y
(X = Y): E = X‟Y‟ + XY = (XY‟ + X‟Y)‟ = (G + L)‟
Let‟s first define bit-wise greater than terms (G) : G1 = X1Y1‟ G0 = X0Y0‟
Then, bit-wise less than term (L) : L1 = X1‟Y1 L0 = X0‟Y0
Therefore, bit-wise equality term (E) : E1 = (G1 + L1)‟ E0 = (G0 + L0)‟
From above definitions we can easily write 2-bit comparator outputs as follows.
(X = Y) = E1.E0
(X > Y) = G1 + E1.G0
(X < Y) = L1 + E1.L0
Thus for any two n-bit numbers X: Xn-1 Xn-2 … X0 and Y: Yn-1 Yn-2 … Y0
We can write, (X = Y) = En-1 En-2 … E0
(X > Y) = Gn-1 + En-1Gn-2 + … + En-1En-2 … E1G0
(X < Y) = Ln-1 + En-1Ln-2 + … + En-1En-2 … E1L0
3.1.9 Programmable Array Logic

Programmable Array Logic (PAL) is a programmable array of logic gates on a single chip.
Programming a PAL: A PAL is different from a PROM because it has programmable AND
array and a fixed OR array. With a PROM programmer, we can burn in the desired
fundamental products, which are the ORed by the fixed output connections.

Unlike PROMs, PALs are not a universal logic solution because only some of the
fundamental products can be generated and ORed at the final outputs. Nevertheless, PALs
have enough flexibility to produce all kinds of complicated logic functions.
3.1.10 Programmable Logic Arrays

Programmable Logic Arrays (PLAs), along with ROMs and PALs, are included in the more
general classification of ICs called Programmable Logic Devices (PLDs).
The input AND-gate array used in a PROM is fixed and cannot be altered, while the output
OR gate array is fusible-linked, and can thus be programmed. The PLA is more versatile than
the PROM or the PAL, since both its AND gate array and its OR gate array are fusible-linked
and programmable.
A PLA having 3 input variables (ABC) and 3 output variables (XYZ) is illustrated below.

3.1.11 HDL Implementation of Data Processing Circuits
Realization of 2-to-1 multiplexer by using conditional assignment operator:

module mux2to1(A, D0, D1, Y); module mux2to1(A, D0, D1, Y);
input A, D0, D1; input A, D0, D1;
output Y; output Y;
assign Y = (~A&D0)| assign Y = A ? D1 : D0; /* Conditional
(A&D1); Assignment */
endmodule endmodule
3.1.12 Arithmetic Building Blocks
Half Adder
With the help of half adder, we can design circuits that are capable of performing simple
addition with the help of logic gates.
Let us first take a look at the addition of single bits.
0+0 = 0
0+1 = 1
1+0 = 1

1+1 = 10
These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this
problem can be solved with the help of an EXOR Gate, if you do care about the output, the
sum result must be re-written as a 2-bit output.
Thus the above equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10
Here the output „1‟of „10‟ becomes the carry-out. The result is shown in a truth-table below.
„SUM‟ is the normal output and „CARRY‟ is the carry-out.
INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the equation it is clear that this 1-bit adder can be easily implemented with the help of
EXOR Gate for the output „SUM‟ and an AND Gate for the carry. Take a look at the
implementation below.

Half Adder Circuit
For complex addition, there may be cases when you have to add two 8-bit bytes together.
This can be done only with the help of full-adder logic.
Full Adder
This type of adder is a little more difficult to implement than a half-adder. The main
difference between a half-adder and a full-adder is that the full-adder has three inputs and two
outputs. The first two inputs are A and B and the third input is an input carry designated as
CIN. When a full adder logic is designed we will be able to string eight of them together to
create a byte-wide adder and cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the normal output is designated as S. Take a
look at the truth-table.
INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1

1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the above truth-table, the full adder logic can be implemented. We can see that the
output S is an EXOR between the input A and the half-adder SUM output with B and CIN
inputs. We must also note that the COUT will only be true if any of the two inputs out of the
three are HIGH.
Thus, we can implement a full adder circuit with the help of two half adder circuits. The first
will half adder will be used to add A and B to produce a partial Sum. The second half adder
logic can be used to add CIN to the Sum produced by the first half adder to get the final S
output. If any of the half adder logic produces a carry, there will be an output carry. Thus,
COUT will be an OR function of the half-adder Carry outputs. Take a look at the
implementation of the full adder circuit shown below.
Full Adder Circuit
Though the implementation of larger logic diagrams is possible with the above full adder
logic a simpler symbol is mostly used to represent the operation. Given below is a simpler
schematic representation of a one-bit full adder.

Single-bit Full Adder
With this type of symbol, we can add two bits together taking a carry from the next lower
order of magnitude, and sending a carry to the next higher order of magnitude. In a computer,
for a multi-bit operation, each bit must be represented by a full adder and must be added
simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be
formed by cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown
below.
3.1.13 Arithmetic Logic Unit
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit
(CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In addition
to ALUs, modern CPUs contain a control unit (CU).
Most of the operations of a CPU are performed by one or more ALUs, which load data from
input registers. A register is a small amount of storage available as part of a CPU. The
control unit tells the ALU what operation to perform on that data and the ALU stores the

result in an output register. The control unit moves the data between these registers, the ALU,
and memory.
3.3Flip-Flops:
There are requirements for a digital device or circuit whose output will remain
unchanged, once set, even if there is a change in input level(s). Such a device could be
used to store a binary number. A flip-flop is one such circuit. Flip-flops are used in the
construction of registers and counter, and in numerous other applications.
3.2.1 RS Flip-Flops
RS Flip-Flops
Any device or circuit that has two stable states is said to be bistable. A flip-flop is a bistable
electronic circuit that has two stable states i.e. its output is either 0 or 1. The flip-flop also has
memory since its output will remain as set until something is done to change it. Flip-flop can
be regarded as a memory device. The flip-flop is often called a latch, since it will hold or
latch, in either stable state.
NOR Gate Latch
The logical circuit of RS Flip-Flop using NOR gate is given below.
There are two inputs to the flip-flop defined as R and S, and two outputs defined as Q and Q‟.
It should be clear that regardless of the value of Q, its complement is Q‟. The input/output
possibilities for this RS flip-flop are summarized in the truth table shown below.

1. When R = 0 and S = 0: Since a 0 at the input of a NOR gate has no effect on its
output, the flip-flop simple remains in its present state i.e. Q remains unchanged.
2. When R = 0 and S = 1: The flip-flop is SET and it switches to the stable state where Q
= 1.
3. When R = 1 and S = 0: The flip-flop is RESET and it switches to the stable state
where Q = 0.
4. When R = 1 and S = 1: This input condition is forbidden, as it forces the outputs of
both NOR gates to the low state. In other words, both Q = 0 and Q‟ = 0 at the same
time. But this violates the basic definition of a flip-flop that requires Q to be the
complement of Q‟.
NAND Gate Latch

The logical diagram and truth table of RS Flip-Flop using NAND gate is given below.
Notice that NAND Gate realization of RS Flip-flop is exact equivalent of NOR Gate
realization and both have the exact same truth table.
3.2.2 Gated Flip-Flops
Gated Flip-Flop
The RS Flip-flops discussed previously are said to be transparent; that is, any change in input
information at R or S is transmitted immediately to the output at Q and Q‟ according to the
truth table.
Clocked RS Flip-Flops
When two AND gates are added at the R and S inputs as shown in the figure below, the flip-
flop can be enabled or disable. When the ENABLE input is low, the AND gate outputs must

both be low and changes in neither R nor S will have any effect on the flip-flop output Q. The
latch is said to be disabled.
When the ENABLE input is high, information at the R and S inputs will be transmitted
directly to the outputs. The latch is said to be enabled. The output will change in response to
input changes as long as the ENABLE is high. When the ENABLE input goes low, the output
will retain the information that was present on the input.
Clocked D Flip-Flops
In the RS Flip-Flop, the forbidden condition of both R and S high may occur inadvertently.
This has led to the D Flip-Flop, a circuit that needs only a single data input.
Figure below shows a simple way to build a D (Data) Flip-Flop.
The behavior of the D Flip-Flop is straight forward (compare to RS Flip Flop).

The standard representation of D latch and truth table is given below.
The idea of data storage using D latches is shown below. Four D latches are driven by the
same clock signal. When the clock goes high, input data is loaded into the flip-flops and
appears at the output. Then when the clock goes low, the output retains the data.

3.2.3 Edge-triggered RS FLIP-FLOP
Edge Triggered RS Flip-Flops

The simple latch-type flip-flops are completely transparent. The gated or clocked RS and D
flip-flops might be considered semitransparent. If any of these flip-flops are used in a
synchronous system, care must be taken to ensure that all flip-flop inputs change state in
synchronism with the clock. Thus the edge-triggered flip-flop was developed to overcome
these rather severe restrictions.
Positive Edge Triggered RS Flip-Flops
The logical diagram and IEEE symbol of positive edge triggered RS Flip-Flop is shown
below.
The Clock (C) is applied to a positive pulse forming circuit. The positive transition developed
is then applied to a gated RS Flip-Flop. The result is a positive edge triggered RS flip-flop.
The small triangle inside the symbol (dynamic input indicator) indicates that Q can change
state only with positive transition of the clock (C). This flip-flop is easy to use in any
synchronous system. The S and R inputs affect Q only while the positive pulse is high, and
they need to be static only during this very short time.
The truth table and the waveforms for the edge triggered RS flip-flop is given below.

Negative Edge Triggered RS Flip-Flops

The behavior of Negative Edge Triggered RS Flip-Flop is similar to the positive edge
triggered RS flip-flop except that Q changes state according to the R and S inputs only during
negative edge of the clock instead of positive edge.
The IEEE symbol and the truth table of negative edge triggered RS flip-flop are given below.
Edge Triggered D Flip-Flops
3.2.4 Edge triggered D FLIP-FLOPs

D latch is used for temporary storage in electronic instruments, even more popular kind of D
flip-flop is used in digital computers and systems. This kind of flip-flop samples the data bit
at a unique point in time.
The above figure shows a positive pulse-forming circuit at the input of a D latch. The narrow
positive pulse enables the AND gates for an instant. The effect is to activate the AND gates
during the positive pulse of C, which is equivalent to sampling the value of D for an instant.
At this unique point in time, D and its complement hit the flip flop inputs, forcing Q to set or

reset. This operation is called edge triggering because the flip-flop responds only when the
clock going edge of the clock; this is referred to as positive edge triggering.
3.2.5 Edge-triggered JK FLIP-FLOPs
Setting R = S = 1 input to an RS flip-flop forces both Q and Q‟ to the same logic level. This
is an illegal condition, and it is not possible to predict the final state of Q. The JK flip flop
accounts for this illegal input, and is therefore a more versatile circuit.
Positive Edge Triggered JK Flip Flop
In the figure shown below, the pulse forming box changes the clock into a series of positive
pulses, and thus this circuit will be sensitive to positive transition of the clock. The basic
circuit is identical to the previous positive edge triggered RS flip flop, with two important
addition:
1. The Q output is connected back to the input of the lower AND gate.
2. The Q‟ output is connected back to the input of the upper AND gate.
The cross coupling from outputs to inputs changes the RS flip flop into a JK flip flop. The
previous S input is labeled J, and the R input is labeled K.

Module-4
4.1 Flip- Flops:
4.1.1. FLIP-FLOP Timing

Switching time is the main cause of propagation delay, designated tP. This represents the
amount of time it takes for the output of a gate or flip flop to change state after the input
changes.
Stray capacitance at the D input makes it necessary for data bit D to be at the input before the
clock edge arrives. The setup time tsetup is the minimum amount of time that the data bit must
be present before the clock edge hits.
Furthermore, data bit D has to be held long enough for the internal transistors to switch states.
Only after the transition is assured can we allow data bit D to change. Hold time thold is the
minimum amount of time that data bit D must be present after the positive transition of the
clock.
4.1.2 JK Master-slave FLIP-FLOP

The figure below shows the JK Master Slave flip flop.

The clock is not edge triggered. The master does in fact change state when C goes high.
However, while the clock is high, any change in J or K will immediately affect the master flip
flop. During this time J and K must be static.
In summary, the master is set according to J and K while the clock is high; the contents of the
master are then shifted into the slave (Q changes state) when the clock goes low.
4.1.3 Switch Contact Bounce Circuits

In most of the digital system there will be occasion to use mechanical contacts for the
purpose of conveying an electrical signal. The single-pole-single-throw (SPST) switch shown
below is one such example. When the switch is open, the voltage at point A is +5 Vdc; when
the switch is closed, the voltage at point A is 0 Vdc. The ideal voltage waveform at A should
appear as shown below.
In actuality, the waveform at point A will appear more or less as shown below, as the result
of a phenomenon known as contact bounce. Any mechanical switching device consists of a
moving contact arm restrained by some sort of a spring system. As a result, when the arm is
moved from one stable position to the other, the arm bounces. The number of bounces that
occur and the period of the bounce differ for each switching device.

A simple RS latch debounce circuit

The RS latch is figure below will remove any contact bounce due to the switch. The output
(Q) is used to generate the desired switch signal.
When the switch is moved to position H, R =0 and S =1. Bouncing occurs at the S input due
to the switch. The flip flop sees this as a series of high and low inputs, settling with a high
level. The flip flop will immediately be set with Q = 1 at the first high level on S. When the
switch bounces, losing contact, the input signals are R = S = 0, therefore the flip flop remains
set (Q = 1). When the switch regains contact, R = 0 and S = 1; this causes an attempt to again
set the flip flop. But since the flip flop is already set, no changes occur at Q. The result is that
the flip flop responds to the first, and only to the first high level at its S input, resulting in a
clean low-to-high signal at its output (Q).
When the switch is moved to position L, S = 0 and R =1 and the bouncing occurs at R input.
The behavior now is similar as described above.
4.1.4 Various Representations of FLIP-FLOPs

Characteristic Equations of flip flops
The characteristic equation of flip flops can be derived using truth tables of flip flops and
optimizing the expression by using K-Map as shown below.

The equation of SR flip-flop and all others can be represented as

SR Flip flop: Qn+1 = S + R‟Qn
JK Flip flop: Qn+1 = JQn‟ + K‟Qn
D Flip flop: Qn+1 = D
Flip Flops as Finite State Machine

In a sequential logic circuit the value of all the memory elements at a given time define the
state of the circuit at that time. Finite state machine (FSM) concept offers a better alternative
to truth table in understanding progress of the sequential logic with time. In FSM, functional
behavior of the circuit is explained using finite number of states as shown below

4.1.5 HDL Implementation of FLIP-FLOP

module DLatch(D, EN,Q); module SRLatch(S, R, EN,Q);
input D, EN; input S, R, EN;
output Q; output Q;
reg Q; reg Q;
always @ (EN or D) always @ (EN or S or R)
if (EN) Q = D; if (EN) Q = S | (~R&Q);
// from characteristic equation // from characteristic equation
endmodule endmodule
4.2 Registers:
A register is a group of binary storage cells capable of holding binary information. A group
of flip-fl ops constitutes a register, since each flip-fl op can work as a binary cell. Registers
can be designed using discrete flip-fl ops (S-R, J-K, and D-type).
4.2.1 Types of Registers

A register capable of shifting its binary contents either to the left or to the right is called a
shift register. The data in a shift register can be shifted in two possible ways: (a) serial
shifting and (b) parallel shifting. The serial shifting method shifts one bit at a time for each
clock pulse in a serial manner, beginning with either LSB or MSB. On the other hand, in
parallel shifting operation, all the data (input or output) gets shifted simultaneously during a
single clock pulse. Hence, we may say that parallel shifting operation is much faster than
serial shifting operation.
There are two ways to shift data into a register (serial or parallel) and similarly two ways to
shift the data out of the register. This leads to the construction of four basic types of registers
which are listed below.
1. Serial in – Serial Out
2. Serial in – Parallel Out
3. Parallel in – Serial Out
4. Parallel in – Parallel Out

4.2.2 Serial In - Serial Out

From the name itself it is obvious that this type of register accepts data serially, i.e., one bit at
a time at the single input line. The output is also obtained on a single output line in a serial
fashion. The data within the register may be shifted from left to right using shift-left register,
or may be shifted from right to left using shift-right register.
Shift-right Register
A shift-right register can be constructed with either J-K or D flip-fl ops as shown in figure
below. A J-K flip-fl op–based shift register requires connection of both J and K inputs. Input
data are connected to the J and K inputs of the left most (lowest order) flip-fl op. To input a 0,
one should apply a 0 at the J input, i.e., J = 0 and K = 1 and vice versa. With the application
of a clock pulse the data will be shifted by one bit to the right.
In the shift register using D flip-fl op, D input of the left most flip-fl op is used as a serial
input line. To input 0, one should apply 0 at the D input and vice versa.

The clock pulse is applied to all the flip-fl ops simultaneously. When the clock pulse is
applied, each flip-fl op is either set or reset according to the data available at that point of
time at the respective inputs of the individual flip-fl ops. Hence the input data bit at the serial
input line is entered into flip-fl op A by the first clock pulse. At the same time, the data of
stage A is shifted into stage B and so on to the following stages. For each clock pulse, data
stored in the register is shifted to the right by one stage. New data is entered into stage A,
whereas the data present in stage D are shifted out (to the right).
4.2.3 Serial In - Parallel out

In this type of register, the data is shifted in serially, but shifted out in parallel. To obtain the
output data in parallel, it is required that all the output bits are available at the same time.
This can be accomplished by connecting the output of each flip-fl op to an output pin. Once
the data is stored in the flip-fl op the bits are available simultaneously. The basic
configuration of a serial-in–parallel-out shift register is shown in figure below.

4.2.4 Parallel In - Serial Out

In the preceding two cases the data was shifted into the registers in a serial manner. We now
can develop an idea for the parallel entry of data into the register. Here the data bits are
entered into the flip-fl ops simultaneously, rather than a bit-by-bit basis.
Consider an 8-bit serial/parallel-in and serial-out shift register. The circuit diagram is given
below.
The data can be loaded into the register in parallel and shifted out serially at QH using either
of two clocks (CLK or CLK inhibit). It also contains a serial input, DS through which the
data can be serially shifted in.
When the input SHIFT / LOAD (SH / LD) is LOW, it enables all the NAND gates for
parallel loading. When an input data bit is a 0, the flip-fl op is asynchronously RESET by a
LOW output of the lower NAND gate. Similarly, when the input data bit is a 1, the flip-fl op
is asynchronously SET by a LOW output of the upper NAND gate. The clock is inhibited
during parallel loading operation. A HIGH on the SHIFT / LOAD input enables the clock
causing the data in the register to shift right. With the low to high transitions of either clock,
the serial input data (DS) are shifted into the 8-bit register.

4.2.5 Parallel In - Parallel Out

There is a fourth type of register which is designed such that data can be shifted into or out of
the register in parallel. In this type of register there is no interconnection between the flip-fl
ops since no serial shifting is required. Hence, the moment the parallel entry of the data is
accomplished the data will be available at the parallel outputs of the register. A simple
parallel-in–parallel out shift register is shown in figure below.
Here the parallel inputs to be applied at A, B, C, and D inputs are directly connected to the D
inputs of the respective flip-fl ops. On applying the clock transitions, these inputs are entered
into the register and are immediately available at the outputs Q1, Q2, Q3, and Q4.
4.2.6 Universal Shift Register
A universal shift register is an integrated logic circuit that can transfer data in three different
modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it
can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the
universal shift register can combine the capabilities of both parallel and shift registers to
accomplish tasks that neither basic type of register can perform on its own. For instance, on a
particular job a universal register can load data in series (e.g. through a sequence of left
shifts) and then transmit/output data in parallel.
Universal shift registers, as all other types of registers, are used in computers as memory
elements. Although other types of memory devices are used for the efficient storage of very
large volume of data, from a digital system perspective when we say computer memory we
mean registers. In fact, all the operations in a digital system are performed on registers.
Examples of such operations include multiplication, division, and data transfer. In order for
the universal shift register to operate in a specific mode, it must first select the mode. To
accomplish mode selection the universal register uses a set of two selector switches, S1 and

S0. As shown in Table 1, each permutation of the switches corresponds to a loading/input

mode.
Operating Mode S1 S0
Locked 0 0
Shift-Right 0 1
Shift-Left 1 0
Parallel Loading 1 1
Table 1
In the locked mode (S1S0 = 00) the register is not admitting any data; so that the content of
the register is not affected by whatever is happening at the inputs. You may verify this detail
by playing around with the main interactive circuit. For example, set L3L2L1L0 = 1010 and
then cycle the clock to see that nothing changes at the outputs as long as S1S0 = 00. See
Table 2.
Clock Cycle L3 L2 L1 L0 Q3 Q2 Q1 Q0
Initial Value 1 0 1 0 0 0 0 0
Cycle 1 1 0 1 0 0 0 0 0
Table 2
Clock Cycle Shift-Right Switch Q3 Q2 Q1 Q0

Initial Value Initial Value 0 0 0 0
Cycle 1 1 1 0 0 0
Cycle 2 1 1 1 0 0
Cycle 3 0 0 1 1 0
Cycle 4 0 0 0 1 1
Cycle 5 1 1 0 0 1
Cycle 6 0 0 1 0 0
Cycle 7 0 0 0 1 0

In the shift-right mode (S1S0 = 01) serial inputs are admitted from Q3 to Q0. You can
confirm this aspect by setting the value of the shift-right switch according to the sequence
1100100 as you cycle the clock; see Table 3. Watch as the signals move from Q3 to Q0. In
the shift-left mode (S1S0 = 10) the register works in a similar fashion, except that the signals
move from Q0 to Q3. Finally, in the parallel loading mode (S1S0 = 11) data is read from the
lines L0, L1, L2, and L3 simultaneously. Here, setting L3L2L1L0 = 1010 will cause
Q3Q2Q1Q0 = 1010 after cycling the clock as depicted in Table 4.
Clock Cycle L3 L2 L1 L0 Q3 Q2 Q1 Q0
Initial Value 1 0 1 0 0 0 0 0
Cycle 1 1 0 1 0 1 0 1 0
Table 4
The universal shift register is able to operate in all these modes because of the four-to-one
multiplexers that supply the flipflops. Our 4-bit universal shift register is built with four
blocks each constituted of a 4X1 mux and a D-flipflop. All the blocks are essentially
identical. Because all the multiplexers in the register are wired similarly, Figure 1 shows a
representative multiplexer which we will reference in explaining the design of the universal
register. The L inputs come through port 11, which is why the L inputs are readable only
when S1S0 = 11. The feedback Q wires are connected at port 00, so that when S1S0 = 00 the
output Q of the D-flipflops feed back into the flipflops‟ inputs resulting in no total change in
the register content. Port 01 is wired to facilitate right-shifts. In mode S1S0 = 01 only port 01
is active and it takes its value from the previous more significant flipflop and passes it down
to the flipflop wired to its mux output. Lastly port 10 is wired to conduce to left-shifts. Being
the only active port when S1S0 = 10, it remits the output of the less significant flipflop
sourcing into it to the flipflop wired to its mux output. As a consequence of this wiring
pattern where each block of the register is an exact replica of any other block, the selector
switches are able to align the behavior of all the multiplexers simultaneously. This
coincidence of behavior is what we refer to as mode behavior of the universal register.

4.2.7 Applications of Shift Registers

Switched Tail Counter
A k-bit ring counter circulates a single bit among the flip-flops to provide k distinguishable
states. The number of sates can be doubled if the shift register is connected as a switch-tail
ring counter. Also known as twisted tail counter and Johnson counter. A switch-tail ring
counter is a circular shift register with the complement of the last flip-flop being connected to
the input of the first flip-flop. Figure below shows such a type of shift register.
The circular connection is made from the complement of the rightmost flip flop to the input
of the leftmost flip-fl op. The register shifts its contents once to the right with every clock
pulse, and at the same time, the complement value of the E flip-flop is transferred into the A
flip-fl op. Starting from a cleared state, the switch-tail ring counter goes through a sequence
of eight states as listed in table below.

Sequence Generator and Sequence Detector

A sequence generator is a circuit that generates a desired sequence of bits in synchronization
with a clock. A sequence generator can be used as a random bit generator, code generator,
and prescribed period generator. The block diagram of a sequence generator is shown in
figure below.
A sequence detector will have one register to store the binary word to detect from the data
stream. Input data stream enters a shift register as serial data in and leaves as serial out. At
every checking instant, bit-wise comparisons of these two registers are done through Ex-
NOR gate as shown in the figure below.

Serial Adder
Serial addition is much slower than parallel addition, but requires less equipment.
The two binary numbers to be added serially are stored in two shift registers. Bits are added
one pair at a time, sequentially, through a single full-adder (FA) circuit shown in figure
below. The carry out of the full adder is transferred to a D flip-fl op. The output of this flip-fl
op is then used as an input carry for the next pair of significant bits. The two shift registers
are shifted to the right for one word-time period. The sum bits from the S output of the full
adder could be transferred into a third shift register. By shifting the sum into A while the bits
of A are shifted out, it is possible to use one register to store both the augend and the sum
bits. The serial input (SI) of register B is able to receive a new binary number while the
addend bits are shifted out during the addition.

The operation of the serial adder is as follows. Initially the augend is in register A, the addend
is in register B, and the carry fl ip-fl op is cleared to 0. The serial outputs (SO) of A and B
provide a pair of significant bits for the full-adder at x and y. Output Q of the flip-fl op gives
the input carry as z. The shift-right control enables both registers and the carry flip-fl op.
Hence at the next clock pulse, both registers are shifted once to the right, the sum bit from S
enters the leftmost flip-fl op of A, and the output carry is transferred into the flip-fl op Q. The
shift-right control enables the registers for a number of clock pulses equal to the number of
bits in the registers. For each succeeding clock pulse, a new sum bit is transferred to A, a new
carry is transferred to Q, and both registers are shifted once to the right. This process
continues until the shift-right control gets disabled. Thus the addition is accomplished by
passing each pair of bits together with the previous carry through a single full-adder circuit
and transferring the sum, one bit at a time, into register A.
If a new number has to be added to the contents of register A, this number must be first
transferred into register B. Repeating the process once more will add the second number to
the previous number in A.

4.2.8 Register implementation in HDL
module Reg74174(D, Clock, module SR1(D, Clock, T); module SR2(D, Clock, Q);
Clear, Q); input Clock, D; // Use input Clock, D;
input Clock, Clear; output T; //Clear as in output [3:0] Q; //Clear as
input [5:0] D; reg T; // LHS to initialize reg [3:0] Q;; // LHS to
output [5:0] Q; reg Q, R, S; //internal initialize
always @ (negedge Clock or always @ (negedge Clock) always @ (negedge Clock)
negedge Clear) begin begin
if (~Clear) Q=6‟b0; Q <= D; Q[0] <= D;
// Q stores 6 binary 0 R <= Q; Q[1] <= Q[0];
else Q=D; S <= R; Q[2] <= Q[1];
endmodule T <= S; Q[3] <= Q[2];
end end
endmodule endmodule
4.3 Counters:
A counter is usually constructed from one or more flip-fl ops that change state in a prescribed
sequence when input pulses are received. A counter driven by a clock can be used to count
the number of clock cycles. Since the clock pulses occur at known intervals, the counter can
be used as an instrument for measuring time and therefore period of frequency. Counters can
be broadly classified into three categories:
(i) Asynchronous and Synchronous counters.
(ii) Single and multimode counters.
(iii) Modulus counters.
4.3.1 Asynchronous Counters

The asynchronous counter is simple and straightforward in operation and construction and
usually requires a minimum amount of hardware. In asynchronous counters, each flip flop is
triggered by the previous flip-fl op, and hence the speed of operation is limited. In fact, the

settling time of the counter is the cumulative sum of the individual settling times of the flip-
flops. This type of counters is also called ripple or serial counter.
Ripple Counter
A binary ripple counter can be constructed using clocked JK flip-flops as shown in the figure
below. The circuit has 3 negative edge triggered, JK flip flops connected in cascade. The
system clock, a square wave, drives flip-flop A. The output of A drives B, and the output of B
drives flip flop C.
When the output of a flip flop is used as the clock input for the next flip flop, we call the
counter a ripple counter, or asynchronous counter.
4.3.2 Decoding Gates

A decoding gate can be connected to the outputs of a counter in such a way that the output of
the gate will be high (or low) only when the counter contents are equal to a given state.
An example of decoding 7 from a 3-bit ripple counter is shown below.

4.3.3 Synchronous Counters

The ripple or asynchronous counter is the simplest to build, but its highest operating
frequency is limited because of ripple action. Each flip-flop has a delay time. In ripple
counters these delay times are additive and the total “settling” time for the counter is
approximately the product of the delay time of a single flip-flop and the total number of flip-
flops. Again, there is the possibility of glitches occurring at the output of decoding gates used
with a ripple counter.
Both of these problems can be overcome, if all the flip-flops are clocked synchronously. The
resulting circuit is known as a synchronous counter.
A 4-bit synchronous counter is shown in figure below. The basic idea here is to keep the J
and K inputs of each flip flop high, such that the flip-flop will toggle with any clock negative
transition at its clock input. The clock is applied directly to flip flop A. Since the JK flip flop
used responds to a negative transition at the clock input and toggles when both the J and K
inputs are high, flip flop A will change state with each clock negative transition.

Whenever A is high, AND gate X is enabled and a clock pulse is passed through the gate to
the clock input of flip flop B. Thus B changes state with every other clock negative transition
at points b, d, f, and h on the time line.
Since AND gate Y is enabled and will transmit the clock to flip flop C only when both A and
B are high, flip flop C changes state with every fourth clock negative transition at points d
and h on the time line.
Examination of the waveform and the truth table reveals that this counter progresses upward
in a natural binary sequence from 000 to 111, advancing one count with each clock negative
transition. This is a mod 8 parallel or synchronous binary counter operating in the count-up
mode.
4.3.4 Changing the Counter Modulus
All of the counters progress one count at a time in a strict binary progression, and they all
have a modulus given by 2n. It is often desirable to construct counters having a modulus other
than 2, 4, 8 and so on. For example, a counter having modulus of 3 or 5 would be useful. A
small modulus counter can always be constructed from a larger modulus counter by skipping
states. Such counters are said to have a modified count.

A Mod-3 Counter
A MOD-3 counter is a counter which has only three distinct states. To design a counter with
three states, the number of flip-flops required can be found using the equation , where n is the
number of flip-flops required and N is the number of states present in the counter. For N = 3,
from the above equation, n = 2, i.e., two flip-flops are required.
The logic diagram, waveform and truth table of MOD-3 counter using JK Flip flop is given
below.
A Mod-6 Counter
Higher modulus counters can be formed by using the product of any number of lower-
modulus counters.
Connect a flip-flop at the B output of the mod-3 counter as shown in the figure below. The
result is a (3 X 2 = 6) mod-6 counter.

Module-5
5.1 Counters:
5.1.1 Decade Counters
A Mod 5 Counter
The design of Mod-5 counter is similar to Mod-3 counter except that the number of flip-flops
required is 3. Below are the circuit connection, waveform and truth table which realizes Mod
5 counter.
A Mod 10 Counter
Mod 10 Counter can be developed by cascading two Mod-5 counter as shown in the figure
below.

5.1.2 Pre settable Counters
The up-counters generally start the count sequence from 00….0 state while down-counters
start from 11.…1 state. This is accomplished by applying a momentary pulse to all the flip
flop‟s CLEAR inputs before the counting operation begins. A counter can also be made to
start counting in any desired state through the use of appropriate logic circuitry. Counters that
have the capability to start counting from any desired state are called presettable or
programmable counters.
A presettable MOD-16 ripple up-counter is illustrated in figure below. In this counter, the
desired state is entered using the PRESET and CLEAR inputs irrespective of what is
happening at the J and K or the clock inputs. The desired preset count is determined by the
preset inputs PA, PB, PC, and PD whose values are transferred into the counter flip flops
when the PRESET LOAD input is momentarily pulsed to the LOW level. When the PRESET
LOAD input returns to HIGH, the NAND gates are disabled and the counter is free to count
input clock pulses starting from the newly entered count that has been preset into the flip-
flops.
5.1.3 Counter Design as a Synthesis problem
Following certain general steps, synchronous counters of any given count sequence and
modulus can be designed. The steps are listed below:
Step 1: From the given word description of the problem, draw a state diagram that describes
the operation of the counter.

Step 2: From the state table, write the count sequences in the form of a table as shown in table
below.
Step 3: Find the number of flip-flops required.

Step 4: Decide the type of flip-flop to be used for the design of the counter. Then determine
the flip-flop inputs that must be present for the desired next state from the present state using
the excitation table of the flip-flops.
Step 5: Prepare K-maps for each flip-flop input in terms of flip-flop outputs as the input
variables. Simplify the K-maps and obtain the minimized expressions.
Step 6: Connect the circuit using flip-flops and other gates corresponding to the minimized
expressions.

5.1.4 A Digital Clock, Counter
A digital clock, which displays the time of day in hours, minutes, and seconds, is one of the
most common applications of counters. To construct an accurate digital clock, a very highly
controlled basic clock frequency is required. For battery-operated digital clocks (or watches)
the basic frequency can be obtained from a quartz-crystal oscillator. Digital clocks operated
from the AC power line can use the 50 Hz power frequency as the basic clock frequency. In
either case, the basic frequency has to be divided down to a frequency of 1 Hz or pulse of 1
second (pps). The basic block diagram for a digital clock operating from 50 Hz is shown in
figure below.
The 50 Hz signal is sent through a Schmitt trigger circuit to produce square pulses at the rate
of 50 pps. The 50 pps waveform is fed into a MOD-50 counter, which is used to divide the 50
pps down to 1 pps. The 1-pps signal is then fed into the SECONDS section. This section is
used to count and display seconds from 0 through 59. The BCD counter advances one count
per second. After 9 seconds the BCD counter recycles to 0. This triggers the MOD-6 counter
and causes it to advance one count. This continues for 59 seconds. At this point, the BCD
counter is at 1001 (9) count and the MOD-6 counter is at 101 (5). Hence, the display reads 59
seconds. The next pulse recycles the BCD counter to 0. This, in turn, recycles the MOD-6
counter to 0.

The output of the MOD-6 counter in the SECONDS section has a frequency of 1 pulse per
minute. This signal is fed to the MINUTES section, which counts and displays minutes from
0 through 59. The MINUTES section is identical to the SECONDS section and operates in
exactly the same manner.
The output of the MOD-6 counter in the MINUTES section has a frequency of 1 pulse per
hour. This signal is fed to the HOURS section, which counts and displays hours from 1
through 12. The HOURS section is different from the MINUTES and SECONDS section in
that it never goes to the zero state. The circuitry in this section is different. When the hours
counter reaches 12, it will be reset to zero by the NAND gate.
5.1.5 Design using HDL
module UC(Clock, Reset, Q); module UCJK(A, B, Clock, Reset);

input Clock, Reset; input Clock, Reset;
output [2:0] Q; output A, B; //modulo-3 requires 2 flip flops
// modulo 8 requires 3 flip flop wire JA, JB, KA, KB;
reg [2:0] Q; assign JA=-B;
always @ (negedge Clock or negedge assign KA=1‟b1;
Reset) assign JB=A;
if (~Reset) Q=3‟b0; assign
else Q = Q+1; KB=1‟b1;
endmodule JKFF JK1 (A, JA, KA, Clock, Reset);
//instantiates JKFF
JKFF JK2(B, JB, KB, Clock, Reset); //instantiates
JKFF
endmodule
module JKFF(Q, J, K, Clock, Reset);

input J, K, Clock, Reset;
output Q;
reg Q;
always @ (negedge Clock or negedge Reset)
if(~Reset) =1‟b0;
else Q <= (J&~Q) | (~K&Q);

endmodule

5.2 D/A Conversion and A/D Conversion:
Digital-to-analog conversion involves translation of digital information into equivalent

analog information.Analog-to-digital conversion involves translation of analog signal to an
equivalent digital signal.
5.2.1 Variable, Resistor Networks
The basic problem in converting a digital signal into an equivalent analog signal is to change
the n digital voltage levels into one equivalent analog voltage. This can be accomplished by
designing a resistive network that will change each digital level into an equivalent binary
weighted voltage (or current).
Binary Equivalent Weight
Consider the truth table for the 3-bit binary signal. Suppose that we want to change the eight
possible digital signals into equivalent analog voltages. The smallest number represented is
00. Let us make this equal to 0 V. The largest number is 111, let us make this equal to +7 V.
This then establishes the range of the analog signal to be developed.
If we divide the analog signal into seven levels, then the smallest increment change in the
digital signal is represented by the least significant bit (LSB), 20. Thus we would like to have
this bit cause a change in the analog output that is equal to one-seventh of the full scale
analog output voltage. The resistive divider will then be designed such that a 1 in the 20
position will cause 7 (1/7) = 1 V at the output.
Since 21 = 2 and 20 = 1, it can be clearly seen that the 21 bit represents a number that is twice
the size of the 20 bit. Therefore, a 1 in the 21 bit position must cause a change in the analog
output voltage that is twice the size of the LSB. The process can be continued, and it will be
seen that each successive bit must have a value twice that of the preceding bit.
Resistive Divider
A resistive divider that has three digital inputs and one analog output is shown in the figure
below.

The resistive divider must do two things in order to change the digital input into an equivalent
analog output voltage:
1. The 20 bit must be changed to +1V, and 21 bit must be changed to +2V, and 22 bit
must be changed to +4V.
2. These three voltages representing the digital bits must be summed together to form
the analog output voltage.
A resistive divider that performs these functions is shown in the figure below. Resistors R0,
R1 and R2 form the divider network. Resistance RL represents the load to which the divider
is connected and is considered to be large enough that it does not load the divider network.
5.2.2 Binary Ladders
The binary ladder is a resistive network whose output voltage is a properly weighted sum of
the digital inputs.
An example of 4 bit ladder is shown below.
Examine the resistive properties of the network, assuming that all the digital inputs are at
ground. Beginning at node A, the total resistance looking into the terminating resistor is 2R.
The total resistance looking out toward the 20 input is also 2R. These two resistors can be
combined to form an equivalent resistor of value R as shown in the figure below.

Similarly, the total resistance looking from node B and C are calculated. Then the output
voltage VA is determined for all combination of digital inputs at A, B and C.
5.2.3 D/A Converters
Apart from conversion of digital signal to analog voltage, some additional circuitry is need to
complete the D/A converters.
1. A register is used to store the digital information.
2. Level amplifiers between the register and the resistive network to ensure that the
digital signals presented to the network are all of the same level and are constant.
3. Some form of gating on the input of the register such that the flip flops can be set with
the proper information from the digital system.
A complete D/A converter block diagram is shown below.

D/A Converter Testing

Two important tests that can be performed to check the proper operation of the D/A converter
are the
1. Steady state accuracy test: This test involves setting a known digital number in the
input register, measuring the analog output with an accurate meter, and comparing
with the theoretical value.
2. Monotonicity test: This test involves checking that the output voltage increases
regularly as the input digital signal increases.

5.2.4 D/A Accuracy and Resolution
Resolution
It is defined by the smallest possible change in the output voltage as a fraction or percentage
of the full-scale output range. If an 8-bit D/A converter is considered for an example, there
are 28 or 256 possible values of output analog voltage. Hence the smallest change in the
output voltage is 1/255th of full-scale output range. Therefore, the resolution is calculated as
1/255 or 0.4%. So a general expression of resolution for an N-bit D/A converter may be
defined as below.
Alternatively, resolution is also defined by the number of bits accepted by the D/A converter.
For example, a 12-bit D/A converter has 12-bit resolution.
Accuracy
The accuracy of a D/A converter is determined by the measure of the difference between the
actual output voltage and the expected output voltage. It is specified as the percentage of
maximum output or the full-scale output voltage. For example, if a D/A converter is specified
as the accuracy of 0.1%, with full-scale of maximum output voltage of 10 V, the maximum
error at output voltage corresponding to any input combination will be 10 × 0.1/100 V = 10
mV.
5.2.5 A/D Converter- Simultaneous Conversion
The process of converting an analog voltage into an equivalent digital signal is known as
analog-to-digital conversion. This operation is somewhat more complicated than the converse
operation of D/A conversion.
Simultaneous method of A/D conversion is based on the use of a number of comparator
circuits. One such system using three comparator circuits is shown below. The analog signal
to be digitized serves as one of the inputs to each comparator. The second input is a standard
reference voltage. The reference voltages used are +V/4, +V/2 and +3V/4. The system is then
capable of accepting an analog input voltage between 0 and +V.

5.2.6 A/D Converter-Counter Method
For construction of high resolution A/D converter we can use counter method.
The digital output signals will be taken from a simple binary n-bit counter, where n is the
desired number of bits. Connect the output of this counter to a standard binary ladder to form
a simple D/A converter. If a clock is now applied to the input of the counter, the output of the
binary ladder is the staircase waveform. The waveform is the reference voltage signal we
would like to have for the comparator with a minimum of gating and control circuitry, this
simple D/A converter can be changed into the desired A/D converter.
Figure below shows the block diagram of a counter type A/D Converter.

5.2.7 Continuous A/D Conversion
For speeding up the conversion of the signal, we should eliminate the need for resetting the
counter each time a conversion is made. If this were done, the counter would not begin at
Zero each time, but instead would begin at the value of the last converted point. This means
that the counter would have to be capable of counting either up or down which can be done
using Up-Down counter.
This method is known as continuous conversion, and thus the converter is called an
continuous type A/D converter.
The block diagram and waveform of continuous A/D converter is shown below.

5.2.8 A/D Techniques
Successive Approximation
The block diagram of successive approximation converter is shown below. The converter
operates by successively dividing the voltage ranges in half. The counter is first reset to all
0s, and the MSB is then set. The MSB is then left in or taken our depending on the output of
the comparator. Then the second MSB is set in, and a comparison is made to determine
whether to reset the second MSB flip-flop. The process is repeated down to the LSB, and at
this time the desired number is in the counter. Since the conversion involves operating on one
flip flop at a time, beginning with the MSB, a ring counter may be used for flip flop selection.

Section Counters
Another method for reducing the total conversion time of a simple counter converter is to
divide the counter into sections. Such a configuration is called a section counter. To
determine how the total conversion time might be reduced by this method, assume that we
have a standard 8-bit counter. If this counter is divided into two equal counters of 4 bits each,
we have a section converter. The converter operates by setting the section containing the four
LSBs to all 1s and then advancing the other sections until the ladder voltage exceeds the input
voltage. At this point the four LSBs are all reset, and this section of the counter is then
advanced until the ladder voltage equals the input voltage.
5.2.9 Dual-slope A/D Conversion
This type of conversion is another method of A/D conversion which involves comparison of
the unknown input voltage with a reference voltage that begins at zero and increases linearly
with time. The time required for the reference voltage to increase to the value of the unknown
voltage is directly proportional to the magnitude of the unknown voltage, and this time period
is measured with a digital computer. This is referred to as a single-ramp method. A variation
on this method involves using an operational amplifier integrating circuit in a dual-ramp
configuration. The dual-ramp method is very popular and widely used in digital voltmeters
and digital panel meters. It offers good accuracy, good linearity and very good noise-rejection
characteristics.
Dual Slope A/D Converter

The logic diagram of a basic dual slope A/D converter is shown below. A conversion cycle
begins with the decade counters cleared to all 0s, the ramp reset to 0.0V, and the input
switched to the unknown input voltage VX. Since VX is positive, the integrator outputs Vc
will be a negative ramp. The comparator output Vg is thus positive and the clock is allowed
to pass through the CLOCK GATE to the counters. Ramp is proceeded for a fixed time
period.

5.2.10 A/D Accuracy and Resolution
The source of the digital error is simply determined by the resolution of the system. Analog
signals are continuous and digital form after conversion is a discontinuous signal composed
of a number of discrete steps. The ladder voltage has steps in it leads to the digital error in the
system. The smallest digital step, or quantum, is due to the LSB. This inherent error is often
called the quantization error.
The main source of analog error in the A/D converter is probably the comparator. The
sources of error in the comparator are centered around variations in the dc switching point.
The dc switching point is the difference between the input voltage levels that cause the output
to change state. Variations in switching are primarily to offset, gain and linearity of the
amplifier used in the comparator.

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Analog and Digital Electronics 15CS32

Analog and Digital Electronics

Subject Code 15CS32 IA Marks 20

Dept .of CSE, SJBIT Page 1

Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD to Decimal

Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce

Dept .of CSE, SJBIT Page 2

1. Anil K Maini, VarshaAgarwal: Electronic Devices and Circuits, Wiley, 2012.

1. Stephen Brown, ZvonkoVranesic: Fundamentals of Digital Logic Design with VHDL,

Dept .of CSE, SJBIT Page 3

1.1 Field Effect Transistors: 8 - 42

2.1 The Basic Gates: 43 - 65

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2.2.4 Don‟t-care Conditions, Product-of-sums Method

3.1 Data-Processing Circuits: 66 - 89

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4.1 Flip- Flops: 90 - 109

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5.2.3 D/A Converters

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1.1 Field Effect Transistors:

Typical Field Effect Transistor

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1.1.1 Junction Field Effect Transistors

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Comparison of connections between a JFET and a BJT

Bipolar Transistor Field Effect Transistor

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JFET Channel Pinched-off

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 No Gate voltage ( VGS ) and VDS is increased from zero.

Output characteristic V-I curves of a typical junction FET

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Drain current in the active region.

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Drain-Source channel resistance.

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 Enhancement Type – the transistor requires a Gate-Source voltage, ( VGS ) to

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Basic MOSFET Structure and Symbol

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The depletion-mode MOSFET is constructed in a similar way to their JFET transistor

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Enhancement-mode N-Channel MOSFET and Circuit Symbols

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Dept .of CSE, SJBIT Page 21

VGS = VGS = VGS =

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1.1.3 Differences between JFETs and MOSFETs

1. Comparing to the JFET, MOSFETs are easier to fabricate.

1.1.4 Biasing MOSFETs

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1.1.5 FET Applications

1. Low Noise Amplifier. Noise is an undesirable disturbance super-imposed on a useful

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Cascode amplifier circuit

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VOUT = {RDS/ (RD + RDS (ON))}* Vin

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Dept .of CSE, SJBIT Page 27

JFET current Limiter