Sequential Circuits

† Have considered only combinational circuits in which circuit outputs are determined
entirely by current circuit inputs.
† We can include storage elements into a circuit that act like memory and store a
system state.

combinatorial
inputs circuit outputs

memory state
elements

† Outputs are then a function of both the current circuit inputs and the system
state.

E&CE 223 Digital Circuits and Systems Page 1

Types of Sequential Circuits

† Two main types of sequential circuits (classification depends on how timing

happens):
„ Synchronous Sequential Circuits – circuit behavior is determined from the
knowledge of signal values at discrete instances in time.
„ Asynchronous Sequential Circuits - circuit behavior is determined by signals
at any instant in time and the order in which input signals change.

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Synchronous Sequential Circuits

† To control the behavior of a circuit at discrete instances in time, we will need to

introduce the concept of a clock.
† It’s a periodic signal consisting of a sequence of pulses. It is used to control the
times at which the storage elements in the circuit change their values.
† The storage elements used can be latches or flip-flops.

combinatorial
inputs circuit outputs

storage state
elements
clock/
control
clock/
control

† The clock/control connects to the storage elements which are latches or flip-flops.

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Clocks

† Clocks are periodic.

† They can control when things happen because their transition from 0-> 1 and from
1 -> 0 occur at discrete instances in time.

† The 0 -> 1 transition is often called the rising edge of the clock.

† The 1 -> 0 transition is often called the falling edge of the clock.

1
clock
0

rising edge (0->1 falling edge (1->0

transition) transition)

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Latches

† Latches are level sensitive storage elements;

„ They operate based on whether signals are at logic levels 0 or 1, not on logic
transitions from 0 -> 1 or 1 -> 0.

† Latches are not really too useful for synchronous sequential circuits (they are for
asynchronous circuits), but form the basis from which flip-flops are built.

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SR Latch (NOR Implementation) Illustrated

† Consider the operation of the following circuit:

R (reset) Q

S (set) !Q

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SR Latch (NOR Implementation) Explained

† In general (one exception, see below), the outputs are complements of each other
(this is why they are labeled Q and :Q):

„ When S=1, R=0 the output is Q=1, :Q=0 and the circuit in the set state.

„ When S=0, R=1 the output is Q=0, :Q=1 and the circuit in the reset state.

† So, S=1 (active high) implies set (Q=1) and R=1 (active high) implies reset (Q=0).

† When S=0, R=0 the output holds at its previous value (storage).

† When S=1, R=1 the output is Q=:Q=0 which is not desirable.

„ We want to avoid this combination of inputs.

E&CE 223 Digital Circuits and Systems Page 7

S’R’ Latch (NAND Implementation) Illustrated

† Consider the operation of the following circuit:

S (set) Q

R (reset) !Q

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S’R’ Latch (NAND Implementation) Explained

† In general (one exception, see below), the outputs are complements of each other
(this is why they are labeled Q and :Q):

„ When S=0, R=1 the output is Q=1, :Q=0 and the circuit in the set state.

„ When S=1, R=0 the output is Q=0, :Q=1 and the circuit in the reset state.

† So, S=0 (active low) implies set (Q=1) and R=0 (active low) implies reset (Q=0).

† When S=1, R=1 the output holds at its previous value (storage).

† When S=0, R=0 the output is Q=:Q=1 which is not desirable.

„ We want to avoid this combination of inputs.

† So, it works similar to the NOR implementation, but the input values are reversed for
each of the different cases.
E&CE 223 Digital Circuits and Systems Page 9
Latch With Control Input (i.e., Gated Latch)

† We can add an additional control input that acts as an enable signal.

† Consider adding some extra NAND gates in front of an S’R’ Latch.

† This gives us a SR Latch with control input.

S
Q
C
!Q
R

E&CE 223 Digital Circuits and Systems Page 10

Latch With Control Input Explained

S
Q
C
!Q
R

† When the control input C=0,

„ The inputs to the latch are both 1 which puts the SR latch into hold state.
„ The latch outputs will not change regardless of S and R values.

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Latch With Control Input (NAND Implementation)

S
Q
C
!Q
R

† When the control input C=1,

„ The S and R inputs will reach the latch and we can analyze the behavior.

† The NAND gates at the input to the latchresult in active high inputs:

„ S=1 (and R=0) causes a set (Q=1).

„ R=1 (and S=0) causes a reset (Q=0).

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D Latch

† We must avoid the undesirable situation in which we cannot determine what the
output of the latch will be…

„ i.e., we never want S=1, R=1 when C=1 (bad!)

† The solution is to construct a latch where S and R can never have the same
value.

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D Latch Illustrated

D
Q
C
!Q

† We still have a hold state when the control input C=0.

† The output Q follows input D when the control input C=1.

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Schematic Symbol for SR Latch (With and Without Control Input)

S Q S Q
C
R R

† Note: as illustrated, this means the inputs are active high; i.e., we set when S=1 (and
R=0) and we reset with R=1 (and S=0).

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Schematic Symbol for S’R’ Latch (With and Without Control Input)

S Q S Q
C
R R

† Note: as illustrated, this means the inputs are active low; i.e., we set when S=0 (and
R=1) and we reset with R=0 (and S=1).

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Schematic Symbol for D Latch (With Control Input)

D Q

† Note: For a D Latch, the control input is required, since it is via the control input that
we have the hold state.

E&CE 223 Digital Circuits and Systems Page 17

Textbook Sections

† Information on Sequential Circuits, Synchronous Sequential Circuits and Latches can

be found in the course textbook in Chapter 5, Sections 5.1 and 5.2.

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Problem With Latches

† Latches do not allow for precise control because they are level sensitive.
„ Consider a D-Latch with the clock signal connected to the control input.
„ Output of the latch can change anytime while the clock is at its active level.

† This creates an interval in time over which the state, or output, of the memory
element can change rather that an instant in time at which the state, or output, of
the memory element can change.

† It would be better to only allow the output to change when the clock edge makes a
transition from 0 ! 1 (rising edge triggering) or 1 ! 0 (falling edge triggering). This
gives even more precise control!

† Flip-flops give more precise control by being edge-triggered.

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Triggering Illustrated

† Response to positive level (a latch) – large window of time for output to change.

† Positive Edge Triggering. The input to the flip-flop just before the clock changes
from 0 ! 1 causes the output to change just after the clock changes from 0 ! 1.

† Negative Edge Triggering. The input to the flip-flop just before the clock changes
from 1 ! 0 causes the output to change just after the clock changes from 1 ! 0.

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Negative Edge Triggered D Flip-Flop (Master-Slave)

† We can make a negative edge triggered D-type flip-flop (DFF) using two D latches.

„ We connect the clock input to the control input of the first latch (master),
and the inversion of the clock input to the control input of the second latch
(slave).

D Latch D Latch
(master) Y (slave)
D D Q D Q Q

CLOCK C C

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Operation of Negative Edge Triggered D Flip-Flop (Master-Slave)

D Latch D Latch
(master) Y (slave)
D D Q D Q Q

CLOCK C C

† While CLK=1, Y will follow input D via the master latch, but Q will not follow Y (it
is in hold state) and will hold its current value.

† When CLK=0 (at the moment of change), Y will be disconnected from D and will
hold its current value. Q will follow Y via the master latch.

† The effect is that the value of D just prior to the falling edge of the clock will
get “transferred” to the output Q just after the falling edge of the clock.

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Positive Edge Triggered D Flip-Flop (Master-Slave)

† We can make a positive edge triggered DFF simply by changing the inversion of the
clock signal
„ Output of master latch, Y, follows D when clock is low (slave in hold).
„ Output of slave latch, Q, follows Y when clock is high (master in hold).

D Latch D Latch
(master) Y (slave)
D D Q D Q Q

CLOCK C C

E&CE 223 Digital Circuits and Systems Page 23

Schematic Symbols for DFFs

† We can introduce schematic symbols for DFFs.

„ Note the indication of the clock input and the change to the symbols (vs. a D
latch) to indicate edge-triggering.

† Positive Edge-Triggered DFF:

D Q

† Negative Edge-Triggered DFF:

D Q

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More Efficient Design of a DFF

† Master-Slave is not the most efficient way to build an edge-triggered DFF.

† The circuit below acts as a positive edge-triggered DFF:

S
Q

R !Q
CLK

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More Efficient Design of a DFF Explained (CLK=0)

† When CLK=0, both S=1 and R=1 and the output latch will hold its state.

1 hold
S
Q

0 R
1
CLK !Q

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More Efficient Design of a DFF Explained (D=0 when CLK=0 ! 1)

† When D=0 and CLK = 0 ! 1, R = 1 ! 0 and the output latch goes into its reset
state (Q=0).
„ Further changes in D while CLK=1 cannot change R and Q=D just after
clock changes.

1 reset
S
Q Q->0
0->1 1->0
R !Q
CLK

0 1
D

E&CE 223 Digital Circuits and Systems Page 27

More Efficient Design of a DFF Explained (D=1 when CLK=0 ! 1)

† When D=1 and CLK = 0 ! 1, S = 1 ! 0 and the output latch goes into its set state
(Q=1).
„ Further changes in D while CLK=1 cannot change S and Q=D just after
clock changes.

1
set
1->0
S
Q Q->1
0->1 1
R !Q
CLK

1 0
D

E&CE 223 Digital Circuits and Systems Page 28

Sets and Resets

† Sometimes flip-flops will have additional, asynchronous control inputs that force
the output Q to a particular value.

† An asynchronous signal that forces Q=1 is called an asynchronous set or preset.

„ The output will remain 1 as long as the set input is active (changes in D and CLK
are ignored).

† An asynchronous signal that forces Q=0 is called an asynchronous clear or reset.

„ The output will remain 0 as long as the reset input is active (changes in D and
CLK are ignored).

E&CE 223 Digital Circuits and Systems Page 29

Reset Illustrated

† The following circuit has an (active low) asynchronous reset.

reset/
hold
S1 0
Q

0/1 R !Q
CLK
1
D
1
RESET 0

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Schematic Symbols for DSRFFs (DFF With Resets and Sets)

† Active low set and reset signals.

D S Q

† Active high set and reset signals.

D S Q

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Characteristic Tables and Equations

† We can describe the behavior of a flip-flop via a characteristic table.

„ The characteristic table shows what the next flip-flop output value will be given
the current flip-flop input value after the clock makes its active edge
transition.

† The characteristic table for a DFF is:

† We can also write this as a characteristic equation:

† For a DFF, the output value becomes the input value when the clock makes its active
edge transition.

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Toggle Flip-Flops (TFF)

† Another type of flip-flop that has a different behavior when compared to a DFF.

† Symbol for a positive edge-triggered TFF:

T Q

† Symbol for a negative edge-triggered TFF:

T Q

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Behavior of a TFF

† The characteristic table for the TFF:

† The characteristic equation for the TFF:

† So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it
remains the same.

E&CE 223 Digital Circuits and Systems Page 34

Construction Of A TFF Using a DFF

† We can actually build a TFF using a DFF and a 2-input XOR gate.

D Q Q T Q
T

CLOCK

E&CE 223 Digital Circuits and Systems Page 35

JK Flip-Flops (JKFF)

† Again, another type of flip-flop that has different behavior compared to a DFF or to
a TFF.

† Positive edge-triggered JKFF:

J Q

† Negative edge-triggered JKFF:

J Q

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Behavior of a JKFF

† The characteristic table for the JKFF:

† We can derive the characteristic equation for the JKFF (I find it easy to explain via
a K-Map):
JK

Q(t) 00 01 11 10

0 0 0 1 1

1 1 0 0 1

E&CE 223 Digital Circuits and Systems Page 37

Construction Of A JKFF Using a DFF

† We can actually build a JKFF using a DFF and some other gates.

J
J Q
D Q Q

K K
CLOCK

E&CE 223 Digital Circuits and Systems Page 38

Circuit Timing With Flip-Flops

† There are some important things to understand when we go to actually make and
implement a circuit with flip-flops.

† In reality, it takes time for gates to change their output values according to the
input values – i.e., there are propagation delays due to resistance, capacitance, etc.

† Changes in flip-flop outputs occur at the active clock edge.

† There are three timing parameters that are especially important:

„ Setup Time (TSU).

„ Hold Time (TH).

„ Clock-To-Output Time (TCO).

E&CE 223 Digital Circuits and Systems Page 39

Definitions

† Setup Time (TSU):

„ The setup time of a flip-flop is the amount of time that the data inputs need to
be held stable (not changing) PRIOR to the arrival of the active clock edge.

† Hold Time (TH):

„ The hold time of a flip-flop is the amount of time that the data inputs need to
be held stable (not changing) AFTER the arrival of the active clock edge.

† Clock-To-Output (TCO):

„ The clock-to-output time of a flip-flop is the amount of time it takes for the
output to become stable (at its new value) AFTER the arrival of the active
clock edge.

E&CE 223 Digital Circuits and Systems Page 40

Comments

† If these timing specifications are not met, then it is possible that the flip-flop will
not behave as expected.

† That is, if we don’t observe setup and hold times at the data inputs, then our output
might not change as expected.

† That is, if we don’t wait long enough (clock-to-output time) for the output to change,
then we might use an incorrect value.

† If we violate any of these timing parameters, then we have a timing violation.

† These timing parameters (as we will see later) have an influence on how fast we
can clock a circuit.

E&CE 223 Digital Circuits and Systems Page 41

Timing Parameters Illustrated (Using A DFF)

TCO
D Q
TSU TH

CLOCK

D should not change in this interval

Q not stable (trustworthy) until this interval ends

E&CE 223 Digital Circuits and Systems Page 42

Textbook Sections

† Information on Flip-Flops can be found in the course textbook in Chapter 5, Section

5.3.

E&CE 223 Digital Circuits and Systems Page 43