DDR3 SDRAM

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 WHAT IS DDR?

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Double Data Rate Synchronous Dynamic Random-Access
Memory or DDR SRAM, is a double data rate class of memory
integrated circuits used in computers.
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Compared to single data rate SDRAM, the DDR SDRAM interface
makes higher transfer rates possible by more strict control of
the timing of the electrical data and clock signals.
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The interface uses double pumping to double data bus
bandwidth without a corresponding increase in clock
frequency.

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DOUBLE PUMPING

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Transferring data on both the rising and falling edges of the
clock signal is calles double pumping.
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The name "double data rate" refers to the fact that a DDR
SDRAM with a certain clock frequency achieves nearly twice
the bandwidth of a SDR SDRAM running at the same clock
frequency, due to this double pumping.
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With data being transferred 64 bits at a time, DDR SDRAM
gives a transfer rate 16 (in bytes/s) . Thus, with a bus
frequency of 100 MHz, DDR SDRAM gives a maximum
transfer rate of 1600 MB/s.

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 MODULES
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A DIMM or dual in-line memory module comprises a series of
dynamic random-access memory .
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Multiple chips with the common address lines are called a
memory rank.
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A memory rank is a set of DRAM chips connected to the same
chip select, which are therefore accessed simultaneously. In
practice all DRAM chips share all of the other command and
control signals, and only the chip select pins for each rank are
separate.
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DDR SDRAM modules for desktop computers, DIMMs have 184
pins.
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Most DDR SDRAM operates at a voltage of 2.5 V, compared to
3.3 V for SDRAM. This can significantly reduce power
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consumption.
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FUNCTIONAL DESCRIPTION:
● The DDR SDRAM is a high-speed CMOS, dynamic random
access memory internally configured as a quad--bank DRAM.
● The DDR SDRAM uses a double data rate architecture to achieve
high speed operation. The double data rate architecture is
essentially a 2n prefetch architecture.
● Read and write accesses to the DDR SDRAM are burst oriented.

Registrations:
● ACTIVE
● READ and WRITE
● MODE REGISTER SET

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 MODE REGISTER
● The Mode Register is used to define the specific mode of
operation of the DDR SDRAM.
● This definition includes the selection of a burst length, a burst type,
a CAS latency, and an operating mode

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 EXTENDED MODE REGISTER
● The Extended Mode Register controls functions beyond those
controlled by the Mode Register; these additional functions include
DLL enable/disable, output drive strength selection.
● The Extended Mode Register is programmed via the MODE
REGISTER SET command.

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COMMANDS

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READ Transfer:

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WRITE Transfer:

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 DDR3 SDRAM
●
The DDR3 SDRAM is a high-speed dynamic random-access
memory internally configured as an eight-bank DRAM.
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The DDR3 SDRAM uses a 8n prefetch architecture to achieve
high-speed operation.
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Power-up Initialization Sequence
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Reset Initialization with Stable Power

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 MODE REGISTER
Mode Register MR0:

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The mode register MR0 stores the data for controlling various
operating modes of DDR3 SDRAM.
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It controls burst length, read burst type, CAS latency, test
mode, DLL reset, WR and DLL control for precharge Power-
Down, which include various vendor specific options to make
DDR3 SDRAM useful for various applications.

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Mode Register MR1:
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The Mode Register MR1 stores the data for enabling or disabling
the DLL, output driver strength, Rtt_Nom impedance, additive
latency, Write leveling enable, TDQS enable and Qoff.

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Mode Register MR2:
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The Mode Register MR2 stores the data for controlling refresh
related features, Rtt_WR impedance, and CAS write latency.

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 Mode Register MR3:
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The Mode Register MR3 controls Multi purpose registers.

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Input clock frequency change
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The input clock frequency can be changed from one stable
clock rate to another stable clock rate under two conditions:
(1) Self-Refresh mode and (2) Precharge Power-down mode.
Outside of these two modes, it is illegal to change the clock
frequency.
Write Leveling:
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For better signal integrity, the DDR3 memory module adopted
fly-by topology for the commands,addresses, control signals,
and clocks.

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WRITE Transfer:

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