iCE40HX-8K Breakout Board User Guide

EB85 Version 1.1, January 2016

 iCE40HX-8K Breakout Board

Introduction
Thank you for choosing the Lattice iCE40HX-8K Breakout Board.

This document provides technical information and instructions for using the iCE40HX-8K Breakout Board. This kit
is based on the Lattice iCE40-HX8K-CT256 high performance FPGA device. Two source codes, one written in Ver-
ilog and the other in VHDL, are available to download for the iCE40HX-8K Breakout Board. Both codes are func-
tionally the same.

The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of
the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and the bill
of materials for the iCE40HX-8K Evaluation Board.

Features
The iCE40HX-8K Breakout Board includes:

• iCE40HX-8K Evaluation Board – The iCE40HX-8K Evaluation Board features the following on board capabili-
ties:
—iCE40HX-8K CT256 device
—8 user accessible LEDs
—SPI Flash for programming configuration
—40 pin 0.1” header for user connectivity
—0.1” holes for user connectivity
—FTDI 2232H for USB interface
—12MHz oscillator
—Jumpers to select programming the SPI flash or iCE40HX-8K
• Pre-loaded Demo – The kit comes with a default design that flashes the LEDs on and off
• USB connector Cable – A mini B USB cable for programming the SRAM fabric of the iCE40HX-8K or the on-
board SPI flash. The USB cable also powers the iCE40HX-8K evaluation board.

Figure 1 shows the top side of the iCE40HX-8K Evaluation Board indicating the specific features that are designed
on the board.

2
 iCE40HX-8K Breakout Board

Figure 1. iCE40HX-8K Evaluation Board (Top Side)

LEDs

iCE40HX-8K

0.1" spaced holes

40 pin header

USB

Figure 2. Block Diagram

HEADER
I/Os
LEDS(1-8)

BANK 0
HEADER

I/Os

HEADER
BANK 3

BANK 1

I/Os
FPGA
iCE40HX8K-CT256
USB USB to RS232
SPI / RS232 Power from USB 5V
CONNECTOR

BANK 2
I/Os

HEADER SPI

3
 iCE40HX-8K Breakout Board

iCE40 Device
This board features an iCE40HX-8K device with a 1.2v core supply. It is packaged in a 256 caBGA package. For a
complete description of this device, see HB1011, iCE40 LP/LX/LM Family Handbook.

Software Requirements
You should install the following software before you begin developing designs for the evaluation board:

• Lattice iCEcube2 Release: 2012.09SP1.22498 or later

• Diamond Programmer: Version 2.2 or later

These software are available at the Lattice website Design Software & IP page. Make sure you log in to the Lattice
website, otherwise these software downloads will not be visible.

Demonstration Design
The design file iCE40HX8KLED.zip contains the following files:

• LED_VHDL.vhd (VHDL code)

• LED_Verilog.v (Verilog code)
• LED.pcf (pin constraint file)
• LED_VHDL_bitmap.hex (Bit stream file for programming FPGA.)
• LED_Verilog_bitmap.hex (Bit stream file for programming FPGA.)

Two source codes are provided, one written in VHDL and the other in Verilog. Both of these codes function identi-
cally. This provides you with an option to use either one of the code when programming the Breakout Board. When
the FPGA is programmed with one of these codes, the red LEDs (D2 thru D9) will flash on for ½ second and off for
½ second.

Figure 3 shows the block diagram of the Verilog or VHDL code.

Figure 3. Block Diagram of the Verilog or VHDL Code

LED 2
LED 2
12MHz Clk 16 ½ second pulse 2
÷2 ÷ 96 2 bit counter Decoder LED 3
LED 9

The source code has two counters that are used to divide the 12MHz clock by 216 and 96 generating a approxi-
mately ½ second pulse. This pulse along with the decoder will turn the LEDs (D2 thru D9) on for ½ second and off
for ½ second. The decoder can be modified to have any type of LED sequence by changing either the VHDL or
Verilog code.

When the board is plugged into a USB port, a +5 volt power is applied to the board that will light a green LED
(D11). After the FPGA has been programmed, a green LED (D10) will light. This LED is connected to the CDONE
line of the FPGA.

4
 iCE40HX-8K Breakout Board

Board Power
The iCE40HX-8K evaluation board is powered with the USB cable. LED location D11 indicates that the board is
powered up. All I/Os are driven at 3.3v.

Board I/Os
The I/Os that feed the holes and the 0.1” connector are driven at 3.3v levels. Location J2 is the populated 2 x 20
row connector. Locations J1, J3 and J4 have hole locations that the users can connect to for their specific I/O
requirements.

Programming Options
Two jumpers, J6 and J7 can be set for two types of FPGA Configurations:

• SPI Flash Mode, for programming the serial flash memory.

• SPI Peripheral Mode, for configuring the volatile CRAM in the FPGA.

In SPI Flash Mode the SPI signals, from the FTDI USB interface chip, programs the serial flash memory. After the
memory is programmed the FPGA reads from the memory and configures its self. The advantage of programming
the serial flash is that the FPGA will be re-configured after power-up. Jumpers must be in locations J7:1-2, J6:2-4,
and J6:1-3. See Figure 4

Figure 4. SPI Flash Programming

In SPI Peripheral Mode the SPI signals loads the program file into the CRAM (configuration ram) of the FPGA
directly. In this mode the FPGA will lose its configuration when power is removed and must be re-configured. Jump-

5
 iCE40HX-8K Breakout Board

ers must be in locations J6:1-2 and J6:3-4. Jumper J7 is not installed. See Figure 5

Figure 5. CRAM Programming

LED in location D10 is connected to the CDONE pin of the iCE40HX-8K. This can be monitored to determine that
the iCE40HX-8K is programmed correctly.

Ordering Information
China RoHS Environment-
Description Ordering Part Number Friendly Use Period (EFUP)
ICE40HX-8K Breakout Board ICE40HX8K-B-EVN

6
 iCE40HX-8K Breakout Board

Technical Support Assistance

Submit a technical support case through www.latticesemi.com/techsupport.

Revision History
Date Version Change Summary
January 2016 1.1 Updated Technical Support AssistanceDemonstration Design section.
Changed “demonstration design” to “design file”.
Updated Technical Support AssistanceTechnical Support Assistance
section.
November 2013 1.0 Initial release.

© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

7
 5 4 3 2 1

D D
Figure 6. Block Diagram

HEADER
I/Os
LEDS(1-8)

BANK 0

I/Os

HEADER
C C
I/Os
FPGA
Appendix A. Schematic Diagrams

iCE40HX8K-CT256

BANK 3
HEADER

BANK 1

USB USB to RS232

SPI / RS232 Power from USB 5V
CONNECTOR

8
BANK 2

I/Os

B
HEADER SPI B

A A

AXELSYS
Title
iCE40-HX8K Breakout Board - Block Diagram
Size Document Number Rev
B ICE40HX8K-B-EVN A

Date: Jul 11, 2013 Sheet 1 of 6

5 4 3 2 1
iCE40HX-8K Breakout Board
 5 4 3 2 1

+3.3V

C1 C2

+3.3V 4.7uF 0.1uF

D D

C3 C4
Figure 7. USB to SPI/RS232

4.7uF 0.1uF

VCC1_8FT +3.3V

+3.3V
VCC1_8FT +3.3V U1
FT2232HL

4
9
12
37
64
20
31
42
56
C5 C6 C7 C8 C9

VPLL
VPHY
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

VCCIO
VCCIO
VCCIO
VCCIO

VCORE
VCORE
VCORE
16 SCK 0 R1 6
ADBUS0 iCE_SCK
50 17 SI 0 R2 6
VREGIN ADBUS1 FLASH_MOSI
18 SO 0 R3 6
C ADBUS2 FLASH_MISO C
49 19
VREGOUT ADBUS3 21 SS 0 R4
ADBUS4 iCE_SS_B 6
22
+3.3V 7 ADBUS5 23 0 R5
5 DM DM ADBUS6 iCE_CDONE 4
5 DP 8 24 0 R6 4
DP ADBUS7 iCE_CREST
C10 C11 R7 2.2K 26
14 ACBUS0 27
+3.3V 10uF 0.1uF RESET# ACBUS1 28
R8 R9 R10 R11 12K ACBUS2 29
6 ACBUS3 30
10K 10K 10K REF ACBUS4 32

9
U2 ACBUS5 33
ACBUS6 34
8 1 FT_EECS 63 ACBUS7
7 VCC CS 2 FT_EECLK 62 EECS 38 0 R12
NU CLK EECLK BDBUS0 RS232_Rx_TTL 3
6 3 FT_EEDATA 61 39 0 R13 3
ORG DI EEDATA BDBUS1 RS232_Tx_TTL
5 4 40 0 R15 RTSn 3
C12 VSS DO BDBUS2 41 0 R16
BDBUS3 CTSn 3
93LC56-SO8 R14 2.2K 2 43 0 R17 DTRn 3
0.1uF OSCI BDBUS4 44 0 R18
BDBUS5 DSRn 3
45 0 R19 3
BDBUS6 DCDn
+3.3V 46
3 BDBUS7
B B
OSCO 48
BCBUS0 52
X1 C13 BCBUS1 53
13 BCBUS2 54
1 4 0.1uF TEST BCBUS3 55
STANDBY# VDD BCBUS4 57
BCBUS5 58
2 3
FTDI High-Speed USB BCBUS6 59
GND OUTPUT BCBUS7
60
12.0000MHZ R20
FT2232H PWREN#
iCE_CLK 4 36
SUSPEND#
0
AGND
GND
GND
GND
GND
GND
GND
GND
GND

1
5

10
11
15
25
35
47
51

A A

AXELSYS
Title
iCE40-HX8K Breakout Board - USB to SPI/RS232
Size Document Number Rev
B ICE40HX8K-B-EVN A

Date: Jul 11, 2013 Sheet 2 of 6

5 4 3 2 1
iCE40HX-8K Breakout Board
 5 4 3 2 1

DNI DNI
VCCIO0
Figure 8. FPGA

+3.3V TP4 TP5 DNI DNI

U3A +3.3V TP8 TP9 VCCIO1
R21 iCE40HX8K-CT256 U3B

1
1
A13 C14 R22 iCE40HX8K-CT256

1
1
A3 VCCIO0_01 PIO0_00 B15 PIO0_01 H10 P16 PIO1_04
VCCIO0_02 PIO0_01 DCDn 2 VCCIO1_01 PIO1_04
1 C14 C17 C18 C15 A8 D13 C15 M13
F8 VCCIO0_03 PIO0_02 B14 PIO0_03 1 C21 C19 C16 C20 H15 VCCIO1_02 PIO1_05 M14
VCCIO0_04 PIO0_03 DSRn 2 VCCIO1_03 PIO1_06
0.1uF 0.1uF 0.1uF 0.1uF C12 N15 L12
PIO0_04 E11 0.1uF 0.1uF 0.1uF 0.1uF VCCIO1_04 PIO1_07 N16 PIO1_08
PIO0_05 C13 PIO1_08 L13
D DNI DNI PIO0_06 A16 PIO0_07 PIO1_09 L14 D
PIO0_07 DTRn 2 PIO1_10
+1.2V TP6 TP7 A15 PIO0_08 CTSn 2 K12
PIO0_08 B13 PIO0_09 PIO1_11 M16 PIO1_12
PIO0_09 RTSn 2 PIO1_12
R23 E10 J10

1
1
E8 PIO0_10 C11 PIO1_13 M15 PIO1_14
E7 PLLVCC0 PIO0_11 D11 PIO1_14 J11
100 C22 C23 PLLGND_0 PIO0_12 B12 PIO0_13 R14 PIO1_15 L16 PIO1_16
PIO0_13 RS232_Tx_TTL 2 PIO1_00 PIO1_16
B10 PIO0_14 2 PIO1_01 R15 K13
PIO0_14 RS232_Rx_TTL PIO1_01 PIO1_17
10uF 0.1uF B11 PIO0_15 P14 K14 PIO1_18
PIO0_15 C10 PIO1_03 P15 PIO1_02 PIO1_18 J15 PIO1_19
PIO0_16 A10 PIO0_17 N14 PIO1_03 PIO1_19 K15 PIO1_20
PIO0_17 A11 PIO0_18 TRST_B PIO1_20 K16 PIO1_21
PIO0_18 D10 PIO1_21 J14 PIO1_22
PIO0_19 C9 PIO0_20 R24 PIO1_22 J12
PIO0_20 E9 PIO1_23 J13
PIO0_21 D9 10K PIO1_24 J16
PIO0_22 A9 PIO0_23 PIO1_25 H13
PIO0_23 F9 PIO1_26 H14 PIO1_29
PIO0_24 BANK1 PIO1_29
B9 PIO0_27 G16 PIO1_30
PIO0_27 D8 PIO1_30 H12
BANK0 PIO0_28 PIO1_31
B8 PIO0_29 G15 PIO1_32
PIO0_29 A7 PIO0_30 PIO1_32 G10
PIO0_30 C7 PIO0_31 PIO1_33 F16 PIO1_34
PIO0_31 B7 PIO0_32 PIO1_34 G11
C PIO0_32 PIO1_35 C
B6 PIO0_33 F15 PIO1_36
PIO0_33 C6 PIO0_34 PIO1_36 G14 PIO1_37
PIO0_34 D7 PIO1_37 E16 PIO1_38
PIO0_35 A6 PIO0_36 PIO1_38 G13
PIO0_36 D6 PIO1_39 D16 PIO1_40
PIO0_37 A5 PIO0_38 PIO1_40 G12
PIO0_38 B5 PIO0_39 PIO1_41 F14 PIO1_42
PIO0_39 LED0 5 PIO1_42
E6 F12
PIO0_40 B4 PIO0_41 PIO1_43 D15 PIO1_44
PIO0_41 LED1 5 PIO1_44
A2 PIO0_42 LED2 5 F11
PIO0_42 D5 PIO1_45 E14 PIO1_46
PIO0_43 A1 PIO0_44 PIO1_46 C16 PIO1_47
PIO0_44 LED3 5 PIO1_47

10
C5 PIO0_45 LED4 5 F13
PIO0_45 C4 PIO0_46 PIO1_48 B16 PIO1_49
PIO0_46 LED5 5 PIO1_49
B3 PIO0_47 LED6 5 GBIN2/PIO1_28 H16 E13
PIO0_47 D4 H11 GBIN2/PIO1_28 PIO1_50 D14 PIO1_51
PIO0_48 E5 GBIN3/PIO1_27 PIO1_51
F7 PIO0_49 D3
C8 GBIN0/PIO0_26 PIO0_50 C3 PIO0_51
GBIN1/PIO0_25 PIO0_51 LED7 5

B
VCCIO0 B
VCCIO1 VCC_1.2V
MAKE PWR TRACES
CAPABLE OF 1A MAKE PWR TRACES
C25 CAPABLE OF 1A
J1 C24 C26 C27
0.1uF J2
0.1uF 0.1uF 0.1uF
2 1 PIO0_07
PIO0_01 4 3 PIO0_08 2 1
PIO0_03 6 5 PIO0_09 PIO1_01 4 3
8 7 PIO1_03 6 5 PIO1_04
PIO0_15 10 9 PIO0_13 8 7
PIO0_14 12 11 PIO0_18 PIO1_14 10 9 PIO1_08
PIO0_20 14 13 PIO0_17 PIO1_16 12 11 PIO1_12
16 15 PIO1_21 14 13 PIO1_20
PIO0_27 18 17 PIO0_23 16 15
PIO0_30 20 19 PIO0_29 PIO1_22 18 17 PIO1_18
PIO0_31 22 21 PIO0_32 PIO1_42 20 19 PIO1_37
24 23 PIO1_29 22 21 PIO1_19
PIO0_34 26 25 PIO0_36 24 23
PIO0_45 28 27 PIO0_33 PIO1_32 26 25 GBIN2/PIO1_28
PIO0_46 30 29 PIO0_38 PIO1_36 28 27 PIO1_30
32 31 PIO1_46 30 29 PIO1_34
A PIO0_51 34 33 PIO0_39 32 31 A
PIO0_47 36 35 PIO0_41 PIO1_44 34 33 PIO1_38
PIO0_44 38 37 PIO0_42 PIO1_51 36 35 PIO1_40
40 39 PIO1_49 38 37 PIO1_47
40 39 AXELSYS
Title

Header2x20
iCE40-HX8K Breakout Board - FPGA
DNI Header2x20 Size Document Number Rev
B ICE40HX8K-B-EVN A

Date: Jul 27, 2013 Sheet 3 of 6

5 4 3 2 1
iCE40HX-8K Breakout Board
 5 4 3 2 1

DNI DNI
Figure 9. FPGA

DNI DNI +3.3V TP14 TP15 VCCIO3

+3.3V TP10 TP11 VCCIO2 U3D
U3C R25 iCE40HX8K-CT256

1
1
R27 iCE40HX8K-CT256 E1 E4

1
1
K8 N6 G6 VCCIO3_01 PIO3_00/DP00A B2 PIO3_01/DP00B
P3 VCCIO2_01 PIO2_00 T1 PIO2_01 1 C29 C30 C31 C28 J6 VCCIO3_02 PIO3_01/DP00B F5
1 C32 C33 C34 C35 R13 VCCIO2_02 PIO2_01 P4 N1 VCCIO3_03 PIO3_02/DP01A B1 PIO3_03/DP01B
R8 VCCIO2_03 PIO2_02 R2 PIO2_03 0.1uF 0.1uF 0.1uF 0.1uF VCCIO3_04 PIO3_03/DP01B C1 PIO3_04/DP02A
0.1uF 0.1uF 0.1uF 0.1uF VCCIO2_04 PIO2_03 N5 PIO3_04/DP02A C2 PIO3_05/DP02B
PIO2_04 T2 PIO2_05 PIO3_05/DP02B F4
D PIO2_05 P5 PIO3_06/DP03A D2 PIO3_07/DP03B D
N8 PIO2_06 R3 PIO2_07 PIO3_07/DP03B G5
DNI DNI L8 PLLGND_2 PIO2_07 R5 PIO2_08 PIO3_08/DP04A D1 PIO3_09/DP04B
+1.2V TP12 TP13 C36 C37 PLLVCC2 PIO2_08 T3 PIO2_09 PIO3_09/DP04B G4
PIO2_09 R4 PIO2_10 PIO3_10/DP05A E3
R26 10uF 0.1uF PIO2_10 M7 PIO3_11/DP05B H5

1
1
PIO2_11 N7 PIO3_12/DP06A E2 PIO3_13/DP06B
PIO2_12 P6 PIO3_13/DP06B G3
100 PIO2_13 M8 PIO3_14/DP07A F3
PIO2_14 T5 PIO2_15 PIO3_15/DP07B H3
PIO2_15 R6 PIO2_16 PIO3_16/DP08A F2 PIO3_17/DP08B
PIO2_16 P8 PIO2_17 PIO3_17/DP08B H6
PIO2_17 T6 PIO2_18 PIO3_18/DP09A F1 PIO3_19/DP09B
PIO2_18 L9 PIO3_19/DP09B H4
PIO2_19 T7 PIO2_20 PIO3_20/DP10A G2 PIO3_21/DP10B
BANK2 PIO2_20 PIO3_21/DP10B
T8 PIO2_21 J4
PIO2_21 P7 PIO3_22/DP11A H2 PIO3_23/DP11B
PIO2_22 N9 PIO3_23/DP11B
VCCIO2 PIO2_23 T9 PIO2_24 J5
PIO2_24 M9 PIO3_24/DP12A
PIO2_25 P9 PIO2_28 H1 PIO3_27/DP13B
PIO2_28 BANK3 PIO3_27/DP13B
K11 R10 PIO2_29
R28 PIO2_45/CBSEL1 P13 PIO2_44/CBSEL0 PIO2_29 L10 J2 PIO3_28/DP14A
PIO2_45/CBSEL1 PIO2_30 P10 PIO2_31 PIO3_28/DP14A J1 PIO3_29/DP14B
C PIO2_31 PIO3_29/DP14B C
649 N10 PIO2_32 K1 PIO3_30/DP15A
PIO2_32 T10 PIO2_33 PIO3_30/DP15A K3 PIO3_31/DP15B
M10 PIO2_33 T11 PIO2_34 PIO3_31/DP15B L4
2 iCE_CDONE CDONE PIO2_34 PIO3_32/DP16A
N11 T15 PIO2_35 L1 PIO3_33/DP16B

1
2 iCE_CREST CRESET_B PIO2_35 PIO3_33/DP16B
T14 PIO2_36 K4
D10 DNI PIO2_36 M11 PIO2_37 PIO3_34/DP17A M1 PIO3_35/DP17B
Green TP16 PIO2_37 T13 PIO2_38 PIO3_35/DP17B L6
+3.3V PIO2_38 N12 PIO2_39 PIO3_36/DP18A L3 PIO3_37/DP18B
R29 10K PIO2_39 L11 PIO3_37/DP18B K5

1
PIO2_40 T16 PIO2_41 PIO3_38/DP19A M2 PIO3_39/DP19B

2
K9 PIO2_41 M12 PIO3_39/DP19B L7
GBIN5/PIO2_26 R9 GBIN4/PIO2_27 PIO2_42 R16 PIO2_43 PIO3_40/DP20A N2 PIO3_41/DP20B
GBIN5/PIO2_26 PIO2_43 PIO3_41/DP20B

11
M6
PIO3_42/DP21A M3
PIO3_43/DP21B L5
PIO3_44/DP22A N3 PIO3_45/DP22B
PIO3_45/DP22B P1 PIO3_46/DP23A
PIO3_46/DP23A M4
PIO3_47/DP23B P2 PIO3_48/DP24A
PIO3_48/DP24A M5
VCCIO2 GBIN7/PIO3_25/DP12B G1 PIO3_49/DP24B R1 PIO3_50/DP25A
MAKE PWR TRACES GBIN6/PIO3_26/DP13A J3 GBIN7/PIO3_25/DP12B PIO3_50/DP25A N4
2 iCE_CLK GBIN6/PIO3_26/DP13A PIO3_51/DP25B
CAPABLE OF 1A
B B
C38
J3 VCCIO3 VCC_3.3V
0.1uF
MAKE PWR TRACES
2 1 PIO2_43 CAPABLE OF 1A
PIO2_41 4 3 PIO2_35 C39 C40 C41
PIO2_36 6 5 PIO2_38 J4
8 7 0.1uF 0.1uF 0.1uF
PIO2_45/CBSEL1 10 9 PIO2_39
PIO2_37 12 11 PIO2_32 2 1
PIO2_31 14 13 PIO2_34 PIO3_50/DP25A 4 3
16 15 PIO3_48/DP24A 6 5 PIO3_46/DP23A
PIO2_29 18 17 PIO2_33 8 7
PIO2_28 20 19 PIO2_17 PIO3_41/DP20B 10 9 PIO3_45/DP22B
GBIN5/PIO2_26 22 21 PIO2_24 PIO3_35/DP17B 12 11 PIO3_39/DP19B
24 23 PIO3_33/DP16B 14 13 PIO3_37/DP18B
PIO2_21 26 25 PIO2_20 16 15
PIO2_16 28 27 PIO2_18 PIO3_30/DP15A 18 17 PIO3_31/DP15B
PIO2_08 30 29 PIO2_15 PIO3_29/DP14B 20 19 PIO3_28/DP14A
32 31 GBIN6/PIO3_26/DP13A 22 21 PIO3_23/DP11B
PIO2_10 34 33 PIO2_07 24 23
PIO2_09 36 35 PIO2_03 PIO3_27/DP13B 26 25 PIO3_21/DP10B
PIO2_05 38 37 PIO2_01 GBIN7/PIO3_25/DP12B 28 27 PIO3_17/DP08B
A 40 39 PIO3_19/DP09B 30 29 PIO3_13/DP06B A
32 31
PIO3_07/DP03B 34 33 PIO3_09/DP04B
PIO3_05/DP02B 36 35 PIO3_04/DP02A
Header2x20 PIO3_01/DP00B 38 37 PIO3_03/DP01B AXELSYS
DNI 40 39 Title
iCE40-HX8K Breakout Board - FPGA
Size Document Number Rev
Header2x20 B ICE40HX8K-B-EVN A
DNI
Date: Jul 26, 2013 Sheet 4 of 6
5 4 3 2 1
iCE40HX-8K Breakout Board
 5 4 3 2 1

+1.2V

+3.3V

C42 C43 C44 C45 C46 C47 C48

10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF

D C49 C50 C51 C52 D

10uF 1uF 0.1uF 0.01uF

Figure 10. Power and LEDs

VBUS_5V U4 +3.31V VCC_3.3V +3.3V

R31 L1
18 3
17 IN1_1 OUT1_1
14 IN1_2 4 C55 0.1 600 Ohm 500 mA
13 IN2_1 OUT1_2 R32 C53 R33 C56 C57
IN2_2 0.01uF
C54 R34 R35 20 2 357K 10uF 100 22uF 0.1uF DNI DNI DNI
SHDN1 BYP1 R36 210K
10uF 1M 1M 11 1 TP1 TP2 TP3
SHDN2 ADJ1
C +1.22V VCC_1.2V +1.2V +3.3V +1.2V C
1
1
1

19 R37 L2 R38
PWRGD1 7
12 OUT2_1
PWRGD2 8 C59 0.1 600 Ohm 500 mA 1
OUT2_2 C58 R39 C60
0.01uF
21 9 4.7uF 100 22uF
THERMPAD BYP2
10
ADJ2
LEDs

12
GND1
GND2
GND3
GND4
3 LED0

5
6

16
15
LT3030EFE#TRPBF 3 LED1

3 LED2

3 LED3

3 LED4
VBUS_5V
B 3 LED5 B
R53
3 LED6

1
1K 3 LED7
D11 U3F +3.3V
C61 Green iCE40HX8K-CT256
L3 A12 D12 D1 R40 R41 R42 R43 R44 R45 R46 R47
0.1uF A4 GND_01 VPP_FAST E12 2 1
600 Ohm 500 mA E15 GND_02 VPP_2V5 1K 1K 1K 1K 1K 1K 1K 1K

2
G7 GND_03 CDBU0520
G8 GND_04
G9 GND_05
H7 GND_06
1
1
1
1
1
1
1
1

H8 GND_07
H9 GND_08 POWER D2 D3 D4 D5 D6 D7 D8 D9
J7 GND_09 +1.2V
J5 GND_10 Red Red Red Red Red Red Red Red
J8
1 J9 GND_11
VCC 2 K2 GND_12 A14
2
2
2
2
2
2
2
2

D- DM 2 GND_13 VCC_01
3 DP 2 K7 F10
D+ 4 R48 0 L15 GND_14 VCC_02 F6
ID 5 R7 GND_15 VCC_03 K10
GND C62 0.1uF T12 GND_16 VCC_04 K6
A T4 GND_17 VCC_05 L2 A
SKT_MINIUSB_B_RA GND_18 VCC_06

AXELSYS
Title
iCE40-HX8K Breakout Board - Power, LEDs
Size Document Number Rev
B ICE40HX8K-B-EVN A

Date: Jul 26, 2013 Sheet 5 of 6

5 4 3 2 1
iCE40HX-8K Breakout Board
 5 4 3 2 1
Figure 11. SPI

+3.3V
D D

R49

U3E 10K
iCE40HX8K-CT256
N13 P12 iCE_MISO
SPI_VCC PIOS_00/SPI_SO P11 iCE_MOSI
C63 PIOS_01/SPI_SI R11
PIOS_02/SPI_SCK R12
SPI PIOS_03/SPI_SS_B
0.1uF
C64

0.1uF

R50 R51 R52

10K 10K 10K

U5

8
FLASH_MOSI 5 2 FLASH_MISO

VCC
C SDI SDO C

2 iCE_SCK 6
SCK
J7 3
WP

2 iCE_SS_B 1 2 1 7
CS HOLD

GND
4
N25Q032A13ESC40F
Short-circuit Jumper

13
JU1 JU2 JU3

J7: Remove shunt only for Programming iCE.

Replace shunt for programming Flash and for normal operation.
63429-202LF 63429-202LF 63429-202LF

B B

J6

2 FLASH_MOSI 3 1 iCE_MISO

iCE_MOSI 4 2 FLASH_MISO 2

For programming Flash - Shunt 1,3 and 2,4 (default)

For programming iCE - Shunt 3,4 and 1,2

A A

AXELSYS
Title
iCE40-HX8K Breakout Board - SPI
Size Document Number Rev
B ICE40HX8K-B-EVN A

Date: Jul 26, 2013 Sheet 6 of 6

5 4 3 2 1
iCE40HX-8K Breakout Board