32-Bit

Microprocessor
Printed in Canada
Student Manual
90876-00 |3090876000000b~

A
 FIRST EDITION

Fourth Printing, January 2007

Copyright 1996 Lab-Volt Systems, Inc.

Copyright 1995 Buck Engineering Co., Inc.

All rights reserved. No part of this publication may be reproduced, stored in a

retrieval system, or transmitted, in any form or by any means (electronic,
mechanical, photocopy, recording, or otherwise), without prior written
permission from Lab-Volt Systems, Inc.

Printed in the United States of America

ISBN 086657-079-9
Trainer Familiarization
A microprocessor, or Central Processing Unit (CPU), is a digital integrated
circuit (IC) that can perform arithmetic and logic functions and transfer
information to and from external devices. The block diagram in Figure 1-1
shows a typical microprocessor system.

MICROPROCESSOR

MEMORY INPUT OUTPUT

ADDRESS BUS

Figure 1-1

The support devices that are usually found in a microprocessor circuit

include other digital ICs for memory and Input/Output (110) functions.
Memory ICs are storage devices that contain information in binary form.
Some of this information is in the form of programs, or sets of instructions
for the CPU to execute.
The CPU also uses part of the memory to store system information and
calculation results.
I/0 devices allow the CPU to communicate with the outside world. The CPU
in a personal computer uses an input device to read your commands from
the keyboard, and an output device to send text and graphics information to
the screen for you to view.
Other system components that can communicate with the CPU in your
computer via I/O devices include your printer, mouse, and disk drive.
Communication between the CPU and memory and I/0 devices occurs on
groups of connecting lines that are called buses, as seen in Figure 1-2. The
binary information travels back and forth on the data bus.

MICROFRCCESSOR

DATA BUS

Figure 1-2
The CPU uses the address bus to pinpoint the exact location to which or
from which the data is transferred.
The size of the buses (number of connecting lines) is a measure of the
CPU's processing power.
The first microprocessors had a 4-bit data bus (see Figure 1-3). In an output
operation, for example, a 4-bit CPU could only send a number in the range
0-15 2 4 ) in one operation. The CPU could send a larger number by making
several successive transfers.

Figure 1-3

Succeeding microprocessor generations had expanded buses, and there-

fore, expanded processing power. The 8-bit CPU could send a number as
high as 256 (28) in one operation, and the 16-bit version could send a
number as high as 65,536 (216).

The 80386 microprocessor on your circuit board is a 32-bit device. The

largest number it can send is 4,294,967,296 (232).

The 80386 is also more powerful in other ways than its predecessors. Its
32-bit address bus can directly access up to 4,294,967,296 external memory
locations.
The 80386 has an expanded number of registers. Registers are internal
memory locations for storage of system status information.
For faster operation, the CPU has an internal 32-bit data bus and the ability
to process an instruction while simultaneously fetching the next instruction.
In addition to the 80386 CPU, your circuit board includes two types of
memory devices, input circuitry and output circuitry, and an applications
area that you can use to demonstrate how microprocessors interface with
the outside world.
Figure 1-4 shows how you can communicate directly with the CPU on your
circuit board. There is a keypad, an alphanumeric LCD display, and a group
of LEDs that display the binary information on the data and address buses.

1-3
 EXERCISE

PROCEDURE B - APPLYING POWER TO THE CIRCUIT BOARD

1-1
In this PROCEDURE section, you will turn on power to the circuit board and
recognize conditions that indicate correct operation.
3. Turn on the SINGLE CYCLE switch. Set the address and data LED
selector switches to LOW.

4. Turn on the PWR switch. a. Other than the PWR LED, what
indication(s) tells you that power is applied to the board?

5. Turn the SINGLE CYCLE switch off and press RESET. The startup
message now appears in the LCD display.
What message appears in the LCD display?

6. Rotate the INTENSITY control from one extreme to the other as you
view the range of adjustment on the display.

7. Adjust the intensity to your preference. You may need to alter this
setting if your viewing angle or the ambient light level changes.

PROCEDURE C - OBSERVING SIGNALS ON THE OSCILLOSCOPE

In this PROCEDURE section, you will observe signal waveforms on the
oscilloscope by connecting probes to the TEST STRIP circuit blocks.
8. Connect oscilloscope CH1 to a pin on the TEST STRIP as shown in
Figure 1-29.

TEST
STRIP

Figure 1-29
 Introduction to the Circuit Board
9. Ground the scope probe to the GND terminal in the TEST STRIP
circuit block. Scope probe ground leads are not shown for the
remainder of this lesson, but you should routinely ground all probes
that you connect to the circuit.

10. Connect a patch lead from the pin next to the scope connection to
BS16# on header JP3. In which circuit block is JP3 located?

11. Turn on the PWR switch and turn off the SINGLE CYCLE switch.
Momentarily press the RESET switch.

12. On the oscilloscope, set CHI for 5 V/DIV, dc coupled. Set the sweep
for 2 μs/DIV and trigger on the positive edge of CHI.

13. Adjust the scope for the top waveform (BSI 6#) in Figure 1-30.

Figure 1-30

14. Set the vertical mode to CHOP. Connect CH2 to another TEST
STRIP pin as shown in Figure 1-31. Connect one end of a second
patch lead to the pin next to the CH2 connection.

Figure 1-31

1-24
 EXERCISE
1-2
You can press the HALT switch on the circuit board at any time to interrupt a
program (see Figure 1-55).

INTENSITY

RESET

HALT STEP
SINGLE CYCLE
Figure 1-55

NOTE: Remember a capitalized word enclosed within the symbols "< >" 
refers to a key on the keypad. Therefore, "<STEP>" refers to the STEP key
on the keypad.

When you halt a program, the address at which the CPU stops appears in
the display, and the CPU returns to the function mode.

PROCEDURE A - LOADING DATA WITH THE KEYPAD

In this PROCEDURE section, you will enter bytes of information into memory
by using the WRT, AUTO, FWD, BACK, FFWD, and FBACK keys. You will
verify your results by reading the LCD display.
You can demonstrate some of the circuit board's memory mode functions by
entering, reading back, and changing data in memory.
1. Turn off the SINGLE CYCLE switch and press RESET to view the
startup message.

2. Press <READ>. What message appears in the LCD display?

 EXERCISE

7. Is the AUTO or WRT key more efficient to use if you need to enter a
long program?

8. Press <FBACK> once. The address decrements eight times to

04000. You can now see the eight data bytes you entered.

9. Press cFBACK> again. The address decrements eight more times to

03FF8, and different data is displayed.

10. Press <FFWD> once. The address increments eight times to 04000.

11. Press <FWD> several times to move the cursor to data byte 88.

12. Press <WRT> and enter "FF". You have demonstrated how you can
change a single byte anywhere in the field by scrolling to it with the
FWD key (you can also use BACK) and using the WRT function.

PROCEDURE B - READING A PROGRAM

In this PROCEDURE section, you will use the keypad and display to
examine a simple program stored in memory. You will verify your results by
comparing the display information to a program listing.
The monitor ROM contains several utility programs for testing parts of the
circuitry and for demonstrating various functions. By examining the way such
a program is written, you will find it easier to follow the keypad operations.
Figure 1-59 is a listing for a stored program that transfers information
between memory and the CPU's internal registers. It is not necessary to
completely understand the program at this point, but you can relate the
program listing to the display information that you will see.
ADDR. CONTENTS MNEMONIC REMARKS
FFCOO 88 00 00 mov ax,0 Set data segment
FFC03 8E D8 mov ds, ax to
FFC05 Load initial test data
FFCOB 66 A3 00 50 mov Write eax to 5000H
FFCOF 66 F7 DO not eax Complement eax
FFCI 2 66 A3 04 50 mov ds: Write eax to 5004H
FFCI 6 6688 mov Read location 5000H
FFCI B 66 04 50 mov Read location 5004H
FFC20 EB Jump back to
FFCOBH

Figure 1-59
The first column of the listing shows the address of the first byte of an in-
struction. The instruction appears in the CONTENTS column and can consist
of 1 to 14 bytes.
In the first line of this program, the three instruction bytes are B8 (address
FFCOO), 00 (address FFC0I), and 00 (address FFC02).

1-41
Operating the Circuit Board
13. What instruction byte is located at address FFC14?

The third column is MNEMONIC. A mnemonic is an abbreviated form

of the instruction that is written in a way that makes it easy to recall
the function.

For example, the first mnemonic (mov ax,O) means "Move the
number 0 into the CPU register ax."

14. What instruction code has the mnemonic, "mov ebx ds:[5004H]"?

The REMARKS column contains notes that the programmer makes

to relate the instruction codes and mnemonics to the actual
operation being performed by the program. This form of program
listing is called assembly language.

15. Make sure the SINGLE CYCLE switch is off and press RESET.
Press <READ> and enter the starting logical address "FFCO 0000".
The display shows the physical address FFCOO and the first eight
instruction bytes.

16. What key can you press to view the next eight bytes?

17. Press <FFWD> several more times and compare the display bytes to
those in the program listing.

PROCEDURE C USING THE SINGLE INSTRUCTION CYCLE MODE

In this PROCEDURE section, you will run the program in the single
instruction cycle mode. You will verify your results by comparing the display
information to the program listing.
18. Press <GO> and enter the starting address "FFCO 0000" to run the
program.

19. Press the HALT switch on the circuit board. Press <STEP> several
times until the address in the display is FFCOB.
 EXERCISE
1-2
Refer again to the program listing in Figure 1-59. Because of the
jump instruction at the last line, the instructions from lines FFCOB
through FFC20 form a loop. The first three instructions (lines FFCOO
through FFC05) are executed once, and then the CPU remains in the
loop until the CPU is interrupted or reset.

20. You have stepped to address FFCOB in the single instruction mode.
What address will be displayed if you press the <STEP> key once?

21. Press <STEP> several times and compare the display information to
the program listing. Each time you press <STEP>, the display shows
the next instruction and the address of the first byte in that
instruction.

PROCEDURE D S T E P P I N G THROUGH THE INITIAL INSTRUCTIONS

In this PROCEDURE section, you will use the register mode to direct the
CPU to the initial program instructions.
When you ran the program in Figure 1-59 in the previous PROCEDURE
section, the CPU executed the first three instructions once, then remained in
a loop (lines FFCOB through FFC20) until you used the HALT switch.
By setting certain registers, you can also step through the first three
instructions, which are outside the loop.
The contents of the CS (code segment) and IP (instruction pointer) registers
contain the address of the next instruction that the CPU will execute. The
current CS-IP register contents are shown in Figure 1-60.

Figure 1-60
22. The CS-IP register pair forms a logical address consisting of a
segment base (CS) and an offset (PP). What is the physical address
for the register contents shown?

In the course of stepping through a program, you can change the

contents of the CS-IP register pair to force the CPU to any desired
address.

23. Press <STEP> until the address FFCOB appears in the display.

1-43
 EXERCISE

When you exit the register mode, the display shows the last address
that was displayed before you entered the register mode.

29. Press <STEP> once. The address is now FFC03, indicating that the
CPU has executed the instruction at FFCOO and has fetched the next
instruction.

30. Compare the display information to the program listing as you press
<STEP> several more times.

PROCEDURE E - OBSERVING REGISTER TRANSFERS

In this PROCEDURE section, you will observe the changing contents of
some of the registers as you step through a program.
Several of the instructions in the test program of Figure 1-59 involve the
registers EAX and EBX. As you step through the program, you can use the
register mode to observe the changing data in these registers.
31. Press RESET, press <REG>, and select <(CS-IP)>.

32. Use the FWD and WRT keys to set the contents of the CS-IP
register pair to the logical address FFCO:0000 (physical address
FFCOO).

33. Press <EXIT> to cancel the register mode, then press <STEP> to
advance to address FFC05.

When you reset the CPU, part of the initialization program includes
setting the EAX register to 00000000H.

34. You can verify this by checking the register contents. Which register
key should you use to view the contents of EAX?

35. Press <REG> and select (A-B). You can see that the contents of
both EAX and EBX are 00000000H.

36. Press <EXIT> to return to address FFC05. This instruction loads the
data AAAAAAAAH into EAX. Press <STEP> t o execute the
instruction.

37. Press <REG> and then press (A-B). Which register contents have
changed?

38. Press <EXIT> to return to address FFCOB. The instruction at this line
writes the contents of EAX into memory location 5000H. Press
<STEP> to execute the instruction.

1-45
 EXERCISE

REVIEW QUESTIONS
1-2

1. Which key(s) can you use to enter data into memory?

a. WRT
b. AUTO
c. Both of the above.
d. None of the above.

2. Which register pair always contains the address of the next instruction
that the CPU will fetch?

a. A-B
b. C-D
c. SI-DI
d. CS-IP

3. Turn off the SINGLE CYCLE switch and press RESET.

Press <REG> and select <(CS-IP)>. Enter the logical address "FFCO
0000". Press <(EXIT)> to jump to the test program you used in the
PROCEDURE.

Press <STEP> until you reach the complement EAX instruction at

address FFCOF.

Press <REG> and select <(A-B)>. Use the <WRT> key to change the
contents of EAX to "CCCCCCCC".

Press <EXIT> and then press <STEP> to execute the complement

instruction.

Press <REG> and select <(A-B)>. What number does EAX contain?

a. 33333333H
b. CCCCCCCCH
c. OOOOOOOOH
d. FFFFFFFFh

4. Press <RESET> and then press <READ>. Enter the address "FFCO
0000" to view the test program (refer to Figure 1-59). Press <FFWD>
eight times and compare the display information to the program listing.
Operating the Circuit Board
Each time you press the FFWD key eight times, the first byte in the display
(after the address) represents

a. the first byte of the next instruction in the program listing.

b. the contents of the CS-IP registers.
c. the first byte of the next eight bytes in the program listing.
d. None of the above.

5. Which key would not be used to change the contents of a CPU register?

a. REG
b. FWD
c. WRT
d. STEP
 EXERCISE
2-1
PROCEDURE C - RECOGNIZING A WAIT STATE
Refer to Figure 2-20. The CPU samples the RDY# input near the end of
every T2 to determine if an external device has responded. If no response is
detected (RDY# sampled high), the CPU enters a wait state and continues
to look at the RDY# input. When the device responds (RDY# sampled low),
the CPU exits the wait state.

READ CYCLE 1 . CYCLE

WAIT
CYCLE 3

I I I I I I I I I
READY# READY#

Figure 2-20

19. Refer to Figure 2.20, the CPU samples the RDY# line at the end of
every T2. Is the state of RDY# active or inactive during CLK cycle 2?

20. Refer again to Figure 2-19. Since RDY# is inactive during CLK cycle
2, the following cycle is a wait state. At the end of the wait state
(CLK cycle 3), the CPU samples RDY# low, terminates the bus
cycle, and starts a new one (bus cycle 2) by driving ADS# low.

21. You can therefore recognize a wait state such as CLK cycle 3 by the
conditions of ADS# and RDY#. A wait state is characterized by three
conditions:

It follows a T2 state.
ADS# is high.
RDY# is high in the previous CLK cycle.

22. Where is the wait state in bus cycle 2?

23. Which CLK cycle(s) in bus cycle 3 is a wait state?

PROCEDURE D - RECOGNIZING AN IDLE STATE

An idle state occurs when the CPU does not issue a bus request. This
means that the CPU does not drive ADS# low to start a bus cycle. When it is
ready to issue a bus request, the CPU exits the idle state and begins a bus
cycle by driving ADS# low (see Figure 2-21).
32-Bit Bus Transfers
2. Press <READ> on the keypad to view the "READ ADDRESS?"
prompt, and enter the address, "0000:5000".

3. Press <AUTO> to load the program, and carefully enter the data,
"66 C7 06 00 70 FF FF FF" as shown in Figure 2-37.

Figure 2-37

4. You have loaded data into addresses 05000H through 05007H, and
the display now shows the next address field beginning at 05008H.
Complete the loading of the program by again pressing AUTO and
then entering "FF EB F5" as shown in Figure 2-38.

Figure 2-38

5. To verify your data, press RESET, and then press <READ>. Enter
address "0000:5000", and verify that the data is 66 C7 06 00 70 FF
FF FF. Press <FFWD> eight times to view the second field, and
verify that the first line reads FF EB F5. Is all the data correct?

PROCEDURE B - SETTING UP THE OSCILLOSCOPE

A brief explanation of the program will help you to determine how to use the
oscilloscope to your best advantage in this PROCEDURE section. You will
examine programming in more detail in Unit 6. The program below begins at
address 05000H and executes a simple loop. The first line instructs the CPU
to load the 32-bit data FF FF FF FF to memory location 07000H. This is a
data transfer you can observe to determine the actions of the CPU byte
enable outputs.

ADDRESS CONTENTS MNEMONICS

5000 66 C7 06 00 70
FF FF FF FF MOV 7000H, OFFFF
5009 EB F5 JMP $ - 14
 EXERCISE
2-2
The second program line instructs the CPU to jump to the beginning and
repeat the program. The CPU executes the loop continuously until you press
RESET. Since the program contains several bus cycles, you need a way to
isolate the cycles of interest on the oscilloscope. One way to do this is to
use address line A13 as one of your signals. To understand the reasoning
for using A13, you can examine what happens during the transfer. The
program transfers the data from the section of memory beginning with
5000H to the section beginning with 7000H.
Figure 2-39 shows the hexadecimal numbers 5000H and 7000H. The five
and seven are shown with their binary equivalents and the address line
corresponding to each bit. If the microprocessor were to transfer data from
memory area 5000H to memory area 7000H, address bit A13 changes from
Oto 1.

Figure 2-39

If you view A13 on one channel of the oscilloscope, you can use the other
channel to examine the way other signals behave when the transfer occurs.
6. Set CH 1 and CH 2 for 0.5 VIDIV. Set the input coupling for both
channels to DC and vertical mode to ALT.

7. Set the scope to trigger on the positive edge of CH1. Set the trigger
COUPLING to AC, and select 0.2 ps on the TIME/DIV control.

8. Connect the CH 1 (X10) probe to address line A13 on header JP1.

Connect the CH 2 (X10) probe to ADS# on JP3.

9. Press <GO> and enter "0000 5000" to run the program. Adjust the
oscilloscope to view the waveforms in Figure 2-40. Do the falling
edges of ADS# represent the beginning or the end of a bus cycle?

Figure 2-40
32-Bit Bus Transfers

16. The ADS# signal shows that two bus cycles now occur during the
time A13 is high. Does this indicate an aligned or misaligned
transfer?

17. Use a third probe to connect the scope's EXT TRIGGER INPUT to
A13. Set the scope trigger source to EXT.

18. Move the CH 1 probe to BE0#, and move the CH 2 probe to BE1#.

Refer to Figure 2-46. Since you are still triggering on A13, the BE0#
and BE1# signals you see on the scope are referenced to A13.
Although you can see only the byte enables on the scope, A13 and
ADS# are shown here to remind you of the timing relationship. Do
the byte enables (BE0# and BE1#) appear as shown on Figure 2-46?

Figure 2-46

Note: Remember ADS#, BE0#, and BE1# are all active low signals.
19. Which byte enable is active for the first bus cycle?

During the second bus cycle, BE1# becomes active and BE0#
becomes inactive.

20. Move the CH 1 probe to BE2# and CH 2 to BE3#.

A13 and ADS# are shown again in Figure 2-47 for reference. Do the
BE2# and BE3# signals appear as shown on the Figure 2-47?
Read and Write Cycles
PROCEDURE B SETTING UP THE OSCILLOSCOPE

3. Set CH 1 and CH 2 for DC input coupling and 5V/DIV. Select ALT

with the vertical mode control. Set TIME/DIV to 0.5 ps.

4. Set the scope to trigger on the positive edge of CH 1, and set

TRIGGER COUPLING to AUTO.

ADS #

JP3
Figure 2-64

5. Connect the CH 1 (X10) probe to ADS#, and connect the CH 2 (X10)

probe to W/R# as shown in Figure 2-64. Connect the probe ground
leads to ground terminals on the circuit board.

6. Press RESET, then press <GO> on the keypad, and enter "0000
6000".

7. Adjust the TIME VARIABLE control on the scope so that the rising
edge of W/R# aligns with the last vertical graticule line, as shown in
Figure 2-65.

Do your waveforms appear as shown on Figure 2-65?

Figure 2-65

The program has one write command. By adjusting the scope to view
one complete cycle of the W/R# output, you can also view one
complete program loop in the width of the screen.
 EXERCISE
2-3
How many of the bus cycles are write cycles?

8. Move the CH 1 probe to M/IO# and the CH 2 probe to D/C#. Connect

a third probe from the scope's EXT input to W/R#. Set the TRIGGER
SOURCE to EXT.

The ADS# and W/R# signals are shown for timing reference only. Do
the M/IO# and D/C# waveforms appear on your scope as shown in
Figure 2-66?

<ADS#>
ov
W/R# M/IO# D/C# Bus Cycle Type
(W/R#)
ov
high I/O data write
CH 1
memory code read
low high high memory data read
CH 2 high high high memory data write
ov

Figure 2-66

This scope pattern shows three different combinations of levels (A,

B, and C) for the W/R#, M/IO#, and D/C# signals. You can use the
table to determine the type of bus cycle. For example, in section A,
W/R# and D/C# are high and M/IO# is low. This combination is
identified in the table as an I/O data write cycle.

Which section consists of I/O data read cycles?

What cycle type is executed in section B?

 EXERCISE
2-3
You have adjusted the scope to view one complete program loop in
one sweep. The transitions on ADS# represent all the bus cycles in a
program loop. Are most of the bus cycles read or write cycles?

16. Move the CH 1 probe to M/IO# and the CH 2 probe to D/C#. Connect
the EXT probe to W/R#, and set the TRIGGER SOURCE to EXT.

The ADS# and W/R# signals are shown for reference. The M/IO#
and D/C# waveforms should appear on your scope as shown in
Figure 2-69.

Figure 2-69

The steady high level on M/IO# means that all the bus cycles are
what type of cycles?

Three different combinations (A, B, and C) of the W/R#, M/IO#, and

D/C# levels occur in one program loop. According to Figure 2-70
and the table, what type of cycle is in section A?

Figure 2-70
CPU Initialization
During reset, the CPU suspends all bus activity and sets the outputs shown
in Table 2-4 to the levels indicated.
When you reset the CPU in its RUN mode, you may not be able to determine
whether a failure due to a circuit fault occurs during reset, or afterward,
when the CPU is executing instructions. To determine if a failure occurs dur-
ing reset, you can reset the CPU in its SINGLE CYCLE mode. This mode
allows you to examine signals statically and compare their levels to those in
Table 2-4.
Table 2-4

The levels of the status outputs D/C#, W/R#, and M/IO# indicate that an I/O
data read cycle occurs (see Table 2-5).
Table 2-5

W/R# M/IO# D/C# BUS CYCLE TYPE

low low high I/O data read
high low high I/0 data write
low high low memory code read
low high high memory data read
high high high memory data write

To locate a circuit fault that does not show up during reset, you need to
know what the CPU does immediately after a reset.
After each reset, the CPU fetches an instruction from memory address FFFF
FFFOH. The system designer will have placed an instruction at this location
so that the CPU can begin operation. On your circuit board, this instruction
is a jump to an initialization program, as shown in Figure 2-74.

FFFF FFFOH JUMP T O " INITIALIZE

'INITIALIZE" SET UP R E G I S T E R S
SET UP MEMORY
WRITE TO D I S P L A Y
I

Figure 2-74
 erfacing
UNIT OBJECTIVE
At the completion of this unit, you will be able to demonstrate memory trans-
fers and describe the functions of memory control signals.

DISCUSSION OF FUNDAMENTALS
Memory is an important part of any microprocessor system. The instructions
that the CPU executes are stored in memory, as well as numerical informa-
tion such as system data, status information, and results of calculations.

MICROPROCESSOR
(CPU)

D A T A BUS

MEMORY INPUT OUTPUT

ADDRESS BUS

Figure 3-1

Semiconductor memory devices are ICs with a large array of data storage
locations. Two basic types are used in microprocessor systems: RAM
(random-access memory) and ROM (read-only memory). The CPU can write
data into RAM and read data from it as shown in Figure 3-2. For this reason,
RAM is also called read/write memory. Most RAM ICs (including those on
your circuit board) are volatile, which means that when power is removed,
the stored data is lost.

READ

READ

WRITE
RAM

Figure 3-2

You can think of ROM data as being permanently stored. With some types of
ROM, the data is stored during the manufacturing process. Other types are
manufactured with blank data. You can use a special programming instru-
ment to load the data before installing the ROM in your circuit.
The type of ROM used on your circuit board is an EPROM
Programmable ROM). D a t a i s stored i n t h e EPROM by a special
programming instrument before the EPROM is installed in a circuit.

3-1
Memory Control Signals
On the next step, the CPU will fetch FCH and the byte immediately
following it, which is shown in the initialization program as "don't
care" data (XX). When you step again, the CPU will execute the
jump. Whenever the 80386 decodes an instruction, it simultaneously
fetches the next instruction, which could consist of one or several
words. For this reason, you may need to step several times before
reaching the address to which the CPU jumps.

13. Press STEP once to transfer the next two bytes. The circuit board
LEDs should match the pattern shown below.

= DON'T

ADDRESS DATA
A15 D l5 0

14. Press STEP several times until the LOW address LEDs read
C012H as shown below.
NOTE: Refer to the program at the bottom of page 3-14.

ADDRESS DATA
A15

Select the HIGH address LEDs and confirm that they read 000FH.

Which instruction will the CPU execute on the next step?

You can see by the address LEDs that the CPU has executed the
jump to 000F C012H. The data LEDs show that the CPU has fetched
the instruction bytes at that address, which are FAH and FCH.

PROCEDURE D -
OBSERVING THE ROM INTERFACE CONTROL SIGNALS
During the early part of initialization, the CPU fetches a series of instructions
from the monitor ROM (see Figure 3-16). At this time, you can expect to see
activity on the control lines associated with ROM transfers. Pulses on ADS#
and RDY# indicate the execution of bus cycles. Since ROM transfers are
memory code read cycles, W/R# and D/C# are low, and M/lO# is high.
The PLDs generate MROMSEL# to select the ROMs and MRDC# to enable
their outputs. BS16# is active because the transfers involve a 16-bit memory
area.
 EXERCISE

Figure 3-29 shows all the combinations of address bits A15 through A18 that
occur In the RAM block. Remember that A17 and A18 are always 0 in the
RAM block. There are four possible combinations of A15 and A16.
Figure 3-30 shows the entire RAM block (00000H through 1FFFFH). If you
assume that the values of A15 and A16 are 0, you can think of the RAM
chips as residing in the first section (0000H through 7FFFH).

0001 F F F F
RAM
0001 8000
0001 7FFF
RAM
0001 0000
0000 FFFF
RAM

RAM

Figure 3-29 Figure 3-30

When A15 is 1 and A16 is 0, the second section (8000-FFFFH) is selected.

Because the address bus is only partially decoded, the CPU does not
recognize the second section as a separate section but rather as an image
of the first section. This means that data contained at an address in the first
section (for example, 0123H) also appears at the corresponding address in
the second section (81 23H).
Similarly, the other two combinations of A15 and A16 correspond to two
additional image sections. For example, 8ABCH, 18ABCH, 1 0ABCH are all
images of address OABCH, although they appear in different RAM sections.
The number of undecoded address bits (n) determines the number of
sections in a memory block. In the RAM block, the 2 undecoded
address bits (A15 and A1 6) result in 4 sections.
In the ROM blocks, there are three undecoded address lines (A14, A15, and
A16). There are 8 sections in each ROM block (see Figure 3-31).

OPEN 1
UROM 0
MROM 1 1

CHIP
D A7
A6 ---- ADDRESS LINES
G A5 - (RAM: A2 - A14,
1 A4 ---- RUM: A l - A13)

Figure 3-31
 EXERCISE
4-2

CH 2
ADS #

Figure 4-22

7. Move the CH 2 scope lead to A6, and see Figure 4-22(d). What state
must address line A6 be in to generate the PPI_EN# signal?

8. Move the CH 2 scope lead to the M/IO# signal, and refer to Figure
4-22(e). What state of the M/IO# signal is required to generate the
PPI_EN# signal?
Maskable Interrupts
14. Use the logic probe to confirm that the W/R#, D/C#, and M/IO# are
low.

The high and low data are "don't care" levels in line 0 because the
data bus is not valid during the first INTA cycle.

15. Press STEP once to view the second INTA cycle at line 1. Use the
logic probe to confirm that the levels of W/R#, D/C#, and M/IO# are
low. In the second INTA cycle, the CPU reads the vector type
number 2BH on the lower 8 data lines.

16. Press STEP once and write the data and address at line 2 of the table.

Why is the address value ACH?

17. The CPU is fetching the vector address in preparation for a jump to
the service routine. The address is 7003 because you activated the
IR3 input. Write "get address" in the OPERATION column.

18. Press STEP once and write the address and data at line 3.

Line 2 specified a jump to address 7003H. Why is the address

7000H at line 3?

19. Press STEP once and write the address and data in line 4.

20. Repeat step 19 for the remaining lines in the table.

21. In lines 4-6, the CPU is preparing for the jump to the service routine
by pushing FLG, CS, and IP to the stack. Write this information into
the OPERATION column for lines 4, 5, and 6.

22. In lines 7-9, the CPU has executed the service routine, which is
simply a return instruction (CFH). The CPU is preparing for the return
to the main program by popping the FLG, CS, and IP from the stack.
Write this information into the OPERATION column for lines 7, 8, and 9.

23. Press STEP several times as you observe the address LEDs. The
LEDs are again sequencing through the values in the table. Why is
the CPU repeating the service routine?
Memory Addressing Modes I

INSTRUCTION CODE: 07
(MOV A X , [BX])

CPU RAM
ADDRESS CONTENTS

REGISTER VALUE ==
EFFECTIVE ADDRESS =

Figure 6-29

12. Read the AX register. Does it contain the memory operand A3DC?

13. Enter the instruction code 8B 07 at logical address 0200:0050

14. What is the base value used to calculate the EA? Record your
answer in Figure 6-29.
15. What is the EA? Record your answer in Figure 6-29.
16. What is the logical address of the memory operand?

17. Enter the memory operand A3DC at the logical address.

18. Press <STEP> to execute the instruction.
19. Read the AX register. Was the memory operand A3DC moved into
the AX register?
Memory Addressing Modes - I
When the base value is in any register except BP, EBP, or ESP, the default
segment is DS (as shown in Table 6-7). When the base value is BP, EBP, or
ESP, the default segment is SS. If you use a segment override prefix in the
instruction code, alternate segment registers may be used.

Table 6-7

SEGMENT REGISTER SELECTION RULES

OF DEFAULT
MEMORY REFERENCE SEGMENT

INSTRUCTION CODE FETCH S NONE IP

STACK OPERATION SS NONE SP
DATA (WHEN EAX, EBX, ECX, C S , S S , ES, EFFECTIVE
EDX. ESI, OR ADDRESS
FOR
BASE VALUE)
DATA (WHEN OR ESP SS CS. DS. ES. EFFECTIVE
USED FOR BASE ADDRESS
VALUE )
'MEMORY DESTINATION OF THE STOS AND MOVS INSTRUCTIONS (AND
REP STOS AND REP MOVS) USE AS THE BASE REGISTER AND
AS THE SEGMENT. NO OVERRIDE POSSIBLE

The instruction code that you will use (66 8B 91 30 00) is for a 32-bit
operand (see 6-31). The instruction code specifies the contents of the Dl
register as the index value and the contents of the BX register as the
value. In the instruction code, the first byte, 66, is the 32-bit operand size
prefix that must be used when the CPU operates in the real mode.
The 0030 displacement value is in the last two bytes of the instruction code
(30 00). The least significant byte (30) comes first and the most significant
byte (00) comes last.
When executed, the instruction causes the CPU to calculate the EA (304B)
by adding the displacement, base, and index values; determine the memory
operand's physical address (0404B) by adding the EA to the DS's base
address; and move the 32-bit memory operand, 1234ABCD, to the EDX
register.

32. Turn off the SINGLE CYCLE switch, and press RESET. Enter the
values shown in Figure 6-31 in the IP, CS, DS, BX, and Dl registers.
NOTE: The BX and Dl registers are the 2 least significant bytes of
the EBX and EDI registers, respectively.
33. Read the EDX register. Does it contain the memory operand
1234ABCD?

34. Enter the instruction code 66 8B 91 30 00 at logical address

0200:1000.
Memory Addressing Modes - II

7. Press <STEP> to execute the instruction. Read the AX register.

Was the memory operand ABCD moved into the AX register?

8. The instruction used what type of memory operand addressing

mode?

PROCEDURE B - SCALED INDEX MEMORY ADDRESSING MODE

In this PROCEDURE section, you will use the scaled index memory
addressing mode to move 16-bit data from a 32-bit memory location to the
AX general-purpose register.
In the scaled index memory addressing mode, the operand's effective
address (EA) equals the index value times a scale factor, with the result
added to the displacement value.
EA = (index value * scale factor) + displacement value
Instruction code: 67 8B 04 75 20 10 00 00
Mnemonic: MOV AX,[(ESI*2)+00001020H]
The instruction code's displacement field contains the displacement value 20
10 00 00.
For 32-bit addressing, the index value may be in any 32-bit general-purpose
register except ESP.
The scale factor for the index value may be 1, 2, 4, or 8.
In the scaled index addressing mode, DS is the default segment.
If you use a segment override prefix in the instruction code, alternate
segment registers may be used.
When executed, the instruction causes the CPU to calculate the EA
(0000102E) by adding the displacement and index * scale values; determine
the memory operand's address (0000502E) by adding the EA to the DS's
base address; and move the 16-bit memory operand, 6789, to the AX
register.
9. Turn off the SINGLE CYCLE switch, and press RESET. Enter the
values shown in Figure 6-40 in the IP, CS, DS, and ESI registers.
10. To be sure that the AX register does not contain the operand, enter
"0000" in the AX register.
 UNIT TEST

1. What determines the physical address of the next instruction for the
80386 CPU?
a. the data segment's base address and the EA
b. the code segment's base address and the offset in the EIP register
c. the addressing mode specified in the instruction code
d. the data in the EFLAGS register

2. What is the function of the six segment registers?

a. They contain data that specifies the six active segments in memory.
b. They contain the next six instruction codes.
c. They contain the results of arithmetic and logical operations.
d. The segment registers control operations and indicate the status of
the 80386 CPU.

3. Where can an operand be located?

a. in an instruction
b. in memory
c. in a general-purpose register
d. All of the above.

4. What is the purpose of the 80386 CPU addressing modes?

a. They specify the op code field of the instruction.
b. They determine the address size of the segments.
c. They specify the destination of the operand.
d. They locate an operand.

5. When the 80386 CPU operates in the real mode, what can the address
size be?
a. 8 bits or 16 bits
b. 16 bits
c. 32 bits
d. 16 bits or 32 bits

6. The instruction code MOV BX,CX uses what type of addressing mode?
a. direct
b. register
c. based
d. index

7. Which instruction code uses the based addressing mode?

a. MOV BX,[SI + BOH]
b. MOV AX,[BP + 2000H]
c. MOV AX,[ESI*2 + 00001 020H]
d. MOV EBX,BC47AA52
 EXERCISE

9. Determine the mod bits from Figure 7-24 and write them in Table 7-7.
MODE (mod) FIELD CODES

mod DESCRIPTION
00 MEMORY MODE: NO DISPLACEMENT FOLLOWS
01 MEMORY MODE: 8-BIT DISPLACEMENT
10 MEMORY MODE: 16- OR 32- BIT DISPLACEMENT
REGISTER MODE

NOTE: WHEN r/m EQUALS 110. THERE IS A

1 6-BIT DISPLACEMENT.
Figure 7-24
10. Determine the reg bits from Figure 7-25 and write them in Table 7-7.

REGISTERS SPECIFIED BY REG (reg) FIELD

16- OR 32- BIT 16- BIT DATA 32- BIT DATA

DATAOPERATION OPERATION OPERATION
reg
w = l w = l
ornowfield
000 AL AX
00 1 CL CX ECX
0 10 DL EDX
01 1 EBX
100 AH SP ESP
101 CH BP
ESI
11 1 BH I

Figure 7-25
11. You now have the binary value for the first nibble of the second byte.
Write the hex value below the binary value in Table 7-7.

12. Determine the r/m bit from Figure 7-26 and write it in Table 7-7.

16- BIT ADDRESSING

EFFECTIVE ADDRESSES SPECIFIED BY r / m AND mod FIELDS
r/m = -
000 + [Bx + [BX + SI
001
010

100 + [SI +
d8] +
110 6 + d1
111 [Bx + + d16]

Figure 7-26

13. You now have the binary value for the second nibble of the second
byte. Write the hex value below the binary value in Table 7-7.
Instruction Formats - II
14. What is the hex displacement value in the instruction MOV CX,[BX +
SI + 0060H]?

15. For the displacement 0060H, what hex code follows the first two
bytes 8B 88?

16. What is the complete instruction code for the mnemonic MOV
CX,[BX + SI + 0060H]?

17. To test the instruction code for the mnemonic MOV CX,[BX + SI +
0060H], do the following on the 32-BIT MICROPROCESSOR circuit
board.

1. Turn the SINGLE CYCLE switch to OFF and press RESET.

2. Enter "0200" in the CS register.
3. Enter "1000" in the IP register.
4. Enter "01 00" in the DS register.
5. Enter a base value "3000" in the BX register.
6. Enter an index value "0004" in the SI register.

With a base value of 3000, an index value of 0004, and a displace-

ment of 0060, what is the EA?

18. Continue by entering the memory operand and instruction code.

1. Press <EXIT> and then press <READ>.

2. Enter the logical address "0100 3064" for the memory operand.
3. Starting at address 04064, enter "88 77" for the operand, which is
7788.
4. Press <READ> and enter the logical address "0200 1000" for the
instruction code.
5. Starting at address 03000, enter the instruction code " 8 B88 60 00".
6. Press <STEP> to execute the instruction code.
 EXERCISE

29. You now have the binary value for the second nibble of the second
byte. Write the hex value below the binary value in Table 7-8.

30. Determine the mod bits from Figure 7-28 and write it in Table 7-8.
MODE (mod) FIELD CODES

mod DESCRIPTION
00 MEMORY MODE: NO DISPLACEMENT FOLLOWS *
01 MEMORY MODE: 8-BIT DISPLACEMENT
10 MEMORY MODE: 16- OR 32-BIT DISPLACEMENT
11 REGISTER MODE

* NOTE: WHEN r/m EQUALS 110. THERE IS A

16-BIT DISPLACEMENT.
Figure 7-28
Determine the reg bits from Figure 7-29 and write it in Table 7-8.
REGISTERS SPECIFIED BY REG (reg) FIELD

16- OR 32- BIT 16-BIT DATA 32-BIT DATA

DATA OPERATION OPERATION OPERATION
w = l w = l
w = O
or no w field or no w field
AL AX EAX
CL CX ECX
DL DX EDX
BL BX EBX
AH SP ESP
CH BP EBP
DH SI ESI
BH Dl EDI
Figure 7-29
32. You now have the binary value for the first nibble of the third byte.
Write the hex value below the binary value in Table 7-8.

33. Determine the r/m bits from Figure 7-30 and write it in Table 7-8.
32- BIT ADDRESSING
EFFECTIVE ADDRESSES SPECIFIED BY r / m AND mod FIELDS

Figure 7-30

34. You now have the binary value for the second nibble of the third
byte. Write the hex value below the binary value in Table 7-8.
Instruction Formats - II
35. The scaled index (EDI*2)is given in the mnemonic. Determine the ss
bits from Figure 7-31 and write them in Table 7-8.
SS FIELD IN S-I-B BYTE

ss SCALE FACTOR
00 1
01 2
10 4
11 8

Figure 7-31

36. Determine the index bits from Figure 7-32 and write them in Table 7-8.
INDEX (index) FIELD IN S-1-B BYTE
SPECIFIED BY INDEX REGISTER
index INDEX REGISTER
000 EAX
001 ECX
010 EDX
01 1 EBX
100 NO INDEX REG *
101 EBP
110 ESI
111 EDI

*NOTE: WHEN T H E I NDEX FIELD I S 100.

THEN THE SS FIELD MUST EQUAL 00.
Figure 7-32

Determine the base bits from Figure 7-33 and write them in Table 7-8.
BASE (base) FIELD IN S-1-B BYTE SPECIFIED BY EFFECTIVE ADDRESS

base mod = 01 mod = 10

000 + + d8] [E AX + (S*l) +

001 + [ECX + [ECX + +
010 [EDX + [EDX + + d8] [EDX + +
01 1 + + + [EBX + +
100 + [ESP + + d8] [ESP +
101 + [EBP + + [EBP +
110 + + + d8] + +
11 1 + + + +
NOTE: S*l EQUALS THE SCALING FACTOR TIMES THE INDEX VALUE.

Figure 7-33

38. You now have the binary value for the last instruction byte. Write the
hex value below the binary value in Table 7-8.

39. What is the complete instruction code for the mnemonic MOV [ECX
+ (ED l*2)],BX?
 EXERCISE
7-
For the instruction MOV EBX,[ECX + (EDI*4) + 0520F8AB], what are the
r/m field bits?

32- BIT ADDRESSING

EFFECTIVE ADDRESSES SPECIFIED BY r/m AND mod FIELDS

r /m mod = 00 mod = 01 _____mod = 10

000 [ EAX] [ E AX + d8] [ E AX + d32]

00 1 [E C X ] [ECX + d8] [ECX + d32]
01 0 [EDX] [EDX + d8] [EDX + d32]
01 1 [EBX] [EBX + d8] [EBX + d32]
100 s- i- b present s- i- b present s- i- b present
101 d32 [EBP + dB] [EBP + d32]
110 [E S I ] [ESI + dB] [ESI + d32]
11 1 [ EDI] [E DI + d8] [EDI + d32]

Figure 7-36

For the instruction MOV EBX,[ECX + (EDI*4) + 0520F8AB], what are the
index field bits?

INDEX (index) FIELD IN S-1-B BYTE

SPECIFIED BY INDCX REGISTER
index INDEX REGISTER
000 EAX
001 ECX
010 EDX
01 1 EBX
100 NO INDEX REG *
101 EBP
110 ESI
111 ED1

*NOTE: WHEN T H E I N DE X F I E L D I S 100.

THEN THE SS FIELD MUST EQUAL 00.
Figure 7-37
Instruction Formats - II
BASE (base) FIELD IN 5-1-0 BYTE SPECIFIED BY EFFECTIVE ADDRESS

base m o d = 00 m o d = 01 m o d = 10

000 [EAX + (S*I)] [EAX + (S*l) + dB] [E AX + (S*l) + d32]

001 [ECX + (S*I)] [ECX + (S*I) + dB] [ECX + (S*l) + d32]
010 [EDx + (S*I)] [EDX + (S*I) + d8] [EDX + (S*I) + d32]
011 [EBx + (S*l)] [EBX + (S*I) + d8] [EBX + (S*I) + d32]
100 [ESP + (S*l)] [ESP + (S*I) + d8] [ESP + (S*I) + d32]
101 [d32 + (S*I)] [EBP + (S*I) + d8] [EBP + (S*I) t d32]
110 [ESl + (S*I)] [ESI + (S*I) + d8] [ESl + (S*I) + d32]
1 11 [ED1 + (S*l)] [ED1 + ( S * I ) + d8] [ED1 + (S*I) + d32]

NOTE: S'I EQUALS THE SCALING FACTOR TIMES THE INDEX VALUE.

Figure 7-38

5. For the instruction MOV [ESl + (EDX*8)],EAX, what are the base field
bits?
 EXERCISE

29. Press the STEP switch until the address 05004 appears on the
address bus. What instruction is the program at?

30. What instruction will be executed next?

31. Press the STEP switch until 05000 appears on address bus and the
W/R# line is HIGH. What hex data appears on the data bus?

32. Is the program in an odd or even loop?

33. Press the STEP switch slowly and stop whenever address 05004 or
05000 appears. Observe the status of the W/R# line and the data
bus, and determine the program's position on the flow chart. Stop
when you return to a write instruction at address 05000.

34. Set the SINGLE CYCLE switch to OFF and press RESET.

35. Turn on CM switch 5 to insert a fault into the memory circuit. Press
RESET, and set the SINGLE CYCLE switch to ON. The CM affects
the read instructions.

36. Slowly step through the bus cycles. Does the CM affect address bus
lines A7 to AO, A15 to A8, data bus lines D7 to DO, or D15 to D8?

37. Turn off CM switch 5.

CONCLUSIONS

1. A simple loop program can test one or several addresses in memory.

2, A loop test program can use write and read instructions combined with
a jump instruction, which causes the program to run continuously.
Using the 80386 CPU Instructions - I
3. You detect faults with a loop test program by single bus cycling the
program and comparing the data on the address and data bus lines with
the programmed data.

4. When you detect a fault by single bus cycling the loop test program,
you can isolate the fault by observing the signals in the memory inter-
face circuits, peripheral chips, and memory chips.

REVIEW QUESTIONS
(Refer to the following program to answer the review questions.)

ADDRESS CONTENTS MNEMONICS REMARKS

04000 66 F0F0F0F0 F0F0F0F0H TO EAX

04006 66 A3 52 MOV WRITE TO MEMORY
66 BO 52 MOV READ FROM MEMORY
EB F6 JMP REPEAT TEST

1. What memory address does the loop program test? (The data segment
base address is 00000.)

a. 0F0F0
b. 0B052
c. 05290
d. 04003

2. What data does the loop program use to test the memory address?

a. F0F0F0F0
b. 66A3B052
c. 6698
d. EBF8

3. For how long will the loop test program run?

a. 3 loops
b. 50 loops
c. 1000 loops
d. The program will run continuously.

4. How do you use the program to detect a memory address fault?

a. step through each instruction

b. step through each bus cycle in the single cycle mode
c. let the program run until the fault is detected
d. All of the above.
 EXERCISE
7-3
5. Place the NORM/TEST shunt in the PARALLEL PORT in the NORM
position. Set the DIP SWITCH for PA7-PA4 to equal 1111 (switch up is
1). Connect the W/R# pin at JP3 to the LOGIC PROBE. Set the SINGLE
CYCLE switch to OFF, and then press RESET.

Enter "0000" in the DS register.

Enter the above program starting at address 0000:4000.
Press <GO> and enter "0000 4000".
Turn the SINGLE CYCLE switch to ON. Press STEP until 054BO ap-
pears on the address LEDs and the W/R# signal is HIGH.

Turn on CM switch 14 to introduce a fault in a data line to RAM.

Press STEP once. The W/R# signal changes to LOW. The fault is in
which data bus line?

Turn off CM switch 14.

 EXERCISE
Using the 80386 CPU
Instructions - I1
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to use 80386 CPU
instructions to create a program that tests a range of memory addresses.
You will verify your results by observing the display or address and data
LEDs.

DISCUSSION
The test loop program that you used in the Exercise 3 PROCEDURE is help-
ful for testing a single address in memory or a peripheral device. However, it
is not practical for testing a range of addresses in memory.
You will use the memory test program below to locate a defective memory
location in RAM. This program is essentially the same as the memory test
program the 32-BIT MICROPROCESSOR circuit board performs if the
NORM/TEST shunt in the PARALLEL PORT circuit block is in the TEST
position and the DIP SWITCH is set for PA7-PA4 equals 1111. When the
defective address is located with this program, you can easily locate the
RAM chip associated with the address.

ADDRESS CONTENTS MNEMONICS REMARKS

SET TEST DATA TO ZERO

I MOV INITIALIZE MEM POINTER
MOV INITIALIZE MEM ADDRESS
INC BX NEXT ADDRESS
CMP BX,DI IF INIT DONE, START TEST
JLE 4004H ELSE INIT NEXT ADDRESS
MOV BX,SI RESET MEM ADD TO START
CMP DL,[BX] IS DATA EQUAL
JNE 4OIDH IF NOT, TRAP ERROR
INC BYTE PTR [ B X ] ELSE INC TESTED DATA
INC BX NEXT ADDRESS
CMP BX,DI ALL ADDRESSES TESTED?
JLE 400DH IF NOT TEST NEXT ADDRESS
INC DL ELSE INC TEST DATA
JNZ 400BH IF NOT LAST DATA. REPEAT
INT 3 ELSE TRAP NO ERROR HERE
INT 3 TRAP ERROR HERE

In this program, register SI contains the offset value for the starting address
for the memory section to be tested, and register Dl contains the offset value
for the ending address. The DS register selector value will be set to 0000
(base address equal to 0000). Register BX contains the offset value to the
DS's base address for the current test address.
Register DL contains the data that is used to test each memory address
(location). The test data is incremented by 1 each time through the loop from
00 to FF.
The first 6 six instructions (from 04000 to 04009) initialize each address to
be tested with the test data 00; the program keeps looping between 04004
and 04009 until all memory addresses contain hex 00. The next instruction
(0400B) resets the memory address to the starting address, whose offset
value is contained in the SI register.
 EXERCISE
7-4
3. Press <EXIT>, and then <READ>. Beginning at address 04000
(0000:4000) enter the program shown below.

ADDRESS CONTENTS MNEMONICS REMARKS

B2 00 SET TEST DATA TO ZERO

DE MOV INITIALIZE MEM POINTER
88 17 INITIALIZE MEM ADDRESS
43 INC NEXT ADDRESS
DF CMP IF DONE, START TEST
7E JLE ELSE NEXT ADDRESS
DE MOV RESET MEM ADD TO START
17 CMP IS DATA EQUAL
75 JNE IF NOT, TRAP ERROR
FE 0 7 INC BYTE PTR [Bx] ELSE INC TESTED DATA
43 INC BX NEXT ADDRESS
DF CMP ALL ADDRESSES TESTED?
7E F5 JLE IF NOT TEST NEXT ADDRESS
FE INC DL ELSE INC TEST DATA
75 EF JNZ IF NOT LAST DATA. REPEAT
CC INT 3 ELSE TRAP NO ERROR HERE
CC INT 3 TRAP ERROR HERE

4. To observe data changes in the DX and BX registers and in memory,

press <REG>, and then enter: "FFFF" in the DX and BX registers.
Press <EXIT>, press <READ>, and then enter "0000 6000". In
addresses 06000 to 06007, enter "FF".

5. Press <STEP> to execute the first instruction, MOV DL,OO. Read the
DL register. Was hex 00 moved to the DL register?

6. Press <EXIT>, and then press <STEP> to execute the second

instruction, MOV BX,SI. Read the BX register. Was the starting
offset value 6000 moved to the BX register?

7. Press <EXIT>, and then press <STEP> to execute the third instruc-
tion, MOV [BX],DL. This instruction moves the contents of the DL
register (00) to memory address 06000. Read address 06000. Was
hex 00 moved to address 06000?
 EXERCISE
-

14. What will the instruction CMP DL,[BX] at address 0400D do?

15. Press <STEP> to execute CMP DL,[BX] at address 0400D. Address

0400F appears on the display.

16. What will the program do when you press <STEP> to execute JNE
401 D at address 0400F?

17. Press <STEP> to execute JNE 401DH at address 0400F. Address

04011 appears on the display.

18. Press <STEP> to execute INC BYTE PTR [BX] at address 04011.
Read address 06000. Were the contents of address 06000 incre-
mented from hex 00 to O1?

19. Press <STEP> two times to execute INC BX and CMP BX,DI.
Address 0401 6 appears on the display.

20. What will the program do when you press <STEP> to execute JLE
400DH at address 0401 6?

21. Press <STEP> to execute JLE 400DH. Address 0400D appears.

What will the instruction CMP DL,[BX] at address 0400D do?

22. Press <STEP> five times to execute the instructions from 0400D to
0401 4. Address 04016 should appear on the display.

The hex 00 data at address 06001 was tested and then incremented
to 01; the value in the BX register was incremented to 06002; and
then the values in the BX and Dl registers were compared.
Using the 80386 CPU Instructions - II
23. What will the program do when you press <STEP> again to execute
JLE 400DH at address 04016?

24. Press <STEP> to execute JLE 400DH. Address 04018 appears on

the display.

25. Press <STEP> to execute INC DL at address 04018. Read the DL

register. What value does it contain?

26. If the contents of the DL register are not (N) zero (Z), the next
instruction JNZ 400BH at address 0401A causes a jump (J) back to
0400B.

27. Press <EXIT>, and then press <STEP> to execute JNZ 400BH. The
program returns to instruction MOV BX,SI at address 0400B.

When you press <STEP>, the instruction MOV BX,SI resets the BX
register to the starting address offset value, 6000.

28. What does the memory test program do during the next pass through
the address test loop from addresses 0400D to 0401 6?

. Now that you have stepped through the instructions from addresses
04000 to 0401A, you will run the memory test program to test
addresses 06000 to O6FFF with data from hex 00 to FF.

30. Enter address "6FFF" in the Dl register, which is the ending address.

31. With the SI register containing 6000 and the Dl register containing
GFFF, what address range will this program test?

32. Press <EXIT> and then press <GO>, and run the program from
address 0000:4000. The test will take several seconds to finish.
 EXERCISE
I

Table 8-2
--

ITEM NOMINAL VALUE OBSERVED VALUE

DISPLAY STARTUP MESSAGE YES NO
ADDRESS LEDS PULSING YES NO
DATA LEDS PULSING YES NO
KEYPAD OPERATIONAL YES NO
MEMORY TEST OPERATIONAL YES NO
(keypad)
MEMORY TEST OPERATIONAL YES
(TEST shunt) NO
RESETSTATE CORRECT
SIGNALS NO
EXTERNAL SIGNALS CORRECT YES
No
SIGNALS
KEYPADSCAN SIGNALS CORRECT YES NO
LOOP
MONITOR OPERATIONAL YES NO
IN ITIALIZATION

5. If the monitor has properly initialized, the system is in the function

mode, waiting for your first keypad command. Press <REG> and
look at the contents of several of the CPU registers. Is the keypad
functioning?

6. In Table 8-2, circle YES in the OBSERVED VALUE column across

from KEYPAD in the ITEM column. An operating keypad indicates
that the monitor is working correctly up to this point and also verifies
the operation of the keypad interface, display, and part of the PPI.

The monitor ROM on your circuit board contains a memory test program
similar to the one you analyzed in Unit 7. The program in the monitor checks
all RAM locations (0000-07FFFH) by loading them with OOH, then reading all
locations to verify that they contain OOH. The test is repeated with 01H, 02H,
and so on up to FFH.
While the test is running, the LCD displays "MEMORY TEST" followed by
the data byte that is currently being written to and read from RAM, as shown
in Figure 8-6(a) (next page). You can see the data byte count u p
sequentially from OOH to FFH. If the test is successful, the message
"MEMORY OK" appears for a few seconds in the LCD display, as shown in
Figure 8-6(b). The startup message [Figure 8-6(c)] then appears, indicating
that the CPU has returned to the function mode.
If the CPU detects a failure, the program stops and the message "MEMORY
ERROR" appears in the first display line, as indicated in Figure 8-7. The
second line shows the address, test data, and actual data at the point of
failure. This information helps you locate faulted data lines as well as which
RAM chip may contain a defective location.
Troubleshooting Basics

(b) I MEMORY OK

(c) Lab- Volt 3 2 bit

Proc. T r a i n e r

Figure 8-6

Figure 8-7

In the example shown in Figure 8-7, the CPU is writing test data 58H to all
RAM locations. When the CPU reads the actual data back from RAM, the
incorrect data 5CH appears at location 06CE9H. The last address digit
indicates which data bus is involved in the transfer (see Table 8-3).
Therefore, the 9 in address 06CE9H tells you that the error is in byte I.
When you compare the binary values of the test data (58H) and the actual
data (5CH), as in Figure 8-8, you can see that bit D10 reads high when it
should be low.
Table 8-3
ADDRESS BYTE ADDRESS BYTE
0 0
1 1
2 XXXXA 2
3 3
0 0
1 XXXXD 1
2 XXXXE 2
3 XXXXF 3

BYTE 3 BYTE 2 BYTE 1 BYTE

TEST D A T A 58H =
ACTUAL DATA = 5 C H =

Figure 8-8
 EXERCISE

PROCEDURE A

1. R u n t h e main p e r f o r m a n c e check on your 32-BIT MICRO-

PROCESSOR circuit board. Verify that the circuit operation conforms
to the specifications provided in Table 8-1 1.

Table 8-1 1

ITEM NOMINAL VALUE* OBSERVED VALUE

DISPLAY STARTUP MESSAGE YES NO
ADDRESS LEDS PULSING YES NO
DATA LEDS PULS lNG YES NO
KEYPAD OPERATlONAL YES NO
MEMORY TEST OPERATIONAL YES NO
(keypad)
MEMORY TEST OPERATIONAL YES NO
(TEST shunt)
RESET STATE CORRECT YES NO
SIGNALS
EXTERNAL SIGNALS CORRECT YES NO
SIGNALS
KEYPAD SCAN SIGNALS CORRECT YES NO
LOOP
MONITOR OPERATIONAL YES NO
INITIALIZATION

* after reset, with SINGLE CYCLE switch off

2. Have your instructor insert a fault into t h e system. Qn t h e

PRACTICAL SKILLS ASSESSMENT form a t t h e end of t h i s
procedure, indicate the answer which best defines the circuit fault.

3. Have your instructor remove the fault.

4. Check circuit performance for proper operation

32-818 MICROPROCESSOR
PRACTICAL SKILLS ASSESSMENT

A. The fault is
a. CLK shorted to ground.
b. A1 shorted to A2.
c. MROMSEL# shorted to V cc .
d. W/R# shorted to ground .
 EXERCISE

PROCEDURE B
8-2
1. R u n t h e main performance check on your 32-BIT MICRO-
PROCESSOR circuit board. Verify that the circuit operation
conforms to the specifications provided in Table 8-1 2.

Table 8-12

ITEM NOMINAL VALUE* OBSERVED VALUE

DISPLAY STARTUP MESSAGE YES NO
ADDRESS LEDS PULSING YES NO
DATA LEDS PULSING YES NO
KEYPAD OPERATIONAL YES NO
MEMORY TEST OPERATIONAL YES NO
(keypad)
MEMORY TEST OPERATIONAL YES NO
(TEST shunt)
RESET STATE CORRECT YES NO
SIGNALS
EXTERNAL SIGNALS CORRECT YES NO
SIGNALS
KEYPAD SCAN SIGNALS CORRECT YES NO
LOOP
MONITOR OPERATIONAL YES NO
INITIALIZATION

* after reset, with SINGLE CYCLE SWITCH off

2. Have your instructor insert a fault into the system. On the

PRACTICAL SKILLS ASSESSMENT form at the end of this
procedure, indicate the answer which best defines the circuit fault.

3. Have your instructor remove the fault.

4. Check circuit performance for proper operation.

32-BIT MICROPROCESSOR
PRACTICAL SKILLS ASSESSMENT
B. The fault is
a. ADS# shorted to VCC.
b. ADS# open.
c. RDY# shorted to VCC.
d. RDY# shorted to ground.
 EXERCISE

PROCEDURE E

1. Run the main performance check on your 32-BIT MICRO-

PROCESSOR circuit board. Verify that the circuit operation
conforms to the specifications provided in Table 8-15.

Table 8-15

ITEM NOMINAL VALUE* OBSERVED VALUE

DISPLAY STARTUP MESSAGE YES NO
ADDRESS LEDS PULSING YES NO
DATA LEDS PULSING YES NO
KEYPAD OPERATIONAL YES NO
MEMORY TEST OPERATIONAL YES NO
(keypad)
MEMORY TEST OPERATIONAL YES NO
(TEST shunt)
RESET STATE CORRECT YES NO
SIGNALS
EXTERNAL SIGNALS CORRECT YES NO
SIGNALS
KEYPAD SCAN SIGNALS CORRECT YES NO
LOOP
MONITOR OPERATIONAL YES NO
INITIALIZATION

* after reset, with SINGLE CYCLE switch off

2. Have your instructor insert a fault into the system. On the

PRACTICAL SKILLS ASSESSMENT form at the end of this
procedure, indicate the answer which best defines the circuit fault.

3. Have your instructor remove the fault.

4. Check circuit performance for proper operation.

32-BIT MICROPROCESSOR
PRACTICAL SKILLS ASSESSMENT
E. The fault is
a. MROMSEL# shorted to Vcc.
b. BS16# shorted to Vcc.
c. BS16# shorted to ground.
d. A1 shorted to A2.
 EXERCISE

PROCEDURE G

1. Run t h e main performance check o n your 32-BIT MICRO-

PROCESSOR circuit board. Verify that the circuit operation
conforms to the specifications provided in Table 8-1 7.

Table 8-17

ITEM NOMINAL VALUE* OBSERVED VALUE

DISPLAY STARTUP MESSAGE YES NO
ADDRESS LEDS PULSING YES NO
DATA LEDS PULSING YES NO
KEYPAD OPERATIONAL YES NO
MEMORY TEST OPERATIONAL YES NO
(keypad )
MEMORY TEST OPERATIONAL YES NO
(TEST shunt)
RESETSTATE CORRECT YES NO
SIGNALS
EXTERNAL SIGNALS CORRECT YES NO
SIGNALS
KEYPADSCAN SIGNALS CORRECT YES NO
LOOP
MONITOR OPERATIONAL YES NO
lNlTlALlZATlON

* after reset, with SINGLE CYCLE switch off

2. Have your instructor insert a fault into the system. On the

PRACTICAL SKILLS ASSESSMENT form at the end of this
procedure, indicate the answer which best defines the circuit fault.

3. Have your instructor remove the fault.

4. Check circuit performance for proper operation.

32-BIT MICROPROCESSOR
PRACTICAL SKILLS ASSESSMENT
G. The fault is
a. CLK shorted to ground.
b. ADS# shorted to ground.
c. RDY# shorted to Vcc.
d. BEO# shorted to Vcc.
 EXERCISE

PROCEDURE H
8-2
1. Run the main performance check o n your 32-BIT MICRO-
PROCESSOR circuit board. Verify that the circuit operation
conforms to the specifications provided in Table 8-1 8.

Table 8-18.

ITEM NOMINAL VALUE* OBSERVED VALUE

DISPLAY STARTUP MESSAGE YES NO
ADDRESS LEDS PULSING YES NO
DATA LEDS PULSING YES NO
KEYPAD OPERATIONAL YES NO
MEMORY TEST OPERATIONAL YES NO

MEMORY TEST OPERATIONAL YES NO

(TEST shunt)
RESET STATE CORRECT YES NO
SIGNALS
EXTERNAL SIGNALS CORRECT YES NO
SIGNALS
KEYPADSCAN SIGNALS CORRECT YES NO
LOOP
MONITOR OPERATIONAL YES NO
INITIALIZATION

* after reset, with SINGLE CYCLE switch off

2. Have your instructor insert a fault into the system. On the

PRACTICAL SKILLS ASSESSMENT form at the end of this
procedure, indicate the answer which best defines the circuit fault.

3. Have your instructor remove the fault.

4. Check circuit performance for proper operation.

32-BIT MICROPROCESSOR
PRACTICAL SKILLS ASSESSMENT
H. The fault is
a. RESET switch normally open
contact shorted to common.
b. HALT switch normally open
contact shorted to common.
c. CLK2 shorted to Vcc.
d. CLK shorted to Vcc.
 APPENDIX B
ANSWERS TO REVIEW QUESTIONS

EXERCISE 1-1
I . d. All of the above.
2. d. repeating low pulse
3. a. IR CONTROLLER
4. b. the information is constantly changing.
5. c. BUS CONTROL

EXERCISE 1-2
1. c. Both of the above.
2. d. CS-IP
3. a. 33333333H
4. c. the first byte of the next eight bytes in the program listing.
5. d. STEP

EXERCISE 2-1
I . b. ADS# and READY#
2. b. 2
3. c. C
4. c. Signal Address Valid
5. b. when READY# is low at the end of a T2 State.

EXERCISE 2-2
I . a. ADS#
2. c. C
3. c. 7004H
4. b. BE1#
5. b. M/IO#

EXERCISE 2-3
I . c. W/R#
2. a. within that cycle.
3. d. cannot be determined (M/lO# level is unknown).
4. c. memory data read
5. b. instructions are fetched from memory, not from I/O.

EXERCISE 2-4
I . c. fetches an instruction from address FFFF FFFOH.
2. c. 1/0 data read
3. d. external reset
4. a. when C40 charges up to the inverter's input threshhold voltage.
5. c. generating one PLDRDY# pulse each time S7 is pressed.

EXERCISE 3-1
I . c. bidirectional data lines
2. d. All of the above.
3. b. 00 00
4. d. All of the above.
5. a. MWTC#

EXERCISE 3-2
1. a. part of the CPU address bus.
2. c. 16
3. a. 1 X
4. a. I 0 0 0 0 H is an image of 00000H.
5. c. Both of the above.
DR#
DR#