Ajay Maheswaran R 217, Saraswathi Hostel, IIT Madras

EE14B003
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Indian Institute of Technology Madras
E DUCATION AND S CHOLASTIC A CHIEVEMENTS
PROGRAM INSTITUTION % / C G PA COMPLETION
B Tech, Electrical Engineering Indian Institute of Technology Madras 7.93/10 2018
XII (CBSE) Maharishi Vidya Mandir Senior Secondary School 94.2% 2014
X (CBSE) Maharishi Vidya Mandir Senior Secondary School 10/10 2012
• Awarded KVPY Scholarship (top 1% out of 10,000 applicants) and offered provisional admission to IISER and IISc
• Secured rank 8 in Regional Maths Olympiad,Chennai Region and qualified for INMO

R ELEVANT C OURSEWORK
• Digital IC Design* • Power Management IC design* • Device Modelling • DSP algo. in architecture
• Analog IC Design • Digital Design Verification • Advanced Topics in DSP* • Computer Architecture
T ECHNICAL S KILLS
• Programming languages- C, C++, Python, Perl • Others- NuSMV, SpiceLT, LabView, Altium
• Hardware Description Languages- Verilog, System-Verilog, VHDL
P ROFESSIONAL E XPERIENCE
R&D Intern-Samsung R&D Institute,Delhi May 2017 - July 2017
• Worked on architecture of Motion Estimation block of HEVC codec and developed RTL of filters in the same block
• Developed a Perl script to generate RTL of Filter Block whose parameters are flexible
Technical Intern-GhostVR May 2016 - Dec 2016
• Developed the macro architecture of motherboard of single board computer for VR applications
• Designed the schematic and layout of the same as six layer PCB
R&D Intern-DRDO,India Dec 2015 - Jan 2016
• Performed a thorough-bred analysis on cryptographic algorithms
• Performed a feasibility analysis on AES algorithm

C OURSE P ROJECTS
Design of a Fully Differential 2-stage Op-Amp
• Designed a Fully Differential 2-stage Op-Amp in 180nm TSMC process in LT Spice, ensured Closed loop stability by Miller compensation of
the second stage, optimized the Op-Amp performance for noise, slew rate and power
Design of CORDIC algo. block in RTL
• Designed a RTL block to calculate cosine and sine values using cordic algorithm and verified the same block
Design and Verification of custom vending machine
• Designed a multi-function Vending machine RTL and verified the same using System-Verilog properties and assertions
Design of a Class-D amplifier
• Designed an audio amplifier by implementing Schmitt trigger, integrator and a non-overlap generator circuits
JPEG-Encoder Source Code Profiling and improvement
• Performed profiling of JPEG Encoder source code,identified the bottle-necks and improved the run-time
Circuit simulator for linear devices
• Designed a linear circuit simulator that takes the inputs from a text file and creates the circuit to be simulated and solves the KCL and KVL
equations to calculate node voltages and branch currents using python and C

CFI P ROJECTS
Home Automation Project
• Developed an intelligent home automation system to control home appliances using mobile phones through bluetooth and wifi interface run
by microcontroller
Virtual Reality Initiative
• Developed a VR environment to simulate a racing car game using electronic control over mechanical bot where fed-in data was from game
in the form of UDP packets and processing of data was done in python.

P OSITIONS OF R ESPONSIBILITY
Coordinator, Electronics Club, CFI 2015-16:Mentoring 20 students with electronics projects involving micro-controllers and
single board computers
E XTRA -C URRICULAR A CTIVITIES
• Was part of National Sports Organisation(NSO)-Sqaush during 2014-15