Chapter 1

Fundamental of MOS Theory and
CMOS Transistors
Good
Good Morning
Morning toto every
every
one
one let’s
let’s learn
learn VLSI
VLSI basic
basic
building
building block…
block…
1
Basic Switch
 A path exists when the Switch Control is closed
 If (Open) OUTPUT = unknown ; Switch is open (OFF )
 Else OUTPUT = INPUT ; Switch is closed (ON)
Switch Control
INPUT OUTPUT
Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Semiconductors
Al
SiO2
X Y
Si
edge view
N+ N+
N-
Conductivity of Si is proportional to No. of free carriers

(electrons or “holes”)
No. of free carriers is “programmable”:
a. At fabrication time (N- means “small excess of electrons”

N+ means “large excess of electrons”)
b. At “run” time (heat/light/static charge/injection).
MOS Transistor
Al
SiO2
X gate Y
Si
+ + + + + + + + + + + + +
- - - - - - - - - - - - -
N+ N+
P-
1. The gate (metal) / SiO2 (oxide) / Si (semiconductor)

sandwich makes a capacitor.
2. Charging the capacitor brings carriers to the surface of the
oxide -- the carriers on the Si side make a high-conductivity
channel.
3. Result: a switch!
0V on gateProf.Kunal
-> OFF; +5V
N Dekate, on gate
G H Raisoni ->of Engineering
college ON Nagpur
The Analogy of A Transistor
Switch Control (Gate)
INPUT OUTPUT
Cross Section
An N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET)

 NMOS Transistors
 4 electrical terminals
Gate
 Source
 Drain

Gate Source Drain

Substrate Substrate (Body)
 Connected to Gnd
 Source and drain are only different in their interpretation


Terminal with lower voltage is the source (by convention)
VG
 Simplified symbol omits the substrate
VS VD
 PMOS Transistors
 Same 4 electrical terminals
Gate
 Source
 Drain
Drain Source

Gate
VDD

Substrate Substrate (Body)
 Connected to VDD
 Again, source and drain are only different in their

interpretation

Terminal with higher voltage is the source (by convention)
VG
 Simplified symbol omits the substrate VS VD

Physical Structure of MOS FETS
NMOS

PMOS
Transistor Characteristics
 Cut-off Region
 Vgs – Vt ≤ 0
 No current (Ids) between drain and source
 Linear (or Ohmic) Region
 0 < Vds < Vgs – Vt Drain
 Ids is a function of Vgs and Vds
 Ids = β*[(Vgs-Vt)*Vds – Vds*Vds/2] Gate Vds
Ids
 Saturation Region
 0 < Vgs – Vt < Vds Vgs Source
 Ids is independent of Vds
 Ids = (β/2)*(Vgs-Vt)2 N-type MOS Transistor
 β = process factor * (W/L)
 Vt : Threshold voltage, a function of
materials, doping, insulator thickness, etc.
Transistor Characteristics

0
MOS Capacitor
 Gate and body form MOS
capacitor
 Operating modes
 Accumulation
 Depletion
 Inversion

1
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs
Vg
 Vgs = Vg – Vs +
+
Vgs Vgd
 Vgd = Vg – Vd - -
 Vds = Vd – Vs = Vgs - Vgd Vs
-
Vd
Vds +
 Source and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence V ≥ 0
ds
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
 Cutoff
 Linear
 Saturation
3: CMOS Transistor
12 of Engineering Nagpur
Theory Prof.Kunal N Dekate, G H Raisoni college
2
nMOS Cutoff
 No channel
 Ids ≈ 0
Vgs = 0 Vgd
+ g +
- -
s d
n+ n+
p-type body
b

3
nMOS Linear
 Channel forms
 Current flows from d to s Vgs > Vt
Vgd = Vgs
 e from s to d
- +
-
g +
-
s d
 Ids increases with Vds n+ n+ Vds = 0
p-type body
 Similar to linear resistor b
Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

4
Switches in Series
INPUT
Truth Table
S1
S1 S2 PATH?
OFF OFF
OFF ON
S2 ON OFF
ON ON
OUTPUT

5
Switches in Series
INPUT
Truth Table (OFF/ON=0/1)
S1
S1 S2 PATH?
OFF OFF NO
OFF ON NO
S2 ON OFF NO
ON ON YES
OUTPUT What Function ??

6
Switches in Series
INPUT
S1
S1 S2 PATH?
0 0 0
S2
OUTPUT Function = ??

7
Switches in Series
INPUT
S1
S1 S2 PATH?
0 0 0
0 1 0
S2

8
Switches in Series
INPUT
S1
S1 S2 PATH?
0 0 0
0 1 0
S2 1 0 0

9
Switches in Series
INPUT
S1
S1 S2 PATH?
0 0 0
0 1 0
S2 1 0 0
1 1 1
OUTPUT Function = Logic AND

0
Switches in Parallel
INPUT
Truth Table
S1 S2 PATH?
OFF OFF NO
S1 S2
OFF ON YES
ON OFF YES
ON ON YES
OUTPUT

1
INPUT
Truth Table
S1 S2 PATH?
0 0 0
S1 S2
OUTPUT Function =??

2
INPUT
Truth Table
S1 S2 PATH?
0 0 0
S1 S2
0 1 1
OUTPUT Function =??

3
INPUT
Truth Table
S1 S2 PATH?
0 0 0
S1 S2
0 1 1
1 0 1
OUTPUT Function =??

4
INPUT
Truth Table
S1 S2 PATH?
0 0 0
S1 S2
0 1 1
1 0 1
1 1 1
OUTPUT Function = Logic OR

5
CMOS Transistor
 Complementary MOS
Source
 P-channel MOS (pMOS)
Gate  N-channel MOS (nMOS)
 pMOS
Drain  P-type source and drain diffusions
pMOS  N substrate
 Mobility by holes
Drain  nMOS
Gate
 N-type source and drain diffusions
 P substrate
Source
 Mobility by electrons
nMOS
6
Pass Transistor using NMOS
Gate=Vdd  Assume capacitor (CL)
Vgs
Vin=Vdd is initially discharged
Vout
I
 Gate=1, Vin=1
Load Capacitor
 CL begins to conduct and
charges toward 1 (Vdd)
Ground and stops at (Vdd-Vt)
 Signal is degraded
Gate=Vdd
Vgs  Gate=1, Vin=0
Vin=0
Vout=Vdd  CL begins to discharge
I toward 0
Load Capacitor 
Ground
7
 Voltage Levels
 The binary values 0 and 1 can be represented as levels

of current or of voltage  voltageVoltage
is most common
V DD
 Positive logic system associates
1 with high and 0 with low Logic value 1
V 1,min
 Max voltage is VDD (or VCC)
Undefined
 5V for TTL
 Much smaller (1.0 V) for ASICs V 0,max
Logic value 0
 Min voltage is VSS (or Gnd)
8 
Typically 0V V SS (Gnd)
 Logic Ranges
 Typically V0,max = 0.4VDD and V1,min = 0.6VDD
Voltage
5V V DD
Logic value 1
3V V 1,min
Undefined
2V V 0,max
Logic value 0
V SS
Prof.Kunal N Dekate, GH (Gnd)
Raisoni college of Engineering Nagpur
9
Transmission Degradation using
Pass Transistor
Vdd (1)
Vdd Vdd - Vt
Vdd - 2Vt
Vdd
Vdd
Vdd
Vout = Vdd- N*Vt
Still 1??

0
CMOS Signal Transfer Property
Source
Gate Path
Gate • Transmits 1 well
0 Closed • Transmits 0 poorly
1 Open
Drain
pMOS
Drain
Gate
Gate Path
0 Open
• Transmits 0 well
1 Closed
Source • Transmits 1 poorly
nMOS
1
CMOS Transmission Gate
 Transmit signal from INPUT to OUTPUT when Gate
is closed
Gate (complementary of Gate)

Gate
Gate pMOS nMOS OUTPUT

Source Drain
0 OFF OFF Z
INPUT OUTPUT
1 ON ON INPUT
Z : High-Impedance State,
Gate consider the terminal is “floating”

2
High Impedance
 When a path exists
Gate=1
 Impedance is low to << 10KΩ
allow ample flow of Source Drain
current
Closed
 When no path Gate=0

>> 100MΩ
 Impedance is high
allowing almost no Source Drain
current flow between Open
two terminals

3
Transmission Gates
Transmit Logic 0 Transmit Logic 1
Gate = 0 Gate = 0
0 0 1 1
Gate = 1 Gate = 1

4
Transmission Gate Symbol
Gate
INPUT OUTPUT
≡
Gate

5
CMOS Inverter
 Connect the following terminals of a PMOS and an NMOS
 Gates
 Drains
Vdd Vdd
Vdd
PMOS Vin Vin

OFF ON
Vin Vout Vout Vout
NMOS Vin ON
Vin OFF
Gnd Gnd
Ground
Vin = HIGH Vin = LOW
Vout = LOW (Gnd) Vout = HIGH (Vdd)

6
CMOS Voltage Transfer Characteristics
Vdd
PMOS
Vin Vout
NMOS
Gnd
OFF: V_GateToSource < V_Threshold

LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold
SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource
Note that in the CMOS Inverter → V_GateToSource = V_in
7
Pull-Up and Pull-Down Network
 CMOS network consists of a Pull- Vdd
UP Network (PUN) and a Pull-
Down Network (PDN)
PUN
 PUN consists of a set of PMOS
transistors
 PDN consists of a set of NMOS ….
OUPTUT
transistors I0
 PUN and PDN implementations I1
PDN
are complimentary to each other
 PMOS ↔ NOMS In-1
 Series topology ↔ Parallel topology
Gnd

8
PUN/PDN of a CMOS Inverter
Vdd
A B
Pull-Up 0 1
Network
1 Z
A B
A B
Pull-Down 0 Z
Network
1 0
Gnd
A B
Combined
CMOS 0 1 CMOS Inverter
Network 1 0

9
Gate Symbol of a CMOS Inverter
Vdd
A B A B
B=Ā
Gnd
CMOS Inverter

0
PUN/PDN of a NAND Gate
A B C
0 0 1 Vdd
Pull-Up
0 1 1
Network
1 0 1
1 1 Z A B
A B C
Pull-Down 0 0 Z
C
Network 0 1 Z
1 0 Z A
1 1 0

1
PUN/PDN of a NAND Gate
A B C
0 0 1 Vdd
Pull-Up
0 1 1
Network
1 0 1
1 1 Z A B
A B C
Pull-Down 0 0 Z
C
Network 0 1 Z
1 0 Z A
1 1 0
B
A B C
0 0 1
Combined
CMOS 0 1 1
Network 1 0 1
1 N Dekate,
Prof.Kunal 1 0 G H Raisoni college of Engineering Nagpur
2
NAND Gate Symbol
Truth Table
Vdd
A B C
0 0 1
0 1 1 B
A
1 0 1
1 1 0
C
A
A
C
B B
C = A⋅B

3
PUN/PDN of a NOR Gate
A B C Vdd
0 0 1
Pull-Up
0 1 Z
Network
1 0 Z A
1 1 Z
A B C B
Pull-Down 0 0 Z
Network 0 1 0 C
1 0 0
1 1 0
A B

4
PUN/PDN of a NOR Gate
A B C Vdd
0 0 1
Pull-Up
0 1 Z
Network
1 0 Z A
1 1 Z
A B C B
Pull-Down 0 0 Z
Network 0 1 0 C
1 0 0
1 1 0
A B
A B C
0 0 1
Combined
CMOS 0 1 0
Network 1 0 0
1 N Dekate,
Prof.Kunal 1 0 G H Raisoni college of Engineering Nagpur
5
NOR Gate Symbol
Vdd
Truth Table
A B C
0 0 1 A
0 1 0
1 0 0
B
1 1 0
A
C
A B
B
C=A+B

6
How about an AND gate
Vdd
Vdd
A B
C A
C
A B
B C=AB
Gnd
Inverter
NAN
D
7
An OR Gate
Vdd
A
Vdd
B
C A
C
B
A B
C=A+B
Gnd
Inverter
NOR
8
What’s the Function of the following
CMOS Network?
Vdd A B C
0 0 Z
Pull-Up
A A 0 1 1
Network
1 0 1
1 1 Z
B B
A B C
C Pull-Down 0 0 0
Network 0 1 Z
A B 1 0 Z
1 1 0
A B A B C
0 0 0
Combined
CMOS 0 1 1 Function = XOR
Network 1 0 1
1 1 0 Nagpur
Prof.Kunal N Dekate, G H Raisoni college of Engineering
9
Yet Another XOR CMOS Network
Vdd A B C
0 0 Z
Pull-Up
A A 0 1 1
Network
1 0 1
1 1 Z
B B
A B C
C Pull-Down 0 0 0
Network 0 1 Z
A A 1 0 Z
1 1 0
A B C
B
B 0 0 0
Combined
CMOS 0 1 1 Function = XOR
Network 1 0 1
1 1 0 Nagpur
Prof.Kunal N Dekate, G H Raisoni college of Engineering
0
Exclusive-OR (XOR) Gate
Vdd
Truth Table
A B C
A A
0 0 0
0 1 1
B B
1 0 1
1 1 0
C
A A
A C
B
B
B
C = A⋅B+ A⋅B = A ⊕ B
1
How about XNOR Gate
Truth Table
A B C
0 0 1
0 1 0 How do we draw the
1 0 0 corresponding CMOS network
1 1 1
given a Boolean equation?
A C
C = A⋅B+ A⋅B = A ⊕ B
2
How about XNOR Gate
Vdd
Truth Table
A B C A A
0 0 1 Vdd
0 1 0 B B
1 0 0
1 1 1 C
A A
A C
B B
B Inverter
C = A⋅B+ A⋅B
XORof Engineering Nagpur
Prof.Kunal N Dekate, G H Raisoni college
3
A Systematic Approach
 Each variable in the given Boolean eqn
corresponds to a PMOS transistor in PUN and an
NMOS transistor in PDN
 Draw PUN using PMOS based on the Boolean eqn
 AND operation drawn in series
 OR operation drawn in parallel
 Invert each variable of the Boolean eqn as the gate
input for each PMOS in the PUN
 Draw PDN using NMOS in complementary form
 Parallel (PUN) to series (PDN)
 Series (PUN) to parallel (PDN)
 Label with the same inputs of PUN
 Label the output
4
Example 1
Vdd
In parallel
F = A⋅C + B
In series
(1) Draw the Pull-Up Network

5
Example 1
Vdd
In parallel
A B
F = A⋅C + B
In series C
(2) Assign the complemented input

6
Example 1
Vdd
In parallel
A B
F = A⋅C + B
In series C
(3) Draw the Pull-Down Network in

the complementary form C
A

7
Example 1
Vdd
In parallel
A B
F = A⋅C + B
In series C
(3) Draw the Pull-Down Network in

the complementary form C
A

8
Example 1
Vdd
In parallel
A B
F = A⋅C + B
In series C
F
Label the output F
A C

9
Example 1
Vdd
In parallel
A B
F = A⋅C + B
In series C
Truth Table
F
A B C F
0 0 0 0 A C
0 0 1 0
0 1 0 1
B
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
0
An Alternative for XNOR Gate
Vdd
Truth Table
A B C
A A
0 0 1
0 1 0
B B
1 0 0
1 1 1
C
A A B
C
A B
C = A⋅B+ A⋅B
1
Example 3
F = A ⋅ D + B ⋅ (A + C) A C A
Start from the innermost term

B D
A D

2
Example 3
F = A ⋅ D + B ⋅ (A + C) A C A

B D
A D

3
Example 3
F = A ⋅ D + B ⋅ (A + C) A C A

B D
A D
A
B
C

4
Example 3
Vdd
F = A ⋅ D + B ⋅ (A + C) A C A
Pull-Up
Start from the innermost term Network
B D
A D
Pull-Down
A Network
B
C

5
Example 4
Vdd
F = (E + D) ⋅ (A ⋅ D + B ⋅ (A + C))
E D
Start from the innermost term Pull-Up

A C A Network
B D
F
A D E
Pull-Down
Network
A
B D
C

6
Another Example
F = A⋅C + B How ??

7
Performance 1: Gate Delay
R (on C (gate
resistance capacitance
of the of the
driver) receiver)
X Y
X (Input)
Y (Output)
Delay
Prof.Kunal proportional
N Dekate, to R
G H Raisoni college * C
of Engineering Nagpur
8
Minimum unit of delay:
tau = R * C
Al
SiO2
X gate Y
Si
Edge
view
N+ N+
P
R proportional
to L/W.
(typical: 10Kohms)
Top W
view
C proportional
L to W * L
(typical: 10fF)
L & W quantized to multiples of the
9 “minimum line width”, currently 0.13um
Gate Delay
 Minimum delay (“tau”) assumes minimum-
size transistors
 Additional delay arises from
 fanout
 real-world outputs (pins ~1pF +)
 long wires...
 Can increase driving transistor width (W) to

reduce delay.
 note exponential
Prof.Kunal N Dekate,chain.
G H Raisoni college of Engineering Nagpur
0
Performance 2: Wire Delay
R (on resistance C (gate capacitance

PLUS wire resistance) PLUS wire capacitance)
X Y
X (Input)
Y (Output)
Delay
Prof.Kunal proportional
N Dekate, to R
G H Raisoni college * C
of Engineering Nagpur
1
Reference: Prof. Hsien-Hsin Sean Lee
Lecture Notes Introduction to Computer Engg.
School of Electrical and Computer Engineering.
Georgia Institute of Technology
2

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Fundamental of MOS Theory and

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Conductivity of Si is proportional to No. of free carriers

No. of free carriers is “programmable”:

a. At fabrication time (N- means “small excess of electrons”

1. The gate (metal) / SiO2 (oxide) / Si (semiconductor)

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

 Source and drain are only different in their interpretation

 Again, source and drain are only different in their

 Simplified symbol omits the substrate VS VD

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

 Ids increases with Vds n+ n+ Vds = 0

 Similar to linear resistor b

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

OUTPUT What Function ??

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

OUTPUT Function = Logic AND

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

OUTPUT Function =??

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

OUTPUT Function =??

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

OUTPUT Function =??

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

 The binary values 0 and 1 can be represented as levels

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Gate (complementary of Gate)

Gate pMOS nMOS OUTPUT

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

 When no path Gate=0

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

PMOS Vin Vin

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

OFF: V_GateToSource < V_Threshold

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

(1) Draw the Pull-Up Network

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

(2) Assign the complemented input

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

(3) Draw the Pull-Down Network in

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

(3) Draw the Pull-Down Network in

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur

Start from the innermost term

Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur