UNIT –IV

1. Algorithmic State Machine (ASM) Charts:

The state diagrams and tables used in this chapter are convenient for describing the behavior of
FSMs that have only a few inputs and outputs. For larger machines the designers often use a
different form of representation, called the algorithmic state machine (ASM) chart. An ASM
chart is a type of flowchart that can be used to represent the state transitions and generated
outputs for an FSM. The three types of elements used in ASM charts are depicted in Figure 6.81.

• State box – A rectangle represents a state of the FSM. It is equivalent to a node in the state
diagram or a row in the state table. The name of the state is indicated outside the box in the top-
left corner. The Moore-type outputs are listed inside the box. These are the outputs that depend
only on the values of the state variables that define the state; we will refer to them simply as
Moore outputs. It is customary to write only the name of the signal that has to be asserted. Thus
it is sufficient to write z, rather than z = 1, to indicate that the output z must have the value 1.
Also, it may be useful to indicate an action that must be taken; for example, Count ← Count + 1
specifies that the contents of a counter have to be incremented by 1.

• Decision box –A diamond indicates that the stated condition expression is to be tested and the
exit path is to be chosen accordingly. The condition expression consists of one or more inputs to
the FSM. For example, w indicates that the decision is based on the value of the input w, whereas
w1 ・ w2 indicates that the true path is taken if w1 = w2 = 1 and the false path is taken otherwise.
• Conditional output box – An oval denotes the output signals that are of Mealy type. These
outputs depend on the values of the state variables and the inputs of the FSM; we will refer to
these outputs simply as Mealy outputs. The condition that determines whether such outputs are
generated is specified in a decision box.

Figure 6.81 Elements used in ASM charts.

 Figure 6.82 ASM chart for the FSM in Figure 6.3. Figure 6.83 ASM chart for the FSM in Figure 6.23.

ASM charts are similar to traditional flowcharts. Unlike a traditional flowchart, the ASM chart
includes timing information because it implicitly specifies that the FSM changes (flows) from
one state to another only after each active clock edge. The examples of ASM charts presented
here are quite simple.
We have used them to introduce the ASM chart terminology by giving examples of state,
decision, and conditional-output boxes. Another term sometimes applied to ASM charts is ASM
block, which refers to a single state box and any decision and conditional-output boxes that the
state box may be connected to. The ASM charts can be used to describe complex circuits that
include one or more finite state machines and other circuitry such as registers, shift registers,
counters, adders, and multipliers.

1. Binary Multiplier (OR) Shift-and-Add Multiplier

We presented a circuit that multiplies two unsigned n-bit binary numbers in Figure 3.35. The
circuit uses a two-dimensional array of identical subcircuits, each of which contains a full-adder
and an AND gate. For large values of n, this approach may not be appropriate because of the
large number of gates needed. Another approach is to use a shift register in combination with an
adder to implement the traditional method of multiplication that is done by “hand.”
 Figure 7.22a illustrates the manual process of multiplying two binary numbers. The
product is formed by a series of addition operations. For each bit i in the multiplier that is 1, we
add to the product the value of the multiplicand shifted to the left i times. This algorithm can be
described in pseudo-code as shown in Figure 7.22b, where A is the multiplicand, B is the
multiplier, and P is the product.
An ASM chart that represents the algorithm in Figure 7.22b is given in Figure 7.23.
Datapath Circuit
We can now define the datapath circuit. To implement A we need a right-to-left shift register that
has 2n bits. A 2n-bit register is needed for P, and it must have an enable input because the
assignment P ← P + A in state S2 is inside a conditional output box.

Figure 7.22 An algorithm for multiplication.

Figure 7.23 ASM chart for the multiplier.

Control Circuit
AnASM chart that represents only the control signals needed for the multiplier is given in Figure
7.25. In state S1, Psel is set to 0 and EP is asserted, so that register P is cleared. When s = 0,
parallel data can be loaded into shift registers A and B by an external circuit that controls their
parallel-load inputs LA and LB. When s = 1, the machine changes to state S2, where Psel is set to
1 and shifting of A and B is enabled. If b0 = 1, the enable for P is asserted. The machine changes
to state S3 when z = 1, and then remains in S3 and sets Done to the value 1 as long as s = 1.
Figure 7.24 Datapath circuit for the multiplier.

Verilog Code
Figure 7.25 ASM chart for the multiplier control circuit.

2. Asynchronous Sequential Circuits

The design of synchronous sequential circuits in which the state variables are represented by flip-
flops that are controlled by a clock. The clock is a periodic signal that consists of pulses.
Changes in state can occur on the positive or negative edge of each clock pulse. Since they are
controlled by pulses, synchronous sequential circuits are said to operate in pulse mode.
In this chapter we present sequential circuits that do not operate in pulse mode and do not
use flip-flops to represent state variables. These circuits are called asynchronous sequential
circuits. In an asynchronous sequential circuit, changes in state are not triggered by clock pulses.
Instead, changes in state are dependent on whether each of the inputs to the circuit has the logic
level 0 or 1 at any given time. To achieve reliable operation, the inputs to the circuit must change
in a specific manner.
In this introductory discussion we will concentrate on the simplest case in which a
constraint is imposed that the inputs must change one at a time. Moreover, there must be
sufficient time between the changes in input signals to allow the circuit to reach a stable state,
which is achieved when all internal signals stop changing. A circuit that adheres to these
constraints is said to operate in the fundamental mode.
Asynchronous circuits are much more difficult to design than synchronous circuits.
Terminology
However, when dealing with asynchronous sequential circuits, it is customary to use two
different terms. Instead of a “state table,” it is more common to speak of a flow table, which
indicates how the changes in state flow as a result of the changes in the input signals. Instead of a
“state-assigned table,” it is usual to refer to a transition table or an excitation table. We will use
the terms flow table and excitation table in this chapter.
 A flow table will define the state changes and outputs that must be generated. An
excitation table will depict the transitions in terms of the state variables. The term excitation
table derives from the fact that a change from a stable state is performed by “exciting” the next-
state variables to start changing towards a new state.

3. Analysis of Asynchronous Circuits

To gain familiarity with asynchronous circuits, it is useful to analyze a few examples. We will
keep in mind the general model in Figure 6.85, assuming that the delays in the feedback paths
are a representation of the propagation delays in the circuit. Then each gate symbol will represent
an ideal gate with zero delay.

Example: GATED D LATCH

We used the gated D latch as a key component in circuits that are controlled by a synchronizing
clock. It is instructive to analyze this latch as an asynchronous circuit, where the clock is just one
of the inputs. It is reasonable to assume that the signals on the D and clock inputs do not change
at the same time, thus meeting the basic requirement of asynchronous circuits.
Figure 9.4a shows the gated Dlatch drawn in the style of the model of Figure 6.85. This circuit
was introduced in Figure 5.7 and discussed in Section 5.3. The next-state expression for this
circuit is

The term Dy in this expression is redundant and could be deleted without changing the logic
function of Y . Hence the minimal expression is
 Figure 9.4 The gated D latch.

Steps in the Analysis Process

We have demonstrated the analysis process using illustrative examples. The required steps can
be stated as follows:
• A given circuit is interpreted in the form of the general model in Figure 6.85. That is, each
feedback path is cut, and a delay element is inserted at the point where the cut is made. The input
signal to the delay element represents a corresponding next-state variable, Yi , while the output
signal is the present-state variable, yi . Acut can be made anywhere in a particular loop formed
by the feedback connection, as long as there is only one cut per (state variable) loop. Thus the
number of cuts that should be made is the smallest number that results in there being no feedback
anywhere in the circuit except from the output of a delay element. This minimal number of cuts
is sometimes referred to as the cut set.
Note that the analysis based on a cut made at one point in a given loop may not produce the same
flow table as an analysis on a cut made at some other point in this loop. But both flow tables
would reflect the same functional behavior in terms of the applied inputs and generated outputs.
 • Next-state and output expressions are derived from the circuit.
• The excitation table corresponding to the next-state and output expressions is derived.
• A flow table is obtained, associating some (arbitrary) names with the particular encoded
states.
• A corresponding state diagram is derived from the flow table if desired.

4. Synthesis of Asynchronous Circuits

Synthesis of asynchronous sequential circuits follows the same basic steps used to synthesize the
synchronous circuits. There are some differences due to the asynchronous nature, which make
the asynchronous circuits more difficult to design. We will explain the differences by
investigating a few design examples.
The basic steps are
• Devise a state diagram for an FSM that realizes the required functional behavior.
• Derive the flow table and reduce the number of states if possible.
• Perform the state assignment and derive the excitation table.
• Obtain the next-state and output expressions.
• Construct a circuit that implements these expressions.

Example: MODULO-4 COUNTER

Now we will synthesize a counter as an asynchronous sequential circuit. Figure 9.17 depicts a
state diagram for a modulo-4 up-counter, which counts the number of pulses on an input line, w.
The circuit must be able to react to all changes in the input signal; thus it must take specific
actions at both the positive and negative edges of each pulse. Therefore, eight states are needed
to deal with the edges in four consecutive pulses.
The counter begins in state A and stays in this state as long as w = 0. When w changes to
1, a transition to state B is made and the circuit remains stable in this state as long as w = 1.
When w goes back to 0, the circuit moves to state C and remains stable until w becomes 1 again,
which causes a transition to state D, and so on.
Using the Moore model, the states correspond to specific counts. There are two states for
each particular count: the state that the FSM enters when w changes from 0 to 1 at the start of a
pulse and the state that the FSM enters when w goes back to 0 at the end of the pulse. States B
and C correspond to the count of 1, states D and E to 2, and states F and G to 3. States A and H
represent the count of 0.

Figure 9.17 State diagram for a modulo-4 counter.

 Figure 9.18 Flow and excitation tables for a modulo-4 counter.
From the excitation table the next-state and output expressions are

Minimization of states is not straightforward. A minimization procedure is described in Section

9.4. State assignment is not done with the sole purpose of reducing the cost of the final circuit. In
 asynchronous circuits some state assignments may cause the circuit to be unreliable. We will
explain this problem using the examples that follow.

5. State Reduction
In Chapter 3 we saw that reducing the number of states needed to realize the functionality of a
given FSM usually leads to fewer state variables, which means that fewer flip-flops are required
in the corresponding synchronous sequential circuit. In asynchronous sequential circuits it is also
useful to try to reduce the number of states because this usually results in simpler
implementations.

Merging Procedure
In Example 9.7 it was easy to decide which rows should be merged because the only possibilities
are to merge row C with either A or E. We chose to merge C and E because this can be done
preserving the Moore model, which is likely to lead to a simpler expression that realizes the
output z.
In general, there can be many possibilities for merging rows in larger flow tables. In such cases it
is necessary to have a more structured procedure for making the choice. A useful procedure can
be defined using the concept of compatibility of states.
Definition 9.1 – Two states (rows in a flow table), Si and Sj , are said to be compatible if there
are no state conflicts for any input valuation. Thus for each input valuation, one of the following
conditions must be true:
• both Si and Sj have the same successor, or
• both Si and Sj are stable, or
• the successor of Si or Sj , or both, is unspecified.
Moreover, both Si and Sj must have the same output whenever specified.

State Reduction Procedure

We can summarize the steps needed to generate the reduced flow table from a primitive flow
table as follows:
1. Use the partitioning procedure to eliminate the equivalent states in a primitive flow table.
2. Construct a merger diagram for the resulting flow table.
3. Choose subsets of compatible states that can be merged, trying to minimize the number of
subsets needed to cover all states. Each state must be included in only one of the chosen subsets.
4. Derive the reduced flow table by merging the rows in chosen subsets.
5. Repeat steps 2 to 4 to see whether further reductions are possible.

Choosing an optimal subset of compatible states for merging can be a very complicated task
because for large FSMs there may be many possibilities that should be investigated. A trial-and-
error approach is a reasonable way to tackle this problem.

6. Hazards
In asynchronous sequential circuits it is important that undesirable glitches on signals should not
occur. The designer must be aware of the possible sources of glitches and ensure that the
transitions in a circuit will be glitch free. The glitches caused by the structure of a given circuit
and propagation delays in the circuit are referred to as hazards.
Two types of hazards are illustrated in Figure 9.61.
A static hazard exists if a signal is supposed to remain at a particular logic value when an input
variable changes its value, but instead the signal undergoes a momentary change in its required
value.
As shown in Figure 9.61a, one type of static hazard is when the signal at level 1 is supposed to
remain at 1 but dips to 0 for a short time. Another type is when the signal is supposed to remain
at level 0 but rises momentarily to 1, thus producing a glitch.
A different type of hazard may occur when a signal is supposed to change from 1 to 0 or from 0
to 1. If such a change involves a short oscillation before the signal settles into its new level, as
illustrated in Figure 9.61b, then a dynamic hazard is said to exist.

Static Hazards

Figure 9.62 An example of a static-hazard.

Figure 9.62a shows a circuit with a static hazard. Suppose that the circuit is in the state where x1
= x2 = x3 = 1, in which case f = 1. Now let x1 change from 1 to 0. Then the circuit is supposed to
maintain f = 1. But consider what happens when the propagation delays through the gates are
taken into account. The change in x1 will probably be observed at point p before it will be seen at
point q because the path from x1 to q has an extra gate (NOT) in it. Thus the signal at p will
become 0 before the signal at q becomes equal to 1.
For a short time both p and q will be 0, causing f to drop to 0 before it recovers back to 1. This
gives rise to the signal depicted on the left side of Figure 9.61a.The glitch on f can be prevented
as follows. The circuit implements the function
f = x1x2 + x1x3
The corresponding Karnaugh map is given in Figure 9.62b. The two product terms realize the
prime implicants encircled in black. The hazard explained above occurs when there is a
transition from the prime implicant x1x2 to the prime implicant x1x3. The hazard can be
 eliminated by including the third prime implicant, encircled in blue. (This is the consensus term,
defined in Property 17a in Section 2.5.) Then the function would be implemented as
f = x1x2 + x1x3 + x2x3
Now the change in x1 from 1 to 0 would have no effect on the output f because the product term
x2x3 would be equal to 1 if x2 = x3 = 1, regardless of the value of x1. The resulting hazard-free
circuit is depicted in Figure 9.62c.

Dynamic Hazards
A dynamic hazard causes glitches on 0 → 1 or 1 → 0 transitions of an output signal. An example
is given in Figure 9.66. Assuming that all NAND gates have equal delays, a timing diagram can
be constructed as shown. The time elapsed between two vertical lines corresponds to a gate
delay. The output f exhibits a glitch that should be avoided. It is interesting to consider the
function implemented by this circuit, which is

Figure 9.65 Static hazard in a POS circuit.

Figure 9.66 Circuit with a dynamic hazard.

7. A Complete Design Example

In the previous sections we examined the various design aspects of asynchronous sequential
circuits. In this section we give a complete design example, which covers all necessary steps.
The Vending-Machine Controller
The control mechanism of a vending machine is a good vehicle for illustrating a possible
application of a digital circuit. Now we will consider a vending-machine controller and it can be
implemented using an asynchronous sequential circuit.

The specification for the controller is:

• It accepts nickels and dimes.
• A total of 15 cents is needed to release the candy from the machine.
• No change is given if 20 cents is deposited.

Coins are deposited one at a time. The coin-sensing mechanism generates signals N = 1 and D =
1 when it sees a nickel or a dime, respectively. It is impossible to have N = D = 1 at the same
time. Following the insertion of a coin for which the sum equals or exceeds 15 cents, the
machine releases the candy and resets to the initial state.
Figure 9.67 shows a state diagram for the required FSM. It is derived using a
straightforward approach in which all possible sequences of depositing nickels and dimes are
enumerated in a treelike structure. To keep the diagram uncluttered, the labels D and N denote
the input conditions DN = 10 and DN = 01, respectively. The condition DN = 00 is labeled
simply as 0. The candy is released in states F, H, and K, which are reached after 15 cents has
been deposited, and in states I and L, upon a deposit of 20 cents. The corresponding flow table is
given in Figure 9.68. It can be reduced using the partitioning procedure as follows

P1 = (ADGJ)(BE)(C)(FIL)(HK)
P2 = (A)(D)(GJ)(B)(E)(C)(FIL)(HK)
P3 = P2

Figure 9.67 Initial state diagram for the vending-machine controller.

The Karnaugh maps for the next-state functions are given in Figure 9.75. From these
maps the following hazard-free expressions are obtained

Figure 9.68 Initial flow table for the vending-machine controller Figure 9.69 First step in state minimization.

Figure 9.70 Merger diagram for Figure 9.69.

Figure 9.71 Reduced flow tables. Figure 9.72 State diagram for the vending-machine controller.

Figure 9.73 Determination of the state assignment.

Figure 9.74 Excitation table based on the state assignment in
Figure 9.73b Figure 9.75 Karnaugh maps for the functions in Figure 9.74.