Digital Electronics Sequential Cicuits FF

Sequential Circuits - Flip-Flops
4-3
Digital Principles and System Design
Digital Principles and System Design 4-2 Sequential Circuits - Flip-Flops
Introduction 1~)/1 Combinational circuits are faster in speed

because the delay between input and output
•~
~i shows the block diagram
. of sequential circuit/Finite State Ma h'llle ,
.....~.~~.~:.t.0_.pr<:E~~~~<:ll_~:l.aY: ..<:~ ..~~~:.s.:_.~ .
ft .c~~cte~to.~ecoIllb;l1ational a~:::back
Combinational circuits are easy
e;eI<leIltsare drcuH pa:

Parallel adder is a combinational
Table 4.1.1 Comparison between combinational and sequential circuits
Combinational
Inp uts .... circuit
Outputs i
(Combinational
component) DII~
. /A clock signal is a particular type of signal that oscillates between a high and a
t Memory ( iow state and is utilized to co-ordinate actions of circuits.
o
elements J-;
.Z.............. . Present state Next st ate

(Sequential • It is produced by a clock generator)
component)
• The most common clock signal is in the form of a square wave with a 50 % duty
~ ~ -. -.. --. - cycle, usually with a fixed, constant frequency as shown in Fig. 4.1.2. ckJ!.-b( C'f-t
at~ the
Sequential circuit
·Fig. 4.1.1 Block diagram of sequential circuit I FSM • Circuits using the clock signal for synchronization may become active
:,smg "'3-
e, fplling edge or in the case Clock r-
• The information stored in the ory of double data rate, both in the rising - I period I--
present state of the sequential ci::: elements at any given time defines the
and in the falling edges of the clock
• The present state. and the external inputs determine
state of the sequential circuit.
th
e outputs and the next _ 'T'~. ~Fi .2 Clock signal
cycle.
~_./).le time required to complete one cycle ~/
.
• Thus we can specIify the sequential circuit b . is called 'clock period' or 'clock cycle' .
mternal states (present st t d y a time sequence of external inputs,
• ~ a es an next states), and outputs. • Ideally, the clock signal should have sharp transitions from one level to other as
..y i ne counters and registers are the comman examples of sequential circuits. shown in Fig. 4.1.2.
I-bit ,
Review Questions
between--=.=:::I::n:a=lonal
Comb' t" 1. Define sequential logic circuit.
__~;;I- and Sequential
2. What is flip·flop ?
3. Give the comparison between combinational and sequential logic circuits.
4. What is clock ? State its use.
III One-Bit Memory Cell

~ Pig. 4.2.1 shows the bask bistable clement used in latches and lHp-flops.
r'~ 1yhas
he
bask bistable element has two outputs Q and Q.
two eross-coupled inverters- i.e., the output of the first mverter is connected
/a~ ~~ ;nput to the second ;nverter and the output of second ;nverler is connected
as an input to the first inverter.
TECHNICAL PUBLICATIONS"'- An up thrust for knowledge
TECHNICAL PUBLICATIONS'" - An up thrust for knowledge

4-4 Digital Principles and System Design 4-5 Sequential Circuits - Flip-Flops
A Q A
Review Question
Q
1. Explain the operation of one-bit memory cell.
B 8 Q 8
III Latches fl. ( (7
(a) Usi~ (b) USin~AND gates (c) USiQg NO~~ II1II SR Latch
Fig. 4.2.1 ~asic bistable elem~ -blt memory cell)
• Fig. 4.3.1 shows SR latch which is l-bit
• The basic bistable element circuit has two stable ~gic 0 and logic 1, hence memory cell. S (Set)
the name 'bistable'. Q
• Two inverters 3 and 4 are connected to
• When A = 0, the output of inverter 1 is 1 (A), i.e., Q = 1. enter the digital information.
• Since the output of inverter 1 is the in..rut to the inverter 2, A = B = 1.
• Input for gate 3 is S and input for
Consequently, the output of inverter 2, .i.e., B is O.
gate 4 is R. This latch is also called RS R (Reset)
• Since the output of the inverter 2 is connected to the input of the inverter 1, latch.
Q = B = A = O.
• For understanding the circuit operation, Fig. 4.3.1 SR latch
• We have assumed same value for A. Thus, the circuit is stable with Q = A = B = 0 t f t determine the output of
and Q = A = B = 1. we mus ateIrs whose one of the . .IS IOglC. 0 and accordingly
NAND input . . we have to
• Using similar explanation it is easy to show that if it is assumed that A = 1, the . g th e ou tpu t 0 f other NAND gate in the cross coupled circuit,
determine
basic bistable element is stable with Q = A = B = 1 and Q = A = B = O. This is a • Because the output of NAND gate is 1 if anyone input is O.
second stable condition of the basic bistable element.
. as follows. In F19. 4:.,
• The circuit operation IS 3 2 the
h output
tp t off shaded NAND gate
shaded NAND as 1
• The two stable states of basic bistable elements are used to store two binary IS determined first, and the 0 input that decides t e ou u 0
elements, 0 and 1.
is shown in bold.
• In positive logic system, state Q = 1 is used to store logic 1, and state Q = 0 is Case 1 : S=R=O
used to store logic O.
. - - - - 1 If Q is I, Q and B inputs for NAND gate 2 are both.1
• Two outputs are complementary. That is when Q = 0, Q = 1; and when Q = 1, In
andthis S - R--=-.
case,output
hence . -Q -_ 0 and S = 1, the output of NAND gate 1 IS
Q = O. Since
Q = O.
1, i.e, Q = 1. tp t
Important Points
If is 0, Q and R inputs for NAND gate 2 are 0 and .1, a~d hen~e ou u
1. The outputs Q and Q are always complementary. -Q =Q1. Since
. -Q = 1 and -S -
- 1, the output of NAND gate 1 IS_ 0, i.e., Q - O.
2. The circuit has two stable states. The state corresponds to Q = 1 is referred to as . I stat e: Q -
Inilla - 0
, -Q - 1 Initial state: Q =1, Q =0
1 state or set state and state corresponds to Q = 0 is referred to as 0 state or
Reset state.
Q=O
3. If the circuit is in the set (1) state, it will remain in the set state and if the circuit is
in the reset (0) state, it will remain in the reset state. This property of the circuit
shows that it can store 1-bit of digital information. Therefore, the circuit is called a
I-bit memory cell. . 0=1
4. The 1-bit information stored in the circuit is locked or latched in the circuit. Fig. 4.3.2
Therefore, this circuit is also referred to as a latch.
m
TECHNICAL PUBLICATIONS'"- An up thrust for knowledge TECHNICAL PUBLICATIONS - An up thrust for knOWledge
4-8
Sequential brcUl1s - Flip-Flops Digital Principles and System Design 4-9 Sequential Circuits - Flip-Flops
• As shown in the truth table, the Q output

Flip-Flop is enabled
follows the 0 input. For this reason 0 latch is V
only when the level
sometimes called transparent latch. of E input is HIGH
Enable 1 -
• Looking at the truth table for 0 latch with input
(E) 01----
enable input and simplifying Q n + 1 function by 0".,0 EN'D + EN'Q"
k-map we get the characteristic equation for 0
latch with enable input . as Fig. 4.3.7 Characteristic equation F·Ig. 4..
4 1 Positive level triggering h
Q n-t- 1 = EN· 0 + EN . Q n- This is illustrated in Fig. 4.3.7. • Negativ evel triggered' '. :t1tp~---.
t of flip-flop responds to the input c anges
Review Questions ut IS 9 (LOWL/
on when its enable' r-r-:
t. V
Enable1
1. What is SR latch? Explain it's operation. input
2. What is gated SR latch ? (E) 01...----
3. Explain the working of gated D latch with truth table and characteristic equation. Flip-Flop is enabled
only when the level
DI Flip-Flops 'JJIIM"IhWPMW!IIDJliMoUWll/iIiliI!m!IU Fig. 4.4.2 Negative level triggering

of E input is LOW
I!II Latches VsFlip-FIops Ed

"
Triggering
. . the oumut respon s
d to the changes in the input only at the
""-"= . ~.
• In the edge trIggerIng,..---_ 1" k lse at the clock input.
positive or negative edge of the c o~ pu
• Latches and flip-flops are the basic bUilding blocks of the most sequential circuits.
• The main difference between latches and flip-flops is in the method used for • There are two types of edge triggermg. d to the changes in the input
changing their state. . . . Here the output respon s
• Positive edge triggering : h ' 1 k ulse at the clock i n p u t . _
• A simple latch forms the basis for the flip-flop. only at the positive edge of t e c oc p
~~~~ ,f---uJ f
• Latches are controlled by enable signal, and they are level triggered, either positive
level triggered or negative level triggered.
V
• The output state is free to change according to the Sand R input values, when
active level is maintained at the enable input.
o t. •
L Output responds
• Flip-flops are pulse or clock edge triggered instead of level triggered. 1 only at the positive
edges of the pulse
lID Level and Edge Triggering Fig. 4.4.3 Positive edge triggering ..
"~"---
Level Triggering
-- . . . Here the output respon d s t 0 the changes in the mput
• Neg ive edge triggermg ef h 'I k pulse at the clock input.
on y at the negative edge 0 t e c oc
• In the level triggering, the ou ut state is allowed to cb aceor ing to input(s)
Output responds
~~~~l~~]-----i- [
when active level (either positive or negative) is maintained at the enable input. only at the negative
• There are two types of level triggered latches : edges of the pulse
• Positive lev~d : The output of flip-flop responds to the input changes

only when its enc.bl~put~
Fig. 4.4.4 Negative edge triggering
TECHNICAL PUBLICATIONS"'. An up thrust for knowledge

TECHNICAL PUBLICATIONS"'· An up thrust for knowledge
4 - 10
Digital Principles and System Design 4 - 11 Sequential Circuits - Flip-Flops
SR Flip-Flop
Positive Edge Triggered SR Flip-Flop Case 2: If S := 0, R - 1 and the clock pulse is applied, Qn + 1 0, This is indicated in
the second row of the truth table.
• The Fig. 4.4.5 shows the positive edge triggered clocked SR flip-flop.
Gated SR latch
Case 3 : If S := 1, R := 0 and the cl~ck, pulse '"
S
d Qn + 1 := 1. This is indicated m CP
app 1·reo,
Q
the third row of the truth table.
S
Case 4 : If S := R := 1 and the clock pUl~e ~s
R--:---
I' ed the state of the fli1p-fl1p 1S
app 1 , . di t d as
d fi d and therefore is m tea e
un e me f th
indeterminate in the fourth row a e
(a) SR flip-flop using NAND gates
truth table.
(b) SR flip-flop using NOR gates
d T 'ggered SR Flip-Flop
%
Fig. 4.4.5 Clocked SR flip-flop
gative E ge n . ed SR flip-flop, the negative
• The circuit is similar to SR latch except enable signal is replaced by the Clock • In the negative edge tngger h' it output S Q
Pulse (CP) followed by the positive edge detector circuit. . .1S u sed and t e circu
. e detector circuit CP
• The edge detector circuit is a differentiator.
:";onds at the negative edges of the clock pulse, R Q
~n
. d Fi . 4.4.9 shows the logic symbol,
• The Fig. 4.4.7 shows input and output waveforms for positive edge triggered • The Fig. 4.4.8 g d au tput waveforms
truth table, and mput an , for negative
clocked SR flip-flop. (a) Logic symbol
edge triggered SR flip-flop., , -flo Fig. 4.4.8
• The circuit output responds to the Sand R inputs only at the positive edges of the • The bubble at the clock input indicates that the flip p
clock pulse. At any other instants of time, the SR flip-flop will not respond to the is negative edge triggered.
changes in input.
The Fig. 4.4.6 shows the logic symbol and truth table of clocked SR flip-flop.
CP
Qn
CP
S Q
SR
01
l--_-n
00 0
0
0 o
R,S I
I
i
I
I
I
L
R Q Q--- I
11 X X
InpUtt'gagn~r~~ ~'~cked
~~.~~~
10 t t waveforms for
(._~ .. (b) Truth Table for negative edge clocked
Fig. ;4.4.9
negative edge n SR flip-flop
SR flip-flop
(a) Logic mbol Qn+1 ::: S + Ro, Fig. 4.4.8
(b) Truth table ~sitive edge clocked
~" flip-flop (c) Characteristic equation
~.
Fig. 4.4.6
Case 1
If S R 0 and the clock pulse is applied, the output do not change, i.e.
:::0 :::0
n
Q + 1 Qn' This is indicated in the first row of the truth table.
:::0
TECHNICAL PUBLICATiONS"'. An up thrust for knowledge
TECHNICAL PUBLICATiONS"'· An up thrust for knowledge

Digital Principles and System Design 4 - 12 Sequential Circuits - Flip-Flops Digital Principles and System Design 4 - 13 Sequential Circuits - Flip-Flops
Realize SR flip-flop using NOR gates.

• These input conditions can be avoided by making them complement of each other.
Solution: This modified SR flip-flop is known as D flip-flop.
SR latch • The D input goes directly to the S input, and its complement is applied to the R
S ------\
Q input. Due to these connections, only two input conditions exists, either S = a and
R = 1 or S = 1 and R = O.
CP
ULr Truth Table
• The truth table for D flip-flop consider only these two conditions and it is as
R----I
Q shown in the Fig. 4.4.12 (b).
Fig. 4.4.10 Negative edge-triggered SR flip-flop using only NOR gates
11II D Flip-Flop
• Th~wS the logic diagrams of D flip-flop. ~. CP
L
~.
D----=:.... (b) Truth table of flip-flop (c) Input and a t waveforms
Q
D fllp-flcp
Fig. 4.4.12
• Q Fl-t- 1 function follows D input at the positive going edges of the clock pulses.
Hence the characteristic equation for D flip-flop is Q n+ 1 = D.
SR flip-flop
• The output Q n + l is delayed by one clock period. Thus, D flip-flop is also known
(a) D flip-flop as delay flip-flop.
• If we connect the Q output of D flip-flop to
its D input as shown in the Fig. 4.4.13, the
CP
output of D flip-flop will change either
from a to 1 or from 1 to a at every positive
edge of the D flip-flop.
Such change in the output is known as toggling Fig. 4.4.13
SR flip-flop
of the flip-flop output.
(b) D flip-flop using NAND gates
Fig. 4.4.11 Negative Edge Triggered D Flip-Flop
• The basic building block of D flip-flop is a SR flip-flop.
• The SR flip-flop has two data inputs Sand R. CP
• The S input is made high to store 1 in the flip-flop and R input is made high to CP
store a in the flip-flop.
D --~
• When both inputs are same the output either does not change or it is invalid
(Inputs -7 00, no change and inputs -7 11, invalid). (a) Logic symbol (b) Truth table of D flip-flop
Q---~
• In many practical applications, these input conditions are not required.
Fig. 4.4.14 Fig. 4.4.15 Input output wavef!Jrms of
negative edge triggered 0 flip-flop
TECHNICAL PUBLICATlONS"'- An up thrust for knowledge

e In case of negative edge triggering, the output is sensitive at the negative edge of
the clock input. operation of JK flip-flop
e The Fig. 4.4.14 shows the logic symbol and truth table for negative edge triggered Case 1 : J= K == 0
D flip-flop. When J = K = a, S = R = a and according to truth table of SR flip-flop there is
e Fig. 4.4.15 shows input and output waveforms for negative edge triggeredD no change in the output.
flip-flop. When inputs J = K == a, output does not change.
e The bubble at the clock input indicates that the flip-flop is negative edge triggered.
Case 2 ~ J == 1 and K == 0
Q == 0, Q = 1 : When J = I, K = a and Q = a, S == 1 and R = O. According to
truth table of SR flip-flop it is set state and the output Q will be 1.
Q == I, Q = 0 : When J = I, K = a and Q = I, S = a and R = O. Since SR =00,
there is no change in the output and therefore, Q = 1 and Q = O.
TheinputsJ;;:;l and K=O,
Fig. Case 3 : J == 0 and K =1

Solution: Q = 0, Q = 1 : When J = a, K = 1 and Q = a, S = a and R = O. Since SR = 00,
there is no change in the output and therefore, Q = a and Q = 1.
CLK--- L
I
I
Q == 1, Q = 0 : When J = 0, K = 1 and Q = 1, S = a and R = 1. According to
truth table of SR flip-flop it is a reset state and the output Q will be O.
0---+-- I
I
Theiriputs} == o and K ;;:;l,ma-kes Q== O,i.e.,resefsfate.

I
I
Q I
(Positive edge)
triggered clock I
I
Case 4 : J= K=1
I
I
I Q == 0, Q = 1 : When J = K = 1 and Q = 0, S = 1 and R = O. According to truth
Q I
(Negative edge) ---+ I

.....l._
I
! _ table of SR flip-flop it is a set state and the output Q will be 1.
triggered clock I
Q = 1, Q = 0 : When J =, K = 1 and Q = 1, S = a and R = 1. According to truth
r
I
p~e
table of SR flip-flop it is a reset state and the output Q will be O.
----'-
triggered clock
ITheinpufJ=K= I, toggles the flip-flop output. I
for master-slave e Fig. 4.4.18 shows the logic symbol, truth table and timing diagram of positive edge
Fig. 4.4.16 (a)
triggered JK flip-flop.
I!II JK Flip-E P
e The ncertainty in the state of an SR

flip-flop when S = R = 1 can be eliminated Q P--.--+-.... Q
J
by converting it into a JK flip-flop.
JlSL
e The data inputs are J and K which are K --....~-........ CP
r---
ANDed with Q and Q, respectively, to P -...........__t-Q
obtain Sand R inputs, as shown in the
Fig. 4.4.17. Thus, S = J-Q and R = K·Q. Fig. 4.4.17 JK ru -flop using SR
lp-flop
TECHNICAL PUBLlCATlONS"'- An up thrust for knowledge

om JK Flip-Flop using N ates.,----. 3 /f· f!-c(U' ~.

J Q
• T~.4~····_·~~s the m ified circuit of JK flip~which has only NAND
CP gates.
~A
K Q
\ -e~(
Q
J--L-_
=JLJL
Fig. 4.4.18 (b) gic symbol
Fig. 4.4.18 ~ K--..r--
CP
JK
On 00 01 11 10
o S =JQ :. S = J Q
R=KQ :. R = KQ
S=JQ R= KQ
Fig. 4.4.21 JK flip-flop using NAND gates
On + 1 =On J + on K = n+ K n o
Fig. 4.4.18 (d Char teristics equation • In JK flip-flop, en J = K = 1, the output toggles (output changes either from a
to 1 or from 1 to a .
CP • Consider that initially Q = a and J = K = 1. After a time interval M equal to the
propagation delay through two NAND gates in series, the output will change to
0 Q = 1 and after another time interval of M the output will change back to Q = O.
J :1 :1
: :1 This toggling will continue until the flip-flop is enabled and J = K = 1. At the end
:1 :1 of clock pulse the flip-flop is disabled and the value of Q is uncertain. This
: ,
K--.1 I :0 i0 I :1 situation is referred to as the race-around condition. This is illustrated in

Fig. 4.4.22.
Q
(toggle)
.........-;.-:..._.J (toggle)
elK
s for positive edge triggered JK flip-flop
Example 4.4.3 Construct a clockedJKflip--flop W h'h' .
IC IS tnggered at the positive edge of the
J--.;-......
clock pulsefrom a clocked SR flip-flop consisting of NOR gates.

Solution: K~
Q---i
Propagation delay
L\t
Fig. 4.4.22 Input and output waveforms for clocked JK flip-flop
Edge
detector • This condition exists when t p 2 M. Thus by keeping t p < M we can avoid race
circuit
around condition.
J • We can keep t p < M by keeping the duration of edge less than M.
• A more practical method for overcoming this difficulty is the use of the
Fig. 4.4.20
Master-Slave (MS) configuration.
TECHNICAL PUBLICATIONS"'. An up thrust for knowledge TECHNICAL PUBLICATIONS"'. An up thrust for knowledge
4 - 18
D' . I Principles and ssy\~s~te~m~D.:essJig~n~
~~
~~~
4 - 19 --=-~ _
Realize a JKflipflop using only NOR gates.
Solution: • Fig. 4.4.25 illustrates the operation of the master-slave flip-flop.
Replacing AND by
CP~ L
bubbled NOR
... K
Q
Cp JLfL S --+--i~,- - " ' ; ' - - - + - - ; - - - T

J<r-_t-Q R-~--i l~-~--;
Mastero~
Slave au puf:
ggered Master Slave Master Slave Master Slave
flip-flop- sets sets resets resets NC NC
Fig. 4.4.25 Input and output waveforms for master-slave flip-flop
lID Master-Slave D Flip-Flop

---. - ~
Fig. 4.4.23 Negative edge triggered JK flip-flop using only NOR gates
11II ~ R Flip-Flop • Fig. 4.4.26 shows the block
diagram of master-slave D 0 Q 0 Q
• A ~ster-slave fli£=.t_fl_o~P_ _is flip-flop. It consists of
constru21ed
, from ~ flip-flops. clocked D flip-flop as a CLOCK Master Slave
~e
S Q t-------j S
circuit serves as a master and Q master and another
Master
the other as a slave, and the Slave clocked D flip-flop as a Q Q
R Q I-----I------t R
overall circuit is referred to as a rz. Q slave.
master-slave flip-flop. ll~ __ ~ Both the flip-flops are ~:, D fl" fl
~::~fl:~24 FIg. 4.~~~;;)
• . .
positive level triggered, Fig . 4.4.2 ock diagram of. master-slave Ip- op
• shows SR master-slave
but inverter connected at ' . . level
~f a ~L-fL42-flo£,_a slave, flir-=:Pop, .~n_~._~~Jnv~~!~-,-_

the clock input of the slave flip-flop forces it to tngger at the negative .
• It
h ositive edge of the clock pulse and the
• Both the flip-flops are positive level triggered, but inverter connected at the clock • D input is transferred to the master at t e p t the output Q of the slave
same 1S . c opied by the slave and therefore appears1 a
input of the slave flip-flop forces it to trigger at the negative level.
flip-flop at the negative going edge of the clock pu se.
• The output state of the master flip-flop is determined by the Sand R inputs at the
positive edge of the clock pulse. lID Master-Slave JK~~.i~~~I~_~
• The output state of the master is then transferred as an input to the slave flip-flop. F ~ way to build a JK master-slave flip-flop.
The slave flip-flop uses this input at the negative edge of the clock pulse to • 19... K fli fl as a slave.
determine its output state. .
• It consists a f c1ock e d JK flip-flop as a master and clocked J 1p- op
. fl
• The output of the master flip-flop is fed as an input to the slave flip- op.

e As shown in the T Flip-Flop

Fig. 4.4.27, clock signal is - J 0 J 0 I--
connected directly to the e T flip-flop is also known as 'Toggle flip-flop'.
ClK
master flip-flop, but it is Master Slave e The T flip-flop is a
,--~-~~_'-
m()~gic.a1iOilOf~t!:t~1~-~~iE-fl~P' ,
- - ---------,."------- - ----- --
connected through inverter - K Q K 0 I-- e As sho-wn in the Fig. 4.4.29, the T flip~ob~ed from a lKl!P-f!0f'_~
to the slave flip-flop.
t connecting
._.••· botJ:llDPll!?,] Cl!1cl J<. tQge_ther."
e The information present at
"'- ·__ ··___ -,-- -., -
the J and K inputs is J

transmitted to the output Fig. 4.4.27 Master-slav f ip-flop T
T J 0
of master flip-flop on the positive edge of the clock p se and it is held there until'
JK
the negative edge of the clock pulse occurs, after which it is allowed to pass CP flip-flap -
through to the output of slave flip-flop.
K 0
e When J = 1 and K = 0, the master sets on the positive clock. The high Y output of b-.....i--+-O
the master drives the J input of the slave, so at negative clock, slave sets, copying K
the action of the master.
e When J = 0 and K = 1, the master resets on the positive clock. The high Y output , Fig. 4.4.29 ~tes ,
of the master goes to the K input of the slave. Therefore, at the negative clock
slave resets, again copying the action of the master. e When T = 0, J = K = 0 and hen~is no change in the output. When T = 1,
e When J = 1 and K = 1, master toggles on the positive clock and slave then copies J=K = 1 and hence output toggles.
the output of master on the negative clock. e The Fig. 4.4.30 shows logic symbol, truth table and the characteristic equation for
e When J = K = 0, the output of master remains same at the positive clock. Thus the T flip-flop.
output of slave also remains same at the negative clock. The Fig. 4.4.28 shows the
truth table and symbol for master-slave JK flip-flop.
T o
PR CP
Qn+1
On (No change) J "I 0 :. 0n+1 =TOn+rc,

0 (Reset) ClK (a)LOg;C~ <, b) Trut able (e) ~tie equation
(Set) K "I Q Fig. 4.4.30
On (Toggle)
ClK
(b) Symbol
,
T o
T
ClK FF
T--i--- (t)
Fig. 4.4.31
TECHNICAL PUBLICATlONS"'- An up thrust tor knowledge TECHNICAL PUBLICATlONS"'- An up thrust for knowledge
4 - 27
Digital Principles and System Design 4 - 26 Digital Principles and System Design
t a d the K input can be either 0 and 1.

o
SR Flip-Flop the J input

must remam a an h en
nt state is a and is to change to 1. This can ~~p
0
. . e
• Table 4.5.2 (a) and (b) • 0 ---7 1 TransItIOn: The pres h 0 J = K = 1 (toggle cond1tIOn).
•
. -1 d K = a (set cond1tion) or w en
show the truth table and either when J - an ith I el for this transition to occur.
excitation tables for SR Thus J has to be 1, but K can be at el er ev n 0
, t t . 1 and is to change to O. This can happe

flip-flop, respectively. • 1 ---7 0 Transition : The present s a e 1S K _ 1 Thus K has to be 1 but J can be
r when J = -. ,
• There are four possible 1 0 either when J = 0 and K = 1 O
transitions from the (a~uth table (b) SR ex~~n table at either level. 1 the K input must
present state to the next V' Table 4.5.2 ~ ..
• 1 ---7 1 TranSItIon .
. Wh both present state and next are ,
en .
state. hil th J input can be 0 or 1.
remain at 0 W l e e , diti ns than the
fli -fl has more don t care con 110
• For each transition, the required input condition is derived from the information • The excitation table for JK Ip op
available in the truth table. excitation table for RS flip-flop. . Th
fore the combinational
11 simplify the function-
ere ,
• The don't care terms usua y l'kely to be simpler than
0
circuits using JK flip-flops for the input functIOns are 1
• 0 ---7 0 Transition: The present state of the flip-flop is 0 and is to remain 0 when those using RS flip-flops.
a clock pulse is applied. Looking at truth table of SR flip-flop we can understand
that, this can happen either when R = S = 0 (no-change condition) or when R = 1
BIll 0 Flip-Flop
• The Table 4.5.4 (a) and (b) show the
and S = O. Thus, S has to be at 0, but R can be at either level. The table indicates
truth table and excitation· table for
this with a "0" under S and an "X" (don't care) under R.
D flip-flop, respectively.
• 0 ---7 1 Transition : The present state is 0 and is to change to 1. This can happen • In D flip-flop, the next state is al~a~s
only when S = 1 and R = 0 (set condition). Therefore, S has to be 1 and R has to equal to the D input and it 1S
be 0 for this transition to occur.
mdepen d en t 0f the present state..
o
• 1---7 0 Transition: The present state is 1 and is to change to a O. This can happen Therefore, D must be a if Q n + 1 has to
only when S = 0 and R = 1 (reset condition). Therefore, S has to be 0 and R has to be 0, and 1 if Qn+ 1 has to be 1,
be 1 for this transition to occur. regardless of the value of Qn'
• 1 ---7 1 Transition : The present state is 1 and is to remain 1. This can happen
either when S = 1 and R = 0 (set condition) or when S = 0 and R = 0 (no change
BID T Flip-Flop
condition). Thus R has to be 0, but S can be at either level. The table indicates this • The Table 4.5.5 (a) ~nd (b) show the
with a "X" under Sand "0" under R. truth table and the excitation table for
T flip-flop, respectively,
JK Flip-Flop • When input T = 1, the state of the
• The truth table and excitation flip-flop is complemented; when T =. 0,
table for JK flip-flop are shown the state of the flip-flop remams (a) T truth table (b) T excitation table
in Table 4.5.3 (a) and (b) a ---7 0 and
unchanged. Therefore, for
respectively. 1 ---7 1 transitions T must be a and for Table 4.5.5
• 0 ---7 0 Transition : When both o ---7 1 and 1---70 transitions T must

present state and next state are 0, (a) JK truth table (b) JK excitation taLle be 1.
Table 4.5.3
BLICATIONS"' - An up thrust for knowledge
TECHNIC AL PU
TECHNICAL PUBLICA nONS'"- An up thrust for knowledge
F
Solution : From F 4 5 2
---
Digital Principles and System Design .4 - 29 Sequential Circuits - Flip-Flops
-
Ig. " we can write truth table for JK flip flop as shown below. 1. Give the characteristic equation and state diagram of JK flip-flop.
For 0(t+1)
JK
Q 00 01 11 10 2. Give the excitation table for JKflip-flop. _~
o
3. Obtain the excitation table of D flip-flop. ~MDD
4. Give the state diagram of JK flip-flop. mm
-
5. What is excitation table ?
:.6(1+1) =J6 + KQ
Fig. 4.5.2 6. Give state diagram of JK flip-flop.
7. Draw state diagram of SR flip-flop. . J _an
8. Draw the truth table and-excitation table of T flip-flop. ~
9. State the characteristics equations of various flip-flops.
Realization of One Flip-Flop using Other Flip-Flop

Solution:
I.\!II~-
State Table • It is possible to convert one flip-flop into another flip-flop with some 'additional
Excitation stable
to state machine gates or simply doing some extra connection.
. . ~~~.~~~~_~.~ flip-flop "
• "~epresents relationship
between input, output • A truth -tabi~'-fu~t'-i~t~'"
and flip-flop states of a the required inputs
state machine. conditions for a given
change of state is known
• The
• It consists of three as excitation table.
sections labeled present
state, next state and • It consists of two
output. sections.
• The present state • First section specifies the

desigrates the state of change of state and Qn
flip-flops before the second section specifies
occurrencs of a clock the required inputs for 0
-ILlY.}) 0 X
pulse. The next state is a
state . of the flip-flops
after the application of a
specified change of state.
o f-l",'IJ1QJ10
\
0 1
clock pulse and the ----"
output section gives the \ 0 1 0
val7les of the output
variables during the
state. 1 X 0
Used in the design process Table 4.6.1

of a state machine.
TECHNICAL PUBLICATIONS"'· An up thrust for knowteaao

TECHNICAL PUBLICATIONS"". An up thrust for knowledge
p c
4 - 30
Sequential Circuits - Flip-Flop~ Digital p_{_in_c_ip_le_s_a_nd_S_ys_te_m_D_e_si_gn 4 - 31 ~--..:_
K-map simplification Logic diagram -----. ----- SR Flip-Flop to T Flip-Flop

ForS ForR III The excitation table for ave conversion is a
oQ n 0 o
o
8=0) R=D
~
Fig. 4.6.1
SR Flip-Flop to JK Flip-EI
•- '..' ~-~"-~ry;"/""""-L""'"
M The excItatIon table for above on
~~
Table 4.6.3
K-map simplification Logic diagram
~ f~D rn fi>--A/
\. (rjJJA:bi ft ForS For R
J ( Qn
r Qn
~~ s r
'./- 0 1 1
0
0 o 0 0 X 0 X 0
\l "<, ~----i-~':}-
f
Of
~- r-,
q. X r
~~
,I
o o " 1 1 0 1 0 1
, X 0
8 = rOn R =r o,
I
~
0 X
Fig. 4.6.5 Fig. 4.6.6 ~iP-fIOP conversion
"'j'4-()O -0 If we apply clock pulses to the circuit, the circuit output will toggle from a to 1 and
1 to O. Thus, we can build J-bit counter using SR flip-flop by converting it to T flip-flop.
1 o 1 X o Prepare the truth table
o for the circuit of Fig. 4.6.7 and
8
Q
show that it acts as. aT-type r
8R
flipflop. CP Flip-flop
1---- Q
R
Logic diagram
ForR Fig. 4.6.7
Solution: For SR flip-flop,

J
K S+RQ n ... Characteristics equation

= S+ S Q n .: R = S
JK flip-flop
Fig. 4.6.3
Fig. 4.6.4 SR to JK f1ip-f!ip conversion S (1 + Q n ) = S
TECHNICAL PUBLICA TlONS"'. An up thrust for knowledge

4 - 32
Sequential Circuits - Flip-Flops 4 - 33 Sequentia/~Circuits - Flip-Flops
We have, S = Qn $ T
K-map simplification
Qn + 1 = Qn $ T
- - ForJ A
TQn +T Q n Q
'" Characteristic equation of T flip-flop T n. 0 1 T
o X 0
o T flip-flop
Fig. 4.6.8 F·Ig.469
. . JK to T flip-flop conversion
1
JK Flip-Flop to D Flip-Flop
1
• The excitation table for above c . 1is as shown in the Table 4.6.6.
version
o
o
Next state
Table 4.6.4 Truth table for the given circuit
• Looking 2.~
column 1 and column 5 of the Table 4.6.4 we can conclude that when
T = 0, the output does not change and when T = 1, the output toggles. Thus, the
given circuit acts as a T flip-flop. This is another way of implementing T flip-flop
using SR flip-flop.
_ JK FIiP.F~.FIOP Table 4.6.6

\ \ K-map simplification Logic diagram
• The excitation table for ab conversion is . Table 4.6.5. ForJ ForK
_
Qn
DQ n 0 D
Input I D 0 1 1
T _~re~~~~~ ~::~'~I ~~F:='S o 0 X 0 X 1..1
o
"" '" ,-- '" ,,' - ,,-- - - - , - " , "'. -,{
'-- -""'-., ~---,-_." ~"
.. "", '- --- ---"'---
1 X 0
o 0 lox J=D K=D

o I
1 1
I. X o
. .4.6. 11 JK to D flip-flop conversion
Fig
Table 4.6.5
TECHNICAL PUBLICATIONS"'. An up thrust for knOwledge

TECHNICAL PUBLICATlONS'''- An up thrust for knowledge
m
ps -
4 - 34
Sequential Circuits - Flip-Flops Sequential Circuits - Flip-Flops
- 35
Logic diagram
T Flip-Flop to DE' -Flop
Q ForD
T n
0 1 for above conversion is as shown in the Table 4.6.9.
0 0 1 T
Present state Next state Flip-flop input
1 1 0 T
Fig. 4.6.12
Fig. 4.6.13 0 to T flip-flop conversion
o = TQn +TQn = TEB Q
n
Analyze the circuit and prove that it. is equioalent to T flip-flop. Table 4.6.9
Solution: To analyze the circuit K-map simplification Logic diagram
means to derive the truth table for it.
ForT
We have, D = Input EB Q n
Input ---11 o Output Q
n
0 0 1
ClK 0 0 1 o
1 1 0
Fig. 4.6.14
Fig. 4.6.15 11
Fig. 4.6.16 T to( 0 flip-flop conversion
Ifill JK Flip-Flop 0 SR Flip-Flop ,!-iIO(11 fr
When input is 0
The excitatio able for above conversion ..! IS as hown in Table 4.6.10. ~ ('f\
I/<_[T
/ P p-flop t: yO (
j output does not

When input is 1
Chang~
(
/.i.
.)
''--7
sta pu
o o j output toggles x
o
Table 4.6.8 Truth table for given circuit
• In the above circuit, output does not change when input is a and it toggles when
input is 1. This is the characteristics of T flip-flop. Hence, the given circuit is
T flip-flop constructed using 0 flip-flop.
Table 4.6.10 Excitation table for JK to SR conversion
TECHNICAL PUBLICA TlONS'". An up thrust for knowledge

4 - 36 Sequential Circuits - Flip-Flops , /'tal Principles and System Design 4 - 37 Sequential Circuits - Flip-Flops
D/9
Logic diagram
ForJ For K
T Flip-Flop SR Flip-Flop
Q Q
n n
SR 0 1 0 1
The excitatio table for conversion of T FF into an SR FF is as shown in the
SR
00 0
Table 4.6.12. "
X 00 X 0 s J Q
Present state Flip-flop input
01 0 X 01 X 1
Qn T
11 X X 11 X R
~" K Q 0 0
CP 1 0
10 1 X 10 0 X
0 0
J=S K=R 1 1
Fig. 4.6.17 Fig. 4.6.18 JK to SR flip-flop
conversion 0 1
1 0
o Flip-FI to SR Flip-Flop
0 x
The excit on table for above conversion is as shown in the Table 4.6.11. 1 x
Table 4.6.12 Excitation table for T to SR conversion
resent state Flip-flop input
Qn D
0 0 For D
1 1
0 0
1 0
0 1
1 1
0 X
1 X (a)
Fig. 4.6.21
Table 4.6.11 Excitation table for 0 to SR conversion
K-map simplification Logic diagram II1II 0 FI' - lop to JK Flip-Flop
The exc tation table for conversion of D flip-flop to JK flip-flop:
For D s Present state Flip-flop input
ROn
S 00 01 11 10 D
o o o
R 1
/ o
0= R On + S o
1
CP SR Flip-Flop
1
Fig. 4.6.19 Fig. 4.6.20 0 to SR flip-flop conversion
1
1 o
TECHNICAL PUBLICATlONS""- An up thrust for knowledge
4 - 38
ForD
------.:...~--~~~~
Logic diagram --
1. Convert JK flip-flop to D flip-flop.

I---r-"-+_ K 0 2. Convert D flip-flop into T flip-flop.
JO
3. Convert JK flip-flop to T flip-flop.
4. Convert a SR flip-flop into a D flip-flop.
5. Convert a T-FF into an S-R FF. Draw the circuit.
6. How will you convert a D flip-flop into JKflip-flop ?
(a) JK flip-flop
7. Convert SR flip-flop into JKflip-flop.
(b)
~-'-Eig,4.~~~ S. Convert SR flip-flop into T flip-flop.
. Oms/ruet a JK flip-flop using ~u[tiP[exerand an inverter,
pplications of Flip-Flops
---------------
Solution : The excitation table for above conversion is as shown in the Table 4.6.13. Some of the important applications of flip-flops are :
• .~ be used as a memory element.
Present state Flip-flop in
~-' //
j / f t can be used to eliminate key debounce.
o
o ~ as a basic ~()~uential circuits such as counters and
o registers. _
1 ~
1
• ~n be used as a delay element.
o o
1
o Bounce Elimination Switch
o
.~r·
1
1 interfacing
~ys
1
o to the
1
1 digital systems, v
o usually push
Table 4.6.13 button keys are o--A
Implementation table
~B
Implementation use9J
Do D1 D2
J • Push button v-=- v f---...,
0
J CD
keys when
pressed bounces
I / -:
:+-_ _-L- __ .I-I-'-~
J -'--1 Do o
J J o ~---I---1 D a few times,
1 Fig. 4.7.1 Effect of key debounce
D2 ~U~ Y 1 - - - - -..... D 01---- closing and
D3 opening the contacts before providing a steady reading, as shown in the Fig. 4.7.1.
• (feading taken during bouncing period may be faulty. This problem is known as
~ey debounce)
• The problem of key debounce is undesirable and it must be avoided.
Fig. 4.6.23
• One way to avoid key debounce problem is to use SR latch.
TECHNICAL PUBLICATlONS"'_ An up thrust for knOWledge
4 - 40
Sequential Circuits - Flip-Flops Digital Principles and System Design 4 - 41 Sequential Circuits - Flip-Flops
::-:------- .
• The circuit used to avoid k b
ey ounce with SR latch is called a switch ----------Difu~;rti.~~;;;;;jm;;::fu;;~di~;-------------iiiiil
a. 3 Differentiate between flip-flop and latch.
debouncer. or contact
Ans. :
• The Fig. 4.7.2 shows the switch debouncer circuit and its f
wave arms.
• When key is at position A, the output VA
Latch
of SR latch is logic I, and when key is A simple latch is the basis for flip-flop
at position B, the output of SR latch is V
logic O. Latch is level triggered either positive
level or negative level triggered.
• When key is in between A and B, SR
inputs are 00 and hence output does The latch output responds to inputs, until
not change, preventing debouncing of active level is maintained at the enable
V in ut.
key output.
• We can say that the output does not o I
a.4 Give the excitation table for JK flip-flop. (Refer section 4.5.3.2)
I
change during transition I a.5 Obtain the excitation table of D and JK flip-flops.
period, I
tr----
I
eliminating key debounce. I (Refer sections 4.5.3.3 and 4.5.3.2)
I
a.6 Give the meaning for edge triggering in flip-flops.
:1
, - - -......- --18 Q
A
Ans. : In the edge triggering, the output responds to the changes in the input only at
.. t
the positive or negative edge of the clock pulse at the clock input. There are two types
8
of edge triggering.
• Positive edge triggering : Here, the output responds to the changes in the
V
I
-=-
Fig. 4.7.2 (a) S;"itch debouncer

:/
Fig. 4.7.2 Waveforms of switch debouncer
.. t •
input only at the positive edge of the clock pulse at the clock input.
Negative edge triggering: Here, the output responds to the changes in the
input only at the negative edge of the clock pulse at the clock input.
Q.7 If the input frequency of a T FF is 1600 kHz, what will be the output
frequency? Give reason for your answer.
Ans. : 800 kHz, because it toggles at every clock pulse.
Q.8 Convert JK FF to D FF. (Refer section 4.6.5)

1. Explain the needfor key debounce circuit.
Q.9 Define a sequential logic circuit. Give an example.
2. What are the advantages of debounce circuit ?
Ans. : The circuits in which the output variables depend not only on the present input
3. Explain the working principle of switch debounce logic. but they also depend upon the past history of these input variables are known as
sequential logic circuits. Flip-flops, counters, registers are the examples of sequential
logic circuit.
Q.lO Draw the logic circuit of a clocked JK flip-flop. (Refer section 4.4.5) _
Q.1 Give the excitation table of SR flip-flop. (Refer section 4.5.3.1) Q.11 Differentiate between combinational and sequential circuits.
Q.2 With reference to a JK flip-flop, what is racing ? _ (Refer section 4.1.1) _MrS~_
Ans.: In a level triggered J-K flip-flop when J and K a r e ' . Q.12 What are synchronous sequential circuits ? ~
toggles continuously..ThIs condition is c~lled a race around c~~~~t~~~' then the output Ans. : Synchronous sequential circuits are those in which signals can affect the memory
elements only at discrete instants of time. Clocked flip-flops are examples of I
synchronous sequential circuits.
TECHNICAL PUBLICA TlONS"'- An up thrust for knowledge
--,ap 5-:: Analysis & Design of Clocked Sequential Circuits
. ·tal Principles & System Design
Digi ..
....---- . 1 epresents a conditIon
Digital Principles & System Design 5-2 Analysis & Design of Clocked Sequential Circuits
Next state: The status of all state variables, at some time, t + , r
~~~. I
Introduction ca h us or clocked sequential circuits are represented by two mode s.
The sync rona Th tp t depends only on the present state of the flip-flops.
• Moore model : e au u . 1 ()
• Synchronous sequential circuits are further classified depending on the timing of d on both the present state of the flip-f op s
their signals : Synchronous sequential circuits and asynchronous sequential • Mealy model : The output d epen s .
circuits. and on the input(s).
• In synchronous sequential circuits, signals can affect the memory elements only at
Moore Model
discrete instants of time.
• In asynchronous sequential circuits change in input signals can affect memory • When the output of X
element at any instant of time. the sequential CP
~~
circuit
1 y.
Synchronous-seqdential circuits only~
~~_the--
flip-flop,_ the Fig. 5.2.1 Example of Moore model
sequential circuit is
referred to as Moore model. . . .
,.-----~' d I F' 5 2 1 shows a sequentIal CircUlt
pIe of Moore mo e. . ig. .. d
• Let us see one exam. d AND ate. The circuit has one input X an
which consists of two JK flip-flops an g
one output Y.
--.
. bles
Excitation vana
Output
-1
f ---
Output
Input { Next .. decClder jVariables
-
Table 5.1.1 Comparison between synchronous and asynchronous sequential circuits variables I.,C'....... ,.
-
state (combinational
decoder circuit)
1. Distinguish between synchronous and asynchronous sequential circuits.

~
r State variables
m Clocked Sequential Circuits Fig. 5.2.2 Moore circuit model with an output decoder
. . . ut X is used to determine the inputs of the

• In synchronous or clocked sequential circuits, clocked flip-flops are used as • As shown m the Fig. 5.2.1, m p. h tp t The output is derived using only
memory elements, which change their individual states in synchronism with the I' t used to determme t e au ur.
flip-flops. t is no . -fl s or combination of it (in this case Y = Q A Q B)'
periodic clock signal. present states of the flip op h matic as
• Therefore, the change in states of flip-flops and change in state of the entire circuit the Moore model can be represented with its block sc e
• In genera1 farm
occurs at the transition of the clock signal. shown in Fig. 5.2.2.
• The states of the output of the flip-flop in the sequential circuit gives the state of (
the sequential circuit.
Present state: The status of all state variables, at some time t, before the next clock
edge, represents condition called present state. TECHNICAL PUBLICATIONS"'. An up thrust for knowledge

Analysis & Design of Clocked Sequential Circuits
5-5
. . aI Principles & System Design
Digital Principles & System Design 5-4 Analysis & Design of Clocked Sequential Circuits {)/gd
--------------=------------ ~ ./, dl
" Circuit Mo e s
Mealy Model /'
• When the output of the sequential circuit ~~~I!Q.~_~m both~ the pr~£!lt~!Clt~~ of L . ~~_~~~._~~~e~ ...~----~.---.
flip-flop(s) and on the ipput(s), the sequential circuit is referred to as ¥ealy '~;~~~tput is a function of present state
model. ~ --., .~~y. ----~..--~..-_._.__.._._---_._.._...._.
,~
Input changes does not affect the
• Fig. 5.2.3 shows the sample Mealy model. As shown in the Fig. 5.2.3, the output of
...~~~!:. _ _ _ - .
the circuit is derived from the combination of present state of flip-flops and
Moore model requires more numbe.r of
input(s) of the circuit. states for implementing same function.
• Looking at Fig. 5.2.3, we can easily realize that, changes in the input within the Table 5.2.1
clock pulses can not affect the state of the flip-flop. However, they can affect the
output of the circuit. Representation of Sequential Circuits
1/0
State Diagram 010
x For Mealy circuit . .

• State diagram is a pictorial repre~ent~tion of
CP -+-I----....-----<lI> a behaviour of a sequential circUit. Pig. 5.2.5 010
010
o °81---, shows a state diagram.
The state is represented by the circle, and 1/0
y • the transition between states is indicated by
Fig. 5.2.5 State diagram for Mealy
directed lines connecting the circles. circuit
Fig. 5.2.3 Example of Mealy model
• A directed line connecting a circle with itself
• Due to this, if the input variations are not synchronized with the clock, the indicates that next state is same as present state. .
derived output will also not be synchronized with the clock and we get false . bl inside each circle identifies the state represented by the circle.
output (as it is a synchronous sequential circuit). • The state vana e t d by a symbol
d ith two binary numbers separa e
• The directed lines are labelle Wl iti is labelled first and the output
• The false outputs can be eliminated by allowing input to change only at the active ,I' The input value that causes the state transi ion 0
transition of the clock (in our example HIGH-to-LOW). · duri the present state is labelled
va 1ue urmg
• In general form the Mealy model can be represented with its block schematic as after the symbol ' I'.
shown in Fig. 5.2.4.
For Moore circuit .
circuit the directed lines
• In case a f Moore '
labelled with only one binary number
::;resenting the sta:~ of the input that
f--.- o
f--.-
Excitation causes the state transltion.
-c r-I-
variables Output Output o
decoder variables • The output state is indicated within the
Input { ---4'- koo
variables
Next circle, below the present state because
-.:.. .... state
Memory
output state depends only on present state
r:=;:
r
decoder
$tate variables
elements
-- and not on the input.

• Fig. 5.2.6 shows the state
di agram for 1
Fig. 5.2.6 State diagram for Moore
Moore circuit. circuit
Fig. 5.2.4 Mealy circuit model

TECHNiCAL PUBLICATIONS"'. An up thrust for knowledge
TECHNICAL PUBLICATlONS"'- An up thrust for knowledqe

Digital Principles & System Design
5-6 Analysis & Design of Clocked Sequential Circuits
r
f 5-7
Digital Principles & System Design Analysis & Design of Clocked Sequential Circuits
State Table
----•
II Rep~esent~tion of state machine using Assignment of values to state variables is called State assignment.
relatIOnshIp between input(s), present • Like state table transition table also represents relationship between input, output
state, next state and the output(s) in and flip-flop states. The Fig. 5.2.7 shows the transition table.
the tabular form is known as state Here, AB are the state variables. The AB = 00 represents one state, AB = 01
table. represents second state and so on.
II Table 5.2.2 (a) shows the state table
for the state diagram shown in
Fig. 5.2.5.
1. What is a state ?
• ~t represents relationship between
2. What is Moore machine ?
input, output and flip-flop states.
3. What is a Mealy machine? Give an example.
• It consists of three sections labeled
4. Compare Moore and Mealy circuits. . I I' •. I :
present state, next state and output.
5. What is transition table ?
• The present state designates the state
of flip-flops before the occurrence of a Analysis of Clocked Sequential Circuits
clock pulse.
• The next state is state of the flip-flop

after the application of a clock pulse,
I.
• The behaviour of a sequential network is eJ

determined from the inputs, the outputs, ex _+-+-_-L--"J-----;t-----f--~
and the output section gives the
values of the output varia . bl es c
and the states of its flip-flops. Of!
during the present state. II The analysis of sequential circuit consists of
obtaining a table or a diagram for the time
• Both the next state and output sections have tw
possible input conditions: X = 0 and X = 1. 0 columns representing two sequence of inputs, outputs and internal
states. -"-'=-..:+---;Q T 1----'
• In case of Moore circuit the output section has onIon . Consider the sequential circuit to be anal a XkfJ 0
. 1'1
r -~""'l
.»: I
not depend on input. The Table 5.2.2 (b) shows y e column smce output does lock
as shown in Fig. 5.3.1.
whose state diagram is shown in F' 526 the state table for Moore circuit L..----tQ
Ig. '" Let us see the steps to analyze the~~H
1.-_ _..1
Transition Table synchronous sequential circuit. Fig. 5.3.1
• A transition table takes the state table

t f one
s ep urther. The state diagram and state
table represent state using symbols or
names.
• In . the transiitiIOn table specific state
variable values are assigned to each state.
Fig. 5.3.2
Fig. 5.2.7
TECHNICAL PUBLICA n,
nONS - An up thrust for knowledge
F
«
5-8 Analysis & Design of Clocked Sequential Circuits
Principles & System Design 5-9 Analysis & Design of Clocked Sequential Circuits
3. Plot the next step map for each flip-flop
\ c
4. Plot the transition table _

~
{)~ ..
r~
5. Draw the state table . an d th e ou t p ut equations from the
Solution : 1. D ete r. mthe
m flip-flop
e . input equations;:. . ,
The transition table shown in Table 5.3.1 can be converted into state table as shown
uen~ C~-;>,ND /;;:b \:' e/ .r: (/o/~.
seq, r:-~<).
ymbols to binary codes are assigned. They are a
~~~,~,j,_~::",~
= 0, b = 1.
o f 0~~"./ _.. \( /''r-<." ~
: :: ~::
(2,,1,\ .'
6. Draw state diagram

~<Y010-'--0#_
~f f 1f~ t~: ~ A . '- '
r 2. Derive the transition equations,
0/0
The transition equations for JK flip-flops can be derived from the characteristic
equation of JK flip-flop as follows :
1/1 We know that for JK flip-flop

Q+ = JQ+KQ
~gram :. A+ = Q~ = JA QA +KAQA
= BA +(X+B) A
and JBQ B +KBQB
.
:;:: X Q, B +XE8 A QB.
= XB+XE8A·B
TECHNICAL PUBL/CATlONS"'_ An up thrust for knowledge

Digital Principles & System Design 5· 10 Analysis & Design of Clocked Sequential CirCuits"~
5 - 11 Analysis & Design of Clocked Sequential Circuits
. . I Principles & System Design
3. Plot . a next-state maps for each flip-flop. Dlgda
The next-state maps are :
+
ForA
o
00 0
+ 01 01 0 o
+
A = BA + (X + B) A 1---+--,1< B = XB + X G> A' B
10 10 0
11 0 1<.
o
_._.__ _.._ _. __.~ __ . .__ F.:ig. 5.3.4 (b) . --

1
4. Plot the transition table. Fig. 5.3.5
The transition table can be formed by combinin9!he. above two maps. The Table 5.3.3
shows the transition table. Q./)"" ,. r-'.
Solution:
i) Logic diagram
A -,---r-.. . .
X
By assigning a = 0 0, b = 01, c = 10
X---~ "A-"'-----
and d = 11 we can write state table
B----lL---'"
from the transition table as shown.
6. Draw state diagram
From the state table we can draw
state diagram as shown in Fig. 5.3.5
Table 5.3.4
ClK --------~------------'
~
X
--> V=(A+S)'
Fig. 5.3.6 (a)

TECHNICAL PUBLICATIONS""· An up thrust for knowledge

5 - 12 Analysis & Design of Clocked Sequential CircUitl;j
, 'tal Principles & System Design 5 - 13 Analysis & Design of Clocked Sequential Circuits
ii) State table ------ ..---
DI91
A sequential circuit with two D flip-flops A and B, one input x, and one
Step 1: Plot the next-state map for each flip-flop. output z is specified by thefollowing next state and output equations :
ForA+ A(t + 1) = A'+B, B(t + 1) = B'x, Z = A + B', (
A~/. . ~. . ... ,.'....\

1) Draw the logic diagram of the circuit
t"~I( . . X 0 1 X
~.
AB AB
0 1 2) Derive the state table
00 0 0 00 0 1 3) Draw the state diagram 0 th cfl.P--"/. ~
01 Solution:
0 1 o1 0 1
A+ == AX + BX
10 0 1 10
1. Logic Diagram
0 0
11 0 1 11 0 0
Fig. 5.3.6 (b)

Step 2: Plot the transition table.
Next state
X=o X=l
A +, B+ A+ B+
CLOCK ----..---------'--~
0 O. 0 1
Fig. 5.3.8
0 0 1 1 2. State Table
0 0 1 0 Step 1 : Plot the next-state map for each flip-flop.
0 0 1 0 ForA+ ForB+
X X
Step 3: Draw the state table. AB 0 1 AB 0 1
!inState diagram
00 1 1 00 0 1
By assigning a = 00, b = 01, c = 10 and d
0/0
we can write state table from the transition Ie. 01 1 1 01 0 0
+ - + -
A == A+B B == BX
10 0 0 10 0 1
Next state 11 1 1 11 0 0
X=o X=l Step 2 : Plot the transition table

a b
a
Next state
d
a c X=o X=l
a c
1/0
ig. 5.3.7
1 o 1 1
TECHNICAL PUBLiCATIONS. An up thrust for knowledge

TECHNICAL PUBLiCATIONS"', An up thrust for knowledge
•
J '

Digital Principles & System Design 5 - 20 Analysis & Design of Clocked Sequential Circuits 't I principles & System Design
~
x
4. Determine the number of flip-flops needed and assign a letter symbol to
B each.
5. Choose the type of flip-flop to be used.
6. From the state table, derive the circuit excitation and output tables.
7. Using the K-map or any other simplification method, derive the circuit output
X
B functions and the flip-flop input functions.
8. Draw the logic diagram.
~=E)--r- State Reductio

Fig. 5.3.15 Example of a Mealy model
• The state eduction technique basically avoids
the' roduction of redundant states.
• The reduction in redundant states reduce the
number of required flip-flops and logic gates,
reducing the cost of the final circuit.
• The two states are said to be redundant or
x--' .J
x equivalent, if every possible set of inputs
generate exactly same output and same next
CP""', ---.__----------...J state.
Fig. 5.4.1 State diagram
• When two states are equivalent, one of the
Fig. 5.3.16
can be removed without altering the
input-output relationship.
1. Explain the various steps in the analysis of synchronous sequential circuits with suitable example. Example
• We start with a sequential circuit whose specification is given in the state diagram
~
of Fig. 5.4.1.
III Design of Clocked Sequential Circuits Step 1: Determine the state table forgiven state diagram.
•
Steps for design of clocked sequential circuits
. Table 5.4.1 shows the state table for given state diagram.
• The recommended steps for the design of a clocked synchronous sequential circuit
are as follows :
1. It is necessary to first obtain the state table from the given circuit information
such as a state diagram, a timing-diagram, or other pertinent information.
2. The number of states may be reduced by state reduction technique if the
sequential circuit can be categorized by input-output relationships independent
of the number of states.
Table 5.4.1 State table
3. Assign binary values to each state in the state table, i.e, state assignment.
---------------~-------
TECHNICAL PUBLICATIONS'''- An up thrust for knowledge
Digital Principles & System Design 5 - 22 Analysis & Design of Clocked Sequential Circuits . I principles & System Design 5 - 23 Analysis & Design of Clocked Sequential Circuits
~
Step 2: Find equivalent states.
solution:
., Looking at the state table for two present states that go to the same next state and 1 . Find equivalent states. The
step ' . . 'E
have the same output for both input combinations, we can easily find that states c T ble 5.4.3 shows the eqUlvalent
Q)
~rn
and e are equivalent. at s in the given state table. The . - Q)
:J .....
sta e 0".l9
Wrn
., This is because, c and e both states go to states c and d and have outputs of 0 and A and C, and states Band E
stateS
1 for X = 0 and X = 1, respectively. Therefore, state e can be removed and gen
erate exactly same output and
replaced by c. arne next state. Hence, state A and
~ are equivalent and similarly states Table 5.4.3 Equivalent states
., The final reduced table is shown in Table 5.4.2. The state diagram for the reduced
13 and Eare equivalent.
table consists of only four states and is shown in Fig. 5.4.2.
step 2 : 'Replace redundant states with equivalent states.
:. Replace C by A and replace E by B, and remove states C and E.
1/0 NoW, there are no equivalent states and hence Table 5.4.3 (a) shows the minimized
state table.
1/1
Fig. 5.4.2 Reduced state diagram

Table 5.4.3 (a) Minimized state table
TECHNICAL PUBLICATIONS'"· An up thrust for knowledge TECHNICAL PUBLICATIONS'''· An up thrust for knowledge
•
r
I
i
Rule 1: States having the same NEXT

STATES for a given input condition
5 - 34
should have assignments which can

be grouped into logically adjacent
cells in a K-map.
• Fig. 5.4.8 shows the example for Rule 1.
As shown in the Fig. 5.4.8, there are four
states whose next state is same. Thus Fig. 5.4.8 Example of using Rule 1
states assignments for these states are
100, 101, 110 and 111 which can be grouped into logically adjacent cells in a
K-map.
Rule 2: States that are the NEXT
STATES of a single state should
have assignment which can be
grouped into logically adjacent
cells in a K-map.
Solution : The state table for
• Fig. 5.4.9 shows the example for
ci~p)
the state diagram shown in
Rule 2. As shown in the Fig. 5.4.9,
Fig. 5.4.10 is as given in
for state 000, there are four next
Fig. 5.4.9 Example of using Rule 2 Table 5.4.13.
states. These states are assigned as
As seen from the state
100, 101, 110 and 111 so that they
can be grouped into logically table there are no equivalent
states. Therefore, no reduction
adjacent cells in a K-map and table
shows the state table with assigned is the state diagram. The e
states. table shows that circuit goes
through four states, therefore
we require 2 flip-flops
(number of states = z'". ,Table 5.4.13 A
Table 5.4.12 State table with assigned states where m = number of 11 'pfl~r <.
flip-flops). Since two flip-flops are required first is denoted as p and second is dknoted
Choice of Flip-Flops and Derivation of Next State and Output as B. <!' It
r E' e/(I.A..(1 fA
f(\...,,- I --)
.H " G1 rY"()I'AH'wL-c6' ~.() "',-

• The most straightforward choice is to use D flip-flops, because in this case the 1. Design using D flip-flops I ~<-- ('" »: vI'"
values of next state are simply clocked into the flip-flops to become the new
As mentioned earlier, for D flip-flops next statel are nothing but the new present
values of present state.
states. Thus, we can directly use next states to ~~mine the flip-flop input with the
• For other types of flip-flops, such as JK, T and RS the relationship between the help of K-map simplification. ~ i/I/1~~: ~~"
next-state variable and inputs to a flip-flop is not as straightforward as D flip-flop.
F~r othe~ types of flip-flops we have to refer excitation table of flip-flop to find
pr-VC-0
4 .
flip-flop inputs. This is illustrated in the following example.
--------------..,------------------
t_-....- _
5 - 36 Analy"s & Des;gn of Clockad Saquant;., C;nMts r O;g;tat Princ;pJes & SysJem Des;gn
For flip . flop A For flip - flop B

The first row of circuit
For output
excitation table shows that
o X there is no change in the state
AB
0 1
17 for both flip-flops. The
00 9/ 1
transition from 0 ~ 0 for T
.of 0 0 flip-flop requires input T to be
11
~ at logic O. The second row
11 1 0
shoWS that flip-flop A has
10 1
ibm:!
0 transition 0 ~ 1. It requires
the input TA to be at logic 1. It
Fi9 . 5.4.1t _
requires the input TA to be at
= ABX+ABX + ABX + ' 8 X and logic 1. Similarly, we can find
'- - -
= ABX+ABX inputs for each flip-flop for
= A8X+AX Table 5.4.15 Circuit excitation table
each row in the table by
With these flip-flop input function and circuit output function we can draw the logic referring present state, next state and excitation table.
diagram as follows Let us use K-map simplification to determine the flip-flop input functions and circuit
A--r--....
B l--..,
output functions.
X--L,._"
A--.r--.... K-map simplificaf
B
X--L_", B
X---L._" X
y AB 0 1
A--.r--.....
B A 00 0 o
X--L_" X---<-__
A 01 01
B
X--L_"
11 11
A--.r-,...
B l---..., ie 10
X----a....~",
B (a) For flip-flop A (b) For fliP-f'o19~ (c) For output
A
B
X--L._"
1Pc Fig. 5.4.13 -:
Therefore, input function for TA = BX + BX,
Fig. 5.4.12 Logic diagram of given sequential circuit using 0 flip-flop
TB = AB + BX + AXkaRd--~
2. Design U S i n ~
Circuit output function
/ Using the excitation table for T flip-flop
shown in Table 5.4.14 we can determine
the excitation table for the given circuit as
shown in Table 5.4.15.

TECHNICAL PUBLICATIONS'"· An,Up thrust for knowledge
D
5- 38 Analysis & Design of Clocked Sequential Circuits
With these flip-flop input functions and circuit output function we can draw the logic
diagram as follows :
r
,
,r
DigitalPrind.le, & S,s/em Design
----- 5 - 39
determine the flip-flop input functions and circuit output functions.

A K.map simplification
B B
x B AB
X
0 1 AB
X
0 1
B x 00 x 0 00 0 .0
X
A
01 0 X 01 X 0
X
11 0 0 11
10
cp-----r------- ---.J
(a) / ' .(~)~~~
A Output (Y)
B Therefore input function for RA = ABX + ABX
x - - --
. . (b) / . SA = ABX+ABX
~~JI~.iaglram. of given sequential circuit using T flip-flops
Fig.
RB = AB + BX
3. Design us~~s fIiP-fl~)-?Lrf \ ~ ~
v SB = ABX and,
Using the excitation table for RS hip-flo~ - --
shown in Table 5.4.16 we can determine the Circuit output function = AX + A B X
excitation table for the given circuit as shown With these flip-flop input functions and circuit output function we can draw the logic
in Table 5.4.17.
diagram as follows :
A
Table 5.4.16 Excitation table for RS flip-flop B
X--L.._"
The first row of circuit A-..r--.....
B
excitation table shows that X-"""L-_"
there is no change in the
state for both flip-flops. The
transition from 0 ~ 0 for RS
flip-flop requires inputs R
and S to be X and 0,
respectively. Similarly, we A
can determine inputs for X
Output (Y)
each flip-flop for each row A-..r-~ .....
B
in the table by referring X-"'L-_
present state, next state and
Fig. 5.4.16 Logic diagram of given sequential circuit using RS flip-flop
excitation table. Let us use
K-map simplification to
Table 5.4.17
TECHNfCAL PUBLICATIONS'"_ An up thrust for knowledge
TECHNICAL PUBLiCATIONS'" - An up thrust for knowledge
1IIttt _
4. Design using JK flip-flops

Using the excitation table for JK flip-flop shown in Table 5.4.18 we can determine the
r
I
Digital Principles & System Design 5 - 41
KB = A+X
Analysis & Design of Clocked Sequential C~
excitation table for the given circuit as shown in Table 5.4.19. Circuit output function = AX + A BX
A
S X
Flip-flop inputs
X
~'~~~--~"--~~'---~-----
B
JA KA J B x A
X
0 X 0
1 X 0 A
X
1 X X A-""--~ -......
Output (Y)
x-
B _
0 X X
Fig. 5.4.18 Logic diagram of given sequential circuit using JK flip-flop
X 0 0
ntial circuit using RS flip flops for the state
X 1 1
mber of flip flops.
X 1 X
JK flip-flop X 0 X
Table 5.4.19
The first row of circuit excitation table shows that there is no change in the state for
both flip-flops. The transition from a ~ a for JK flip-flop requires inputs J and K to be
a and X, respectively. Similarly, we can determine inputs for each flip-flop for each row
in the table by referring present state, next state and excitation table. Let us use K-map
simplification to determine the flip-flop input functions and circuit output functions.
x
AS _ _-
DO
01 .... d
Solution: From example 5.4.2 we have rrururruze
11 state table for given problem as shown in the
10 Table 5.4.19.
(a) For J A Assigning a = 000, b = 001, c = ala, d = all

(b) For K A (e) For J s (d) For Ks (e) For output and e = 100 and referring excitation table for RS
Fig. 5.4.17 flip flop (Table 5.4.16) we have following excitation
Therefore, input function for table.
fA = BX + BX
KA = BX + BX
Table 5.4.20 Minimized state table
JB = AX
TECHNICAL PUBLICATIONS'". An up thrust for knowledge
...\
Digital Principles & System Design 5 - 42 Analysis & Design of Clocked Sequential Circuits r Digital Principles & System Design 5 - 43
---
1
i ~ Design Wit~~
• There are occasions when a sequential circuit may use less than the available
number of states. We can consider the unused states as don't care conditions and
a can be used to simplify the input functions to flip-flops.
b • Let us consider one example. First we will design the given sequential circuit
c without using unused states and then we will design the given sequential circuit
d
using unused states.
e
K~map simplification
ForRA For Re
BC BC
xf!\. 00 01 11 10 Xf!\. 00 01 11 10
oosx --5(' 0 X 00 X 0
01 1 X X X 01 X X
11 1 X X X 11 0 X X X 11 0 X X X
,L
10 X X X X 10 0 0 0 0 10 X 0 0 0
~~t'
ForSe ForRe ForSe
BC
Step 1: Derive excitation table
XA 00 01 11 10 00 01 11 10 r-'
The excitation table for given state diagram is as follows
00 X 1 1 ~ 00 0 0 0 0
01 X X X X, 01 0 X X X
11 0 X X X 11 1 X X X
10 X 0 0 0 10 1 X X 1
Se=XA+ Be Re=X Se=X

Fig. 5.4.19
Logic diagram
A C
CP - f - - - - - d ' S
A--r-- A X
C
X-t...-'" A
S·r--
C
Fig. 5.4.20 Table. 5.4.21
TECHNICAL PUBLICA TlONS'" - An up thrust for knowledge

, ) li
Digital Principles & System Design 5 - 44 Analysis & Design of Clocked Sequeniist Circuit« ~afPrincipies
!
Syslem Design 5 - 45 Analysis & Daslgn of Clocked Saquanlial Clnoul/S
Step~ma lification for K i: u; and gr;~t- o;;V Derive circuit output and flip-flop input~C~~~~d-$~
/
ex
.. F~rJA For KA ex For JB . ex For K
B
et us see the circuit design with the use of unused states. These unused states ODD,
AS 00 01 11 01 11 AS 00 01 11 10 AS 00 01 11 10 101 and 111 are considered as a don't cares and are used to simplify the K-maps as
)-~-
00 0 00 X X 00 X follows :
01 0 0 01 X X X X ForJ A
ForJ B
ex Sexoo ex
11 X X AS 00 01 A 01 11 10 AS 00 01 11
11 0 0
00 X X 00 ··x X 1 i1i 00 X
10 X X 10 X X
01 0 0 01 X X X lxl
i i 01 X
11 X X 11 X X X !X! 11 0 11 0 0 X ·X
ForJ c ForKc
cx-. ex ex
For Output 10 X X 10 1
k •._ 0 X lxl 10 0 10 X X X X
AS 00 AS 00 01 11 AS 00 01 11 10
00 00 00 ForJ c ForK c For Output
" . \ 01
11 11 X X
10 10 X X 01
Fig. 5.4.22 11
Therefore, input functions for 10
Fig. 5.4.24
Therefore, input functions for
Circuit output function, Y = AB C X + ABC + ~A BC + ACX

St~p
3 : raw logic _diagram. /
The circuit output function Y = ABX + ACX + BX + CX
/ ~ 1 ,......,.,........".......,
C
A Step 5 : aw logic diagram.
C
X
A
c x
A
8
C
X
Output (Y) A----o-,
A B
!l. C
B ~
c
x x ~---.---- Output (Y)
.t, C
x---._-
8
C xc c
(A~ C]<) Output of AND 7
X
. (A C X) Output of AND 5
cp--..------------~ Output otAND 3
L~
(b)
(a)
Fig. 5.4.23 Fig. 5.4.25
TECHNICAL PUBLlCATlONS"'_ An up thrust for knowledge TECHNICAL PUBLlC~S'M - An up thrust for knowledge
Digital Principles & System Design 5 - 46 Analysis & Design of Clocked Sequential Circuits
From the logic diagram it can be realized that using unused state as don't cares we solution:
step 1 : State diagram
can furt r sim e ' -flop input functions and circuit output function.
Here, states 5, 2 and a are forced to go
into 6, 3 and 1 state, respectively to avoid
ocked Condition
lockout condition.
• --I.i"l:-e~gy;R-ff~'[f
the next state
of some. unused state is again
an unused state and if by step 2 Excitation table
chance the counter happens Next states
to find itself in. the unused
states and never arrived at a B+1
used state then the counter is (a) Desired sequence (b) Uhused state forming lockout
a a
q
f
. said to be in the lockout
onditions. This is illustrated
in the Fig. 5.4.26.
Fig. 5.4.26
1 a
a 1
~
• The counter which never goes in lockout condition is called self starting counter.
a a
• The circuit that goes in lockout condition is called bushless circuit.
(~
1 1
• To make sure that the counter will come to the initial state from any unused state,
the additional logic circuit is necessary. 1
• To ensure that the lock out does not occur, the counter should be designed by 1
forcing the next state to be the initial state from the unused states as shown in
1
Fig. 5.4.27.
Step 3 K-map simplification

ForJ B
BC
11 10 A 00 01 11 10
o 0 o x x
00 ~ o 0
X X
-:
Fig. 5.4.27 State diagram for removing lockout
JS=A
JA =BC
For example, as shown in Fig. 5.4.27, actually it is not necessary to force all unused For Kc
For K B
states into initial state. Forcing anyone state is sufficient. Because if counter initially 11 10
00 01 11 10
goes to unused state which is not forced, it will go to another unused state. This will A 0 X
continue until it reaches the forced unused state. Once forced unused state is reached
0 X
next state is used state, and ree circuit. This is illustrated in Fig. 5.4.27 (b).
J c = A+ B Kc=B

w
TECHNICAL PUBLlCATlONS - An up thrust for knowledge
r
1
f
Step 4: Logic diagram

Step 3:
So = 0000,
Assign states,
Next state
x = 1
x = 0
Sl = 0001,
. 0001 0010
~JA - 0A Js Os
I-V Jc °c I--<
S2 = 0010,
0011 0100
S3 = 0011,
r-<t>@ ~0 0011
crAP t>0
,---< ,---< 0100
D-~KA KS
OS r KC Oc
S4 = 0100, 0101 0110
S5 = 0101, 0110 0101
S6 = OlIO, 0111 1000
1000 0111
CP
S7 = 0111,
0000 0000
Fig. 5.4.29 S8 = 1000.
0000 0000
Step 4: Determine the . state
Table 5.4.23(b) State transition table
transition table.
For a four bit even parity bit generator inputs c l erially. The four bits of
the input sequence are to be examined by the circuit and a parity bit Design a sequential circuit with 4 FF ABCD. The next states of B, C, Dare
which is to be added in the original sequence. The circuit equal to the present states of A, B, Crespectively. The next state of A is equal to the
I another four bits after producing a parity bit for the last seq EX-OR of the present states of C and D.
I'
~
and write down the state transition table. Solution:
Solution: ~--------------I
(
I Step 1: Draw the state diagram. Step 2 : Determine the stable table. DA QA Dc Qc DO Qo
F/F F/F
The state diagram for given problem is Next state F/F
[ i
© @
f
as shown in the Fig. 5.4.30. ®
x=O x=l Qc
ClK ---..lo--- -----i~----.e--------'

Fig. 5.4.31
synchronous
for the given
Table 5.4.23(a) State table

o
Fig. 5.4.32
Fig, 5.4.30 State diagram

~.'
f
I
Digital Principles & System Design 6-2 Shift Registers
i
I
I
III I~roduction A B c D
• }~iP-flOPS can beused-to.store a word, which is ca_ll~e\~--",-----:/

• A... ip-flo can stor~it in~a~. So an n-bit register has a group of n
flip-flops and is capable of storing any binary information/number containing
n-bits.
BD Buffer Register CP --J--===---W----===-+~==~jJ

• Fig. 6.1.1 shows the sim lest re ister constructed with fou~JThis RD
register is also aIle buffer register..
• Each D flip-flop is triggered with a common negative edge clock pulse.
• The input bits set up the flip-flops for loading. Fig. 6.1.2 Controlled buffer register
• When the first negative clock edge arrives, the stored binary information becomes, • As seen above the 4-bit register can store 4-bit binary information. In general, n-bit
QAQBQCQD = ABCD register can store n-bit binary information.
A B c D
PA QA DC Qc
What is register ?
<9 e What is buffer register ?
What do you mean by controlled buffer register ?
Fig. 6.1.1 Buffer register Shift Registers

• In this register, four D flip-flops are used. So it can store 4-bit binary information. • The binary information (data) in a register can be moved from stage to stage
• The number of flip-flop stages in a register determines its total storage capacity. within the register or into or out of the register up application of cl~ulses. 0;-
this type of bit movement or ?.bill!.ng is essential for certain ~thmetic and logic
Controlled Buffer Register ~~-~sed-ln-ffiI~ssors. This gives rise to a group of registers called
e.---
'~
• We can control input and output of the register by connecting tri-state devices at
the input and output sides of register as shown in Fig. 6.1.2. So this register is Databits~ ~Databits
called 'controlled buffer register'.
• Here, tri-state switches are used to control the operation. (a) Serial shift right, then out (b) Serial shift left, then out
• When you want to store data in the register, you have to make LOAD or WR Data bits
signal low to activate the tri-state buffers.
• When you want the data at the output, you have to make RD signal low to
activate the buffers.
[tiTI ~ C[fdJJ L{ffijJ
• Controlled buffer registers are commonly used for temporary storage of data ~
Data bits
within a digital system.
(e) Parallel shift in (d) Parallel shift out (e) Rotate right (f) Rotate left
Fig. 6.2.1 Basic data movement in registers

TECHNICAL PUBLICATIONS"·'· An up throe: for knOWledge
T ------------
Digital Principles & System Design 6-5
It They are very important in applications involving the storage and transfer of data
in a digital system. • Fig. 6.3.2 shows waveforms for shift left operation
• Fig. 6.2.1 gives the symbolical representation of the different types of data
~ movement in shift register operations. I II
i
1 2 3 4
.~ According to the data movement in a register, there are different types of shift , . CP
registers. ! I
I Types of Shift Registers
i-D,
I I
j In I
..... , .. ...
i
I .~
j I 1 1 1 1
~~~)iShift Register
I
I----- 00
.... ... .... ......
01
0 1 1 1
Shift Left Mode I-----
i I
• Fig. 6.3.1 shows serial-in serial-out sh~register. i I
0 1 1
I·· •
D OU !- °A DA Os Os °c Dc
!
°D DD ---- Din
-- °2 I
0
(Serial data outp ut) i i

(S erial data input) 1
0« ~ @« P- @< 0-- @< 0- 0 31 0 0 0
-----
..
Jli1SL
CP
=1 1000 1100 1110 1111
...__.-.....'_.,_...
. Data in register
.. ,,',,"
Fig. 6.3.1 Shift-left register Fig. 6.3.2 Waveforms for shift left register
;) We will illustrate the entry of the four bit binary number 1111 into the register, Shi~ode ." .....
beginning with the left-most bit. Initially, register is cleared. • Fig: 6.3.3 shows serial-in serial-out S~ri~register.
r
SO QAQBQCQO == 0000 Din- 0 3 O2 01 Do 00 ~
°3 °2 °1
• The Table 6.3.1 summarizes the shift left operation. r< ~@
r-< >.0 --c >® --c >@
CP
Fig. 6.3.3 Shift-right register
• We will illustrate the entry of the four bit binary number 1111 into the register,
beginning with the left-most bit. Initially, register is cleared.
SO Q 3Q2Q1QO == 0 0 0 0
• Table 6.3.2 summarizes the shift right operation.
Table 6.3.1 Shift left operation
Table 6.3.2 Shift right operation

it
The Fig. 6.3.4 shows waveforms for shift right operation.

i
.
, Ij
1 2 3 4
- Cp- --+-- ...... _- I - - --- I--
I······
Serial
03 Q3 data
-0
. In I -= CD
Qut-,
! i 1 1 1
............ Q
3 cp_~--====_l--====----l~===~....J
i ! '···1 i··· ... ...
i I Fig. 6.3.6 Parallel In Serial Out (PISO) shift register
- ~. Q a 1 1 1
r
2
i I
!
._. ..... Q
1
I a .rr 1
• There are four input lines A3, A 2, AI' A o for entering data in parallel into the
register.
! i
I • SHIFT/LOAD is the control input which allows shift or loading data operation of
0°1 a a a! 1
the register.
I
-1 0000
.
1000
_.~---_._~----
1100 1110
---
1111 Data in ,~, ..
, ", • When SHIFT/LOAD is low, gates G I, G2, G3 are enabled, allowing each input
data bit to be applied to D input of its respective flip-flop.
Fig. 6.3.4 Waveforms for shift right register
• When a clock pulse is applied, the flip-flops with D = 1 will SET and those with
erial In Parallel Out (SIPO) Shift Register
D = a will RESET.
• The data bits are entered serially into the • All four bits are stored simultaneously.
register but the output is taken in parallel. • When SHIFT/LOAD is high, gates G I, G2, G3 are disabled and gates G 4, Gs, G 6
• Once the data are stored, each bit appears are enabled. This allows the data bits to shift right from one stage to the next.
on its respective output line and all bits • The OR gates at the D-inputs of the flip-flops allow either the parallel data entry
are available simultaneously as shown in operation or shift operation, depending on which AND gates are enabled by the
Table 6.3.3 Truth table
Fig. 6.3.5.
level on the SHIFT /LOAD input.
J
Oat~-.- 0
input' 3 °3 °2 °2 ~
°1 °1 ~O
°0 I-- Parallel In Parallel OU~hift Register
r-<: >0 r-<: >0 r-<: ><D r-< >(2)
• In 'parallel in parallel out register', there is simultaneous entry of all data bits and
the bits appear on parallel outputs simultaneously.
• Fig. 6.3.7 shows this type of register.
Fig. 6.3.5 A Serial In Parallel Out (SISO) shift register
Parallel In_~~ljal/o6hiftR~gist~r
• In this type, the bits are entered in parallel i.e simultaneously into their respective
stages on parallel lines.
• Fig. 6.3.6 illustrate~ a four-bit parallel in serial out register.

Digital Principles & System Design 6-9 _______________S:-h~i"~t~Registers
Parallel data inputs
------------
Az A 1
• When the RIGHT/LEFT signal is low, gates G s, G 6, G 7, G s are enabled.
.. The Q output of each flip-flop is passed through the D input of the preceding
flip-flop.
'--
°3 Q3 - - °2 Qz - - °1 Q1 I-- '--
Do >00 r-
• When clock pulse arrives, the data are shifted one place to the left.
-< ~<D rC ~® --<l >iG) r-C >@
Bidirectional Shift Register with Parallel Load
»<
• When parallel load capability is added to the shift register, the data entered in
/: --
parallel can be taken out in serial fashion by shifting the data stored in the
Q3 Qz Q1 Q
- --....--
Parallel data outputs
- register. Such a register is called bidirectional shift register with parallel load.
• Fig. 6.3.9 shows bidirectional shift register with parallel load.
Fig. 6.3.7 Parallel In Parallel Out (PIPO) shift register
• As shown in the Fig. 6.3.9, the D input of each flip-flop has three sources: Output
Bidirectional Sh,fCRegister of left adjacent flip-flop, output of right adjacent flip-flop and parallel input. Out
• This type of register allows shifting of data either to the left or to the right side. It of these three sources one source is selected at a time and it is done with the help
can be implemented by using logic gate circuitry that enables the transfer of data of decoder. The decoder select lines (SLI and SLo) select the one source out of
from one stage to the next stage to the right or to the left, depending on the level three as shown in the Table 6.3.4.
of a control line. Parallel Inputs
• Fig. 6.3.8 iIlustrates a four-bit bidirectional register.

------------------
RIGHT / LEFT
Serial data in
for right-shift
Parallel outputs
Fig. 6.3.9 4-bit bidirectional shift register with parallel load
Fig. 6.3.8 4-bit bidirectional shift register

• When select lines are 00 (i.e. SLI = a
• The RIGHT/LEFT is the control input signal which allows data shifting either and SLo = a), data from the parallel
towards right or towards left.
inputs is loaded into the 4-bit register.
• A high on this line enables the shifting of data towards right and a low enables it
• When select lines are 01 (i.e, SLI = a
towards left.
and SLo = I), data within the register
• When RIGHT/LEFT signal is high, gates G I , G2, G3, G4 are enabled. is shifted I-bit left.
• The state of the Q output of each flip-flop is passed through the D input of the • When select lines are 10 (i.e. SLI = 1
following flip-flop. and SLo = a), data within the register Table 6.3.4
• When a clock pulse arrives, the data are shifted one place to the right. is shifted l-bit right.
TECHNICAL PUBLlCATlONS"'- An up thrust for knowledge

-----------------ya a
Digital Principles & System Design 7-2 Counters Digital Principles & System Design 7-3
Counters
Introduction
~unler is a register capable of counting the number of clock pulses arriving at

• The Table 7.1.1 shows the comparison between synchronous and asynchronous
counters.
its clock input.
Asynchronous co
• Count represents the number of clock pulses arrived.
~ arrival of each clock pulse, the counter is incremented by one. In this type of counter flip-flops are
~ase of down counter, on arrival of each clock pulse, it is decremented by one. connected in such a way that output of first
flip-flop drives the clock for the next
• The Fig. 7.1.1 fli -~~P. :____________ __ _ .. . __
shows the logic ClK n-bit n-blt I the flip-flops are not clocked
counter ClK
symbol of a counter __l:llta~~£~sl'.':: .. _
binary counter. c circuit is very simple even for more
ber of states.
• External clock ~ ~
n-bit output Main drawback of these counters is their low
is applied to n-bit output
speed as the clock is propagated through
the clock input (a) Positive edge triggered (b) Negative edge triggered number of flip-flops before it reaches last
of the counter. n-blt counter n-blt counter flip-flop.
Fig. 7.1.1 Logic symbol of counter
• The counter can Table 7.1.1 Synchronous Vs asynchronous counters
be positive edge triggered or negative edge triggered.
Modulus of Counter
• The n-bit binary counter has n flip-flops and it has 2 n distinct states of outputs.
..---------- ..
• The total number gf counts Qr stable states a counter can indicate is called
~r example, 2-bit counter has 2 flip-flops and it has 4 (2 2 ) distinct states : 00, Ol, 'Modclus'.
10 and 11.
• The modulus of a four-stage counter would be 1610, since it is capable of
~3-bit binary counter has 3 flip-flops and it has 8 (2 3 ) distinct states : 000, 001, indicating 00002 to 11112 ,
ala, all, ioo. 101 110 and 111. • The term 'modulo' is used to describe the count capability of counters.
• The ~~that the binary counter can count is t:: • For example, mod 6 counter goes through states a to 5 and mod 4 counter goes
through states a - 3.
• For example, in 2-bit binary counter, the maximum count is 2 2 -1 = 3 (11 in
binary). Draw the state diagra . OD-10 counter.
• After reaching the maximum count the counter resets, to a on arrival of the next Solution:
clock pulse and it starts counting again.
Synchronous Counter:
• When counter is clocked such that each flip-flop in the counter is triggered at the
same time, the counter is called synchronous counter.
Asynchronous Counter I Ripple Counter :
• A binary asynchronous/ripple counter consists of a series connection of
complementing flip-flops, with the output of each flip-flop connected to the clock 85
input of the next higher-order flip-flop.
Fig. 7.1.2
• The flip-flop holding the least significant bit receives the incoming clock pulses. As.sume 'tha: the 5-bit binary. counter .starts in the 00000 state. What will be
thecoutlfajter 144 input pulses ?
TECHNICAL PUBLICATlONS"'- An up thrust for knOWledge
Digital Principles & System Design 7-4
Counters Digital Principles & System Design 7-5 Counters
Solution: (144ho = (1001 OOOOh
Since counter is a 5-bit counter, it resets after 25 = 32 clock pulses.
• The clock signal is connected
to the clock input of only CP
I 1
4 first stage flip-flop. I 1
32 fi44
- 128 • The clock input of the
LSB 0A
0
I I
0
I
j
L
1
16 second stage flip-flop is MSB Os

0
1
1
0
I 1
.,
·1 L
sg
I 1
triggered by the QA output
Therefore, counter resets four times and then it counts remaining 16 clock pulses.
Thus, the count will be (10000h, i.e., 16 in decimal. of the first stage.
Count
stage
01
1 I 10
2 I 11
3 I
In general, • Because of the inherent Fig. 7.2.1 (b) Timing diagram for the counter of
propagation delay time Fig. 7.2.1 (a)
Count = Remam. d er 0 f [Number of input pUlses] in binary
2n through a flip-flop, a .. t of first stage
transition of the input clock pulse and a transition of the QA o~tpu
where n = Number of counter bits can never occur at exactly the same time. Therefore, the two flIp-flop.s are never
simultaneously triggered, which results in asynchronous counter operation.
Fi . 7.2.1 (b) shows the timing diagram for two-bit asynchronous counter. It
1. What is counter? • illustrates
g the changes in the state 0 f th e fliIp- flop 0 utputsin response to the clock.
2. State types of counters. • J and K input of JK flip-flops are tied to logic HIGH hence output will toggle for
3. Compare synchronous and asynchronous counter. each negative edge of the clock input
4. What is MOD counter?
Extend the counter shown ·in Fig. 7.2.1 (a) for 3-stages, and draw output
5. Give comparison between synchronous and asynchronous counters. wa1?eforms.
Ripple I Asynchronous Counters Solution:
HIGH
• A binary ripple/asynchronous counter consists of a series connection of
complementing flip-flops, with the output of each flip-flop connected to the clock
1>(6) n @ n
~ JAOA ~ Js Os p- J I-
input of the next higher-order flip-flop. c °c
e The flip-flop holding the least significant bit receives the incoming clock pulses.
CP - t--<
-
o
L- KA °A
L- Ks as '-- Kc Oc I-
• A complementing flip-flops can be obtained from a JK flip-flop with the J and K
inputs tied together as shown in the Fig. 7.2.1 or from a T flip-flop. Fig. 7.2.2 (a) Logic diagram
• A third alternative is to use a D flip-flop with the complement output connected

to the D input
CP
• The D input is always the complement of the present state and the next clock
pulse will cause the QA ....2...-J
,
0 0 0
HIGH-.......- - -_ _---,
flip-flop to complement
Qs
o o
-.::.-......-----
0 0
• Fig. 7.2.1 (a) shows 2-bit
CP JlI1Jl.IL o
asynchronous counter using 0 0
JK flip-flops. 001 010 011 100 101 110 111

2 3 4 5 6 7
Fig. 7.2.1 (a) A two-bit asynchronous binary
counter
Fig. 7.2.2 (b) Output waveforms for 3·bit asynchronous counter
TECHNICAL PUBLiCA TlONS"'- An up thrust for knowledge
n
TECHNICAL PUBLlCATIONS ,- An up thrust for knowledge
Counters
7-15
Digital Principles & System Design 7 - 14 Counters Digital Principles & System Design
Note: The reset input

• At point X, A goes low (A goes high); however, because of flip-flop delay time, B (CLR) of each Flip-FloP
is active-low input.
does not go low until point Y. Thus between points X and Y we have the By making CLR input
condition C =:: I, B =:: 1 and A =:: 1. As a result, the output is high between points of all Flip-Flops logic 0,
we can reset the counter.
X and Y. This undesirable output is known as glitch.
Thus reset logic is
• We can avoid the glitch on the output waveform by connecting clock as a fourth designed such a way
that for invalid
input to the decoding gate along with inputs A, Band C. This is illustrated in the Valid states, Y = a and
states counter resets.
Fig. 7.2.17.
t:' ''-X~
-
1. Explain in detail the operation of a 4-bit binary ripple counter. ~ . ()i
2. Design and explain the working of an up-down ripple counter. 7)f) /1\l/
'';;:J , . Co-J'JL~--
I ~ :Jro r ~:.{/ ~
I~~~~~ (lRJ f1
.
ronous) Counters
- ,iN !()~
.. ~~.
i
'(J~,k
, l r- lD'.....},(11'
r
('Of'
J..~
MJ-(
. .
~
? ()t-"~I
~
Qf!-. Table 7.3.1 Truth table for BCD counter '---
. .
1. Determme the number of flip-flops needed. ? / V' In
r: r
Step 4 : Derive reset logic

2. Choose the type of flip-flops to be used: T ?r JK. If T flip-flops are used conn ct T : coCO CD CD CD
11 10
--
AB ' 00· 01.
ipPut~~ip-flops ~ If ]K flip-flops~re used connect both J and~ l'~W----
MM._._
AS 00 1 1 i 1 1
~all flip flops-!,o logic 1._ _.. _._-,'
Such connection toggles the flip-flop output on each clock transition. AB 01 1 1 1 1
3. Write the truth table for the counter. AB 11 0 0 0 0

BC
4. Derive the reset logic by K-map simplification. AS 10 I1 1 I
t
0 0
5. Draw the logic diagram.

Fi9.7·~-1
~.
Step 5 : Draw logic diagram.
logic 1
Solution:
elK
Step 1 : Determine the number of flip-flops needed. The BCD counter goes through
states 0-9, i.e. total 10 states. Thus, N =:: 10 and for 2n ~ N, we need n =:: 4,
i.e. 4 flip-flops required.
Step 2 : Type of flip-flops to be used : JK
Step 3 : Write the truth table for the counter Reset logic
Fig. 7.3.2 Logic diagram of BCD ripple counter

Counters
7·17
~igital Princ!£!!..-S & System Design
Digital Principles & System Design 7 -16 Counters
Step 4: Derive reset logic
i;tep 3: Write the truth table for counter
Design a 3-bitasynchronousripple counter using T jlip-flopsan4explCiinits
operation. ~
Solution: The Fig. 7.3.3 Logic 1---<~-------+--------.., BC Be BC Be BC
shows a 3-bit AOO 01 11 10
asynchronous ripple A0 _a1__ i . __...
~
1iI
counter using T Valid

states
flip-flops. As shown in
Fig. 7.3.3, the clock input
B
of only first stage Fig. 7.3.3 3·bl'f asynchronous counter using T flip-flops :. Y =A+B
flip-flop. The clock input
of the second stage flip-flop is triggered by the QA output of the first stage and third
stage flip-flop is triggered by the QA output of second stage. Because of the inherent Fig. 7.3.6
propagation delay time through a flip-flop, a transition of the input clock pulse and a
transition of the QA output of previous stage can never occur at exactly the same time.
lstep 5: Draw logic diagram
Therefore, flip-flops are never simultaneously triggered, which results in asynchronous logic 1-------..,------1
counter operation. C
Since, T input is connected to logic 1 each flip-flop toggles at clock input. The elK
Fig. 7.3.4 shows the timing diagram for 3-bit asynchronous counter.
CP
:
QA -LJ a a j a L Reset logic
Fig. 7.3.7
Qs a a a a j L
Qc a a a a L
~l I
Count 001 010 011 100 101 110 111
stage 1 2 3 4 5 6 7
occurrence of count 1010.
Fig. 7.3.4 Output waveforms for 3·bit asynchronous counter [Ans, ; y = A + DC]
Example 7.3.5 : Design mod 5 ripple counter using T flip-flops.
Design mod 6 ripple counter using T flip-flops.

Solution:
Step 1: Determine the number of flip-flop required. Here, counter goes through 0 - 5
states, i.e., total 6 states. Thus N = 6 and for 2n ~ N we need n = 3, i.e. 3
flip-flops. Synchronous Counters
. 1 k d such that each flip-flop in the counter is triggered at the
Step 2: Type of flip-flops to be used : T 61 When counter IS c oc e
same time, the counter is called as synchronous counter.

, Digital Principles & System Design
7 - 22
Counters
•
11'I Design of Synchronous Counters Digital Principles & System Design 7 - 23 Counters
?- K-Map simplification
n
ForJ c For Kc ForJ s
1. Dete'mine the numbe, of flip-flops needed. If n 'epresents number of flip-flops BOA BOA
2 2:: number of states in the counter. oc 00 01 11 10 oc 00 01 11 10 11 10
2. Choose the type of flip-flops to be used. 0 0 0 1 0 o rX' X X X' X
1 X X X X 1 iii X X X o X
3. USing
counter.excitation table fa, selected flip-flop detennine the excitation table fa, the
Jc = °BOA
ForKs
4. functions.
Use K-map any other simplifleation method to derive the flip-flop input DO
0'
11 10 oc B A00 01 11 10
X X l' 0 0 X 1 1 X'
1 X X ..0..1 X 1 lx X X X
JA =Qc
Fig. 7.5.1
- .....S lution : - y -< (). tX <:> "" .. 0.. 0) ff
J7)8 :';-'f! i f
~ '2 '~)
ep 1: Detennine the numffer of flip-flop needed Step 5: Draw the logic diagram Timing Diagram
L Ti Flip-flops required are
2 n 2:: If\J)
i. oD(j;lJ-'
t.,,/..-(
Ie.;
-:;?
r
/ F(::-
n = 3 i.e. ~_flip-flops are required._
>
Here N = '9' < •

Type of flip-flop to be used ; IK .~
CP
Step 2 :
QA
Step 3: Determine the excitation table for the counter. I
CP .
Qs 0 0 I
I
I
I0
I
0
I
°A(LSB)
<;
Os
-..........--
°c(MSB)
.--/
Qc 0 0 0 I
,
I
0
rTl I
0
Outputs
Fig. 7.5.2 (a) MOD-5 synchronous counter
Fig. 7.5.2 (b)

Table 7.5.1 Excitation table for
JK flip-flop
Solution :_~ d d
Step 1: Determine the number 0 . -flo
.~ p s nee e .
~ble 7.5.2 Excitation table '0' count.. For designing mod 6 counter using the formula
2 n 2:: N
r[\\ ~.' ~~
~) . .t>:>
Here
Step 2 :
N - 6 '.. n = 3
Type of flip-flops to be used : T
. 3 flip-flops are required.
I.e..
TECHNICAL PUBLICATIONS'". An up thrust for knowledge
TECHNICAL PUBLICATIONS"' · An up thrust for knowledge

7 - 24
Step 3: Determine the excitation table for counter.

Counters
---
step 2:
.
Type of flip-flop to be used : SR
7 - 25 Counters
step 3: Determine the excitation table for counter.

Here, the next state for each present state is written according to given sequence. For
example, the next state for the present state 000 is Ill.
Table 7.5.3 Excitation table for

T-fllp-flop
Table 7.5.4 Excitation table for counter
Step 4: K-map simplification.
ForTe ForT B
I 01
01 11
QQ
B A
\ 10 QC 00
0 1
01
1
11
1
10
1
1 1 1 X X
Fig. 7.5.3
Step 5: Draw the logic diagram.
Table 7.5.5 Excitation table of SR

flip-flop Table 7.5.6 Excitation table for counter
Vee
(1)
Step 4 : K-map simplification.
For SA ForRA ForS s

BC
01 11 10 A 00 01 11 10 01 11 10
0 0 0 0 X X X 0 X 0
Q e (MSB)
---------------------~-- X X X 0 0 0 0 X 0
Outputs
Fig. 7.5.4 logic diagram SA =ii:BC RA =ABC SB=BC
For RB ForSe ForRc

BC BC
ABC 00 01 11 10 A 00 01 11 10 A 00 01 11 10
1"""""
0 0 X 0 0 1 0 0 1 0 0 1 1 0
Step 1: Determine the number of flip-flops needed 0 X 0 1 1. 0 0 1 1 0 1 1 0

b_ il7;'TrlTh
n
We know that 2 ::::.: N. Here, N =8 :. n =3 RB= BC Sc = C RC = C
of
Fig. 7.5.5 (a)

TECHNICAL PUBLICATIONS"'. An up thrust for know/edge
f)igital Principles & System Design
-~-----------_.-
"~ri~nc~ip~/~e~s~&~S~y~s~te~m~D~e~s~ig~n~ ~-=.:~
7 - 26
. . t!. 7-27 _
----
Dlgda P Counters
Step 5 : Draw logic diagram
A_I, step 4: K-map simplification
B
C -- ForQO+1 For Qc + 1
QSQA QSQ A
Q o Qc 00 01 11 10 Q o Qc 00 01 10
1_1_-,
00 0 00 0
C
01 01 (11
Q A (MSB) Q
' ---- Outputs

Fig. 7.5.5 (b) Logic diagram
s
---------------- Q C (lSB)
11
11~~T
10 l...----¥ __=_
QO+1 ;"'OOQA + QCQBQ A QC+1 = Q
/' Fa Q B +1
y ~..
Solution:. ~ade co~
e.1'\/;) 0' is a mod-lO Counter. It has ten states: 0 _ 9.
\~ \ '\"","r®-®-~_"", ""
~o\·:\· ~
00
~
01
\ \ ,0 " \ Fig. 7.5.6 11
Step 1 Determine the number of flip-flops needed. 10 10 Io=:~ _
Step 2 :
~
We know that 2" N. Here, N 19 .. n ~ ~ 4 i.e. 4 flip-flops needed. 'A
'----'----
Type of flip-flops to be used , D ~ \y ,~trd

Step 3 :
Determine the excitation table for counter.
r Step 5 : Draw the logic diagram.
Qo_...._-,
Os
QA--'--''''-
Qs
°A- ._-
°c_ . ,
Qs h"..---==_ . -I (lSB)
QA
ClK -~===--------
Fig. 7.5.8 Logic diagram
'r
Table 7.5.7 Excitation table for counter
TECHNICAL PUBLICA nONS'"- An up thrust for knowledge

TECHNIC AL PUBLICATIONS'"- An up thrust for knowledge
- -~--------~~~~-
~rinciples & System Design
7 - 28
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 X X 1 00 X 1 1 X
01 1 X X 1 01 X 1 1 X
11 X X X X 11 X X X X
10 1 X X X. 10 X 1 X X
K D :: 1
Fig. 7.5.9
Implementation
Logic 1
A
D
CLK--+-------If-----+------+-----+------+----J
ForJA
CD Q D (LSB)
AB 00 01 11 CD ForJs
AB 00 01 11 10 CD
00 0 0 AB . 00 01
00 X
'Y=~
X
,,--
X
01 0 00 0 0
0
01 X X X X 01 X
11 X X X
11 X X X X 11 X
10 X X X
0 0 1 X, X Step 1: Determine the number of flip-flops needed. Here, counter should count
10 0 0
J A :: BCD
maximum count = 7 = (111h which is 3-bit. Thus, we need 3-flip-flops.
Js - CD Step 2: Flip-flops to 'be used : JK.

TECHNICAL PUBLiCATIONS'"
- An up thrust for knowledge
TECHNICAL PUBLICATlONS"'- An up thrust fOI knowledge
7 - 30
------------------------------------
Step 3: Determine the excitation
table for counter. Here, the
next state for each present
state is written according to
Counters
--
DlgJta
. . I Principles & System Design
step 5 .. Draw logic diagram.

7 - 31 Counters
given sequence. For example,

the next state for the present
state 3 (all) is 7 (111). The
counts which are not in
sequence are treated as don't
cares.
CP~---~+-~~--I~
A(MSB) B C (LSB)
"-----------------.......--- - - - - -. - /
Output
Table 7.5.8 Excitation table of JK
flip-flop
Step 4 : K-map simplification Table 7.5.9 Excitation table for counter

Solution:
ForJA
ForKA =4 .
Step 1 .. N u mber of flip-flops needed ~
BCB e BC ac Be
A 00 01 BC Be BC BC Be
11 10 A 00 01 11 10 Step 2 : Flip-flops to be used = SR ~ ..•
A0 0 0 1 X
00 01 11 10
A0 X X X X
~ ~~':""'~"'''''''''~~-'~.,~''''".-]
0 0 1 X
A 1 X X X X Step 3 : "
X A 1 1 X 0 0 A 1 0 X X X
ForKS
BC Be BC ac Be ForKC
A 00 01 11 10 BC Be BC BC BC
----... 00 01 11 10
0 r"-'-
X X 0 X A 00 01 11 10
-,
0 IS. 1 X x . ~J
A 1 X
A 0- x 0 0 x
X 0 1 A 1 0 X X
~,.
0 A 1
Kc=A
Fig. 7.5.11
TECHNICAL PUBLICATIONs'''. An up thrust for knowledge
TECHNICAL PUBLICATlONS"". An up thrust for knowledge

Counters
r
• , I Principles & System Design
~
7 - 33
ForR c
Counters
For Sc :::0
M M= 1
M= 1 D CD 10
M =0 CD 10 AB 00 01 11 10 AB 00 01 11
01 11 10 . AB 00 01 11
......::.::.:...-;;..:..,....;..;..,--.., X 00 X X 0 1 00 X 0
o X 0 00 0 0
X 0 01 X 0
01 0 X 01 0
0 X 0
X 11 X X X X
X X X 11 X X
X X X 11 X
10 X X X X
X 10 0 X X
0 X X 10 0 0 X
Rc=MCD+MCD
Sc =M BC is + MAC D
{fJ M::: 0
For So
M=1 ,tV - M::: 0
01 11
For R o
AB
CD
00 01 11 10
M =1
CD 10
CD
00 01 11 10 AB 00 01 11 ....
AB
.~ i"····· '~"i
""~
1 00 0 '--1 ' f' 0
00 1 0 0 1 00 1 0 0
01 0 1 1 0
0 1 01 1 0 0 1
01 1 0
~;~
11 X X X X
Table 7.5.10 X 11 X X X X
11 X X X
1 X. X
~~.4 K-ma: Si~::i::atiOn

10 0
_ 1
10. ~...,,' 0 X
b~'...
10 ~.,1., 0 X e, '" '"
_ : .... _----
R =D
o
' / . M = U / D =0 M = U / D =1 M=O M =1
CD CD CD
AB 00 01 11 10 AI?! 00 01 11 10 AB 00 01 11 10 B D 00 01 11 10 Fig. 7.5.13
r: . 00 0 0 0 00 0 0 00 0 X X X 00 X X X X
~""" 01 0 0 0 0 t"b1 0 0 01
."
X
... ",
X X X
•." ....
01 X X 0 X
M
A-.--....
11 X X X X 11 X X 11 X X X X 11 X X X X B
C A
i5
10 0 X X X 10 X O' 10 1 0 X X 10 0 1 X X
/~!-.
'~..J
""'"".
r-""_
ForS B For RB // ~ - ' ------'

M =0 M=1 M =0 M=1 M--r--.....
CD CD
B D 00 01 11 10 AB 00 01 11 10 B 00 01 11 10 AB 00 01 11 A
o~--
00 0 0 0 0 00 0 0 00 X X X X 00 X X CP--------~-----------'
."'.~ M-r--....
01 0 X X X 01 X X 01 1 0 0 0 01 0 0
.....,
,
,""'."
B
C
"5
11 X X X X 11 X X 11 X X X X 11 X X M-r"-.....
!}}.,.,;
A
10
b",c!
1 0 X X
t,,,.w,
10 0 0 10 0 X X X 10 X X E~--
R B = M BCD + MBCD
Fig. 7.5.14

TECHNICAL PUBLICATIONS"" An up thrust for knowledge
Counters
7 - 35
Digital Principles & System Design 7 - 34 Counters
.a.,;
Hil Jc
c
- JA .A.. L-_ JB
Solution:
Step 1 : Since 2 3
> 7, three flip-flops are required
:-< > 0 r< > ® :-< > e Ie ~
Step 2 : Flip-flops to be used : JK

t-- - KA
A
I--
Hig~
I- KB
rt Kc
Step 3 : Excitation table for counter CP C (LSB)

A (MSB)
solution:
step 1 : Since N = 10,
step 2 : Flip-flops to be used: T
Determine excitation table for counter
step 3 :
Next state
ForJ s
BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
,....
0 1 1 0 X 0 X X X X 0 1 0 X X
1 X X X X 1 1 1 0 X 1 1 0 X X
~~." , . . .>• • •
. ForKS ForJ c ForKc

BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
.,.~ ......,.•
0 X X 1 X 0 1 X X X o
1 X X 1
"""'" ~"
X.
.Jii
1 1 X X X
Ks =1 Jc = 1 KC=A
Fig. 7.5.15 (a)
TECHNICAL PUBLICATIONS"'. An up thrust:o r knowledge

7-36
---
Counters , 'tal Principles & System Design 7 - 37 Counters
DIg'
Step 4 : K-map simplification
ForTs
QSQA
B A ForTe
QoQ c 00 01 11
C 00 01 11 10 QSQA
00 0
lip-flop inputs
00 1 1 1 QoQe 00 01
1
01 1 1 1 1
00 0 0 TB TA
11 X X X X 01 0 0
11 X X X X
10 0 0 X X 10 1
11 X 1 1
1 X X
10 0 0 0 1
Tc = QAQ B 1 1
Fig. 7.5.16
0 1
High 1
0 1
1 1
0 1
0 1
1 1
CP-e>--------I-- - - ---J 0 1
1 1
Fig. 7.5.17
0 1
Step 6: Timing diagram
1 1
Fig. 7.5.18 shows the timing diagram for the synchronous decade counter. 0 1
CP 1 1
1 I 0 0 1 j 0
o o ForTe ForTs
o 0
1 0 0
11 10
QSQ A
UD Q c 00 01 11 10 c 00 01 11 10
o o o o o o o o
L o o 00 00
1 1 1 1
01 1 1 1 1
11 1 1 1 1
1 1 1 1
10
------------.~
!!I'
'!
7-38
7 - 39
logic diagram Counters
UP/OOWN-f-- _ Logic diagram
LSB
A MSB Logic 1 C LSB
CP - - 4 , - - - - - - - - , - - + - - - - - - - - - - - J
CP--4-----....::.:::.~k _J
Solution: N = 3 and
Step 1: Since 2 2 > 3, n = 2 'i.e, flip-flops needed = 2.

Step 2: Flip-Flops used: JK
Step 3: Transition table
1
o 0 Table 7.5.14
Table 7.5.13 Step 4: K-map simplification

ForJ s ForKs
ForTs QA
BC
A 00 01 11 10 BC ForTe QB a QB a 1 Q
B a 1
A 00 01 11 10 BC
A 00 01 11 a a a x x a x
a a a it~
a
10 1
a a 1 1 a a 1 1
1 a a
1 1 x x 1 1 X 1 X X
~ a 1 a 1 1 a 1 1 1 1 1 JB =Q A
Ts=C , .'
Fig. 7.5.23 (a)
Fig. 7.5.21
TECHNICAL PUBLIC '"

ATIONS - An up thrust for knowledge
!!..igital Principles & System Design
7 - 40
Counters Digital Principles & System Design 7 - 41 Counters
step 4: K-map simplification
ForJc ForK C ForJ s
QSQA QSQA
Qc 00 01 11 10Qc 00 01 11 10 00 01 11 10
® -
® a a a 0 X X X X a a 1 X X
r--t--I K s Os
o a 1 X X X 1 1 0 1 X X
-
Clock ---------_-.J Jc =Qs QA
ForKs
QSQA
Qc 00 01 11 10 00 01 11 10 Q
c 00 01 11 10
Step 1 : N = 7, and since 2 3 7 0 X X a ~J_ ---xl X 1J 0 X 1 1 X
> , n = 3 i.e. Flip-Flops needed = 3
Step 2: Flip-Flops used: JK
X lX X 1 1 X X a 1 X 1 X X
.-
Ks =QA + Qc
Fig. 7.5.24 (a)
. Nexfstate Step 5 : Logic diagram
a a
a 1 a
a 1
Clock---1IIJo-----------_-------------'
1 a a Fig. 7.5.24 (b)
1 a 1
1 1 a Solution:
a a a Step 1 : Here, N = 4 and since 2 2 :::: 4 we need 2 Flip-Flops
x x x Step 2: Flip-Flops to be used : JK
TECHNICAL PUBLICATIONS'"
- An up thrust for knowledge
7 - 42
7 - 43 Counters
solution: Step 1: State diagram Step 2: State table
Fig. 7.5.26 (a)

Table 7.5.16
Step 4: K-map simplification Upon power on, if counter is in
ForJ s unused states, it is reset to 000.
A ForKS
A
8 A A
8 0 1 8 0 1 8 0
r'-' 1
0 X X 0 1 X j 0 X Step 3: Krnap simplification
( 1
1 0 t
---1 1 1 Xl 1 X 1 ForTA ForTs ForTe

BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
Fig. 7.5.25 (a) o 0 0 0 0 1 1 1 0 1 1 1 0
o 0 1 0 1 1 1 1 1 1 1 0
TA =AB + Be TB=B +C
Fig. 7.5.26 (Il)
Clock --+-------_...J A
B
B B
C C
B C
C
B C
ClK
Fig. 7.5.26 (e)
TECHNICAL PUBLICATIONS'"- An up thrust for knowledge

r
Digital Principles & System Design 7 - 44
Counters Digital Principles & System Design 7 - 45
Counters
Logic 1
8(2) 8(7)
1 A
7400'4 QA J s (9) 8
Os
(15) (11)
Solution: Step 1 : Excitation table X ---,1-L---'-"i 1
(6) 7476'2
B B
K S(12) Qst--~-
(14) (10)
R(8)
7476 (A) 7476 (8)
cp-----...------------~
Solution: Since counter has 0-15 states we need 4 flip-flops.
Next state
Step 2: K-map simplification
ForJ A ForKA
AS
X 00 01 11 10 X AS 00 01 11 10
o o
Fig. 7.5.27
We can implement combinational logic circuit for JA and K input using

A
NAND-NAND logic, as shown in the Fig. 7.5.27.

r Digital Principles & System Design 7 - 46 Counters Digital Principles & System Design 7-47 Counters
K-map simplification Logic diagram

C A
ForJ s D D C
C A~--'
CD D
AB 00 01 11 10 B
D ----1.-",
B----'
00 X X X X C
Logic 1
01 X X X X
11 1 X 1 X A-r---.
C D
10 1 1 X X D ----1.-", B
C
D
JA =CD + CD + B
ForKS ForJ c ForKC
CD CD CD Fig. 7.5.258 (b)

AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
.. ~
rw:~,
00 X X X X 00 X a 1
!; Example 7.5.18 Design a Mod-6 synchronous counter using JK flip-flops.
01 X 1 X 1 01 X t' X X 1
11 a X a X 11 (x"! X 1 f"5<") Example 7.5.19 Find a modulo-6 gray code using K-map and design the corresponding
x) counter.
10 10.. ixJ
..
-
X X X X X X
Example 7.5.20 Design and explain the working of a mod-11 counter.
KC=D+A
-
Example 7.5.21 Using D flip-flops, design a synchronous counter which counts in the
ForJ o ForKo sequence, 000, 001, 010,011, 100, 101, 110, 111, 000.
CD CD
AB 00 01 11 10 AB 00 01 11 10 Example 7.5.22 Design a modulo-12 up synchronous counter using T flip-flops and draw
00 a X X a 00 the circuit diagram.
01 X X X 1 01
11 a X X X 11
Q.1 What is the minimum number of flip-flops needed to design a counter of
10 a X X X 10
modulus 60 ?
Ans.: 2n ~ 60 :. n = 6
K D = AB +AB Q.2 What is the minimum number of flip-flops required to implement a modulo 21
Fig. 7.5.28 (a)
synchronous counter?
Ans. : 2n ~ 21 :. n = 5
TECHNICAL PUBLICATIONS'''· An up thrust for knowledge


Digital Electronics Sequential Cicuits FF

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Digital Electronics Sequential Cicuits FF

Caricato da

Copyright:

Formati disponibili

Sequential Circuits - Flip-Flops

Introduction 1~)/1 Combinational circuits are faster in speed

e;eI<leIltsare drcuH pa:

t Memory ( iow state and is utilized to co-ordinate actions of circuits.

.Z.............. . Present state Next st ate

III One-Bit Memory Cell

TECHNICAL PUBLICATIONS'" - An up thrust for knowledge

1. Explain the operation of one-bit memory cell.

• As shown in the truth table, the Q output

DI Flip-Flops 'JJIIM"IhWPMW!IIDJliMoUWll/iIiliI!m!IU Fig. 4.4.2 Negative level triggering

I!II Latches VsFlip-FIops Ed

• Positive lev~d : The output of flip-flop responds to the input changes

Fig. 4.4.4 Negative edge triggering

TECHNICAL PUBLICATIONS"'. An up thrust for knowledge

TECHNICAL PUBLICATiONS"'. An up thrust for knowledge

TECHNICAL PUBLICATiONS"'· An up thrust for knowledge

Realize SR flip-flop using NOR gates.

Fig. 4.4.10 Negative edge-triggered SR flip-flop using only NOR gates

TECHNICAL PUBLICATlONS"'- An up thrust for knowledge

Fig. Case 3 : J == 0 and K =1

Theiriputs} == o and K ;;:;l,ma-kes Q== O,i.e.,resefsfate.

(Negative edge) ---+ I

e The ncertainty in the state of an SR

TECHNICAL PUBLlCATlONS"'- An up thrust for knowledge

om JK Flip-Flop using N ates.,----. 3 /f· f!-c(U' ~.

K--.1 I :0 i0 I :1 situation is referred to as the race-around condition. This is illustrated in

clock pulsefrom a clocked SR flip-flop consisting of NOR gates.

Cp JLfL S --+--i~,- - " ' ; ' - - - + - - ; - - - T

Fig. 4.4.25 Input and output waveforms for master-slave flip-flop

lID Master-Slave D Flip-Flop

~f a ~L-fL42-flo£,_a slave, flir-=:Pop, .~n_~._~~Jnv~~!~-,-_

TECHNICAL PUBLICATIONS"'. An up thrust for knowledge

e As shown in the T Flip-Flop

the J and K inputs is J

On (No change) J "I 0 :. 0n+1 =TOn+rc,

t a d the K input can be either 0 and 1.

SR Flip-Flop the J input

, t t . 1 and is to change to O. This can happe

circuits using JK flip-flops for the input functIOns are 1

• 0 ---7 0 Transition : When both o ---7 1 and 1---70 transitions T must

4. Give the state diagram of JK flip-flop. mm

Realization of One Flip-Flop using Other Flip-Flop

• The present state • First section specifies the

Used in the design process Table 4.6.1

TECHNICAL PUBLICATIONS"'· An up thrust for knowteaao

K-map simplification Logic diagram -----. ----- SR Flip-Flop to T Flip-Flop

Solution: For SR flip-flop,

K S+RQ n ... Characteristics equation

TECHNICAL PUBLICA TlONS"'. An up thrust for knowledge

_ JK FIiP.F~.FIOP Table 4.6.6

T _~re~~~~~ ~::~'~I ~~F:='S o 0 X 0 X 1..1

o 0 lox J=D K=D

TECHNICAL PUBLICATIONS"'. An up thrust for knOwledge

Ifill JK Flip-Flop 0 SR Flip-Flop ,!-iIO(11 fr

j output does not

Table 4.6.10 Excitation table for JK to SR conversion

TECHNICAL PUBLICA TlONS'". An up thrust for knowledge

1. Convert JK flip-flop to D flip-flop.

a.6 Give the meaning for edge triggering in flip-flops.

Fig. 4.7.2 (a) S;"itch debouncer

Q.8 Convert JK FF to D FF. (Refer section 4.6.5)

1. Distinguish between synchronous and asynchronous sequential circuits.

. . . ut X is used to determine the inputs of the

TECHNICAL PUBLICATIONS"'· An up thrust for knowledge

~f a ~L-fL42-flo£,_a slave, flir-=:Pop, .~n_~._Jnv!~-,-_

_._.__ _.._ _. .~ . .__ F.:ig. 5.3.4 (b) . --