MGA-665P8
Low Noise Amplifier for 3.5 GHz Applications using the MGA-665P8
Application Note 5229
Introduction
Avago Technologies’ MGA-665P8 is a low noise MMIC
using enhancement mode PHEMT technology. The
MGA-665P8 operates from +3 V at a nominal 20 mA
and has a useful power-down function. The device is
designed primarily for the 5 to 6 GHz 802.11 and WLAN
markets but can be applied to other applications in the
0.5 to 6 GHz frequency range. This application note ad-
dresses a design for the 3.5 GHz frequency range. The
3.5 GHz design is targeted at licensed 802.16A WiMAX-
wireless connectivity applications.
While the new Avago Technologies enhancement mode
technology provides excellent RF performance, it also
simplifies MMIC design by only requiring a positive volt-
age on the gate for normal FET operation. This allows
sources to be directly grounded without the customary
source resistor and associated source bypass capacitor.
The MGA-665P8 is housed in a miniature 2.0 x 2.0 x 0.75
mm, 8-pin Leadless-Plastic-Chip-Carrier (LPCC) package.
The compact low profile package offers a size advan-
tage for many applications.
MGA-665P8 Circuit Description
The general schematic diagram and pinouts for the
MGA-665P8 are shown in Figure 1.
GND PADDLE
1: GND 8: UNUSED
2: RFIN 7: RFOUT & VD
3: GND 6: VD
4: UNUSED 5: POWERDOWN
Figure 1. Pinouts of the MGA-665P8 Low Noise MMIC
The MGA-665P8 is a multistage MMIC that requires a
positive supply voltage to be applied at two terminals.
The first stage is biased at the VD terminal while the
second-stage is biased through the RFOUT and VD ter-
minal. This is easily accomplished with a simple bias
decoupling network to be described in this application
note. The POWERDOWN mode is utilized by applying a
positive voltage to the POWERDOWN terminal that is
greater than 1.9 V. Leaving the POWERDOWN pin open
circuited or connected to ground keeps the MGA-665P8
in the normal mode. The ground paddle, as shown in
Figure 1, is the output stage ground, which should be
connected to the printed circuit board ground with
numerous plated through holes for best high frequency
performance. Pins 1 and 3 are connected together inter-
nally and provide the ground for the input stage. Pins 1
and 3 should be grounded to the printed circuit board
ground with a single plated through hole for each pad.
MGA-665P8 Demonstration Board Table 1. Part List for the 3.5 GHz MGA-665P8
The schematic diagram describing the MGA-665P8 Demonstration Board
amplifier is shown in Figure 2. The parts list for the
C1 2.7 pF C6 0.01 mF
demonstration board is shown in Table 1. Standard 0402
Phycomp0402
chip components are used in the assembly.
C2 2.2 pF L1 1.8 nH
The input network consisting of C1 and L2 provide a Phycomp0402 TocoLL1005FH
broad band match that provides a good noise figure
coincident with good input return loss. C1 also provides C3 1000 pF L2 1.5 nH
a dc block for the device. L2 also provides improved Phycomp0402 TocoLL1005FH
ESD protection for the amplifier by providing a dc short C4 10 pF R1 2.2 W
at the input of the amplifier. Phycomp0402
Although the output return loss of the MGA-665P8 is C5 Not Used J1, E.F. Johnson
already very good, network L1 and C2 provides a broad- J2 SMA connector
band bias decoupling network for the insertion of dc 142-0701-881
into the output stage and also provides a dc block at
the output. C4 provides an in-band RF bypass for L1 and
also provides a convenient point at which the first stage
of the MGA-665P8 can be biased. R1 provides a low fre- INPUT C1 Gnd Unused C2 OUTPUT
quency resistive termination. C6 provides a low imped- Zo RFin RFout & Vd Zo
ance bypass that reduces power supply noise. One of Gnd Vd

the most overlooked purposes of C6 is the importance J1 Unused Powerdown L1

J2
L2
of this component in terminating the difference signals
produced when making third-order intermodulation
distortion measurements. C4
C3
R1

Vc Vd C6

Figure 2. Schematic Diagram of the 3.5 GHz MGA-665P8 Amplifier

Figure 3. MGA-665P8 Demonstration Board

2
Demonstration Board
The demonstration board shown in Figure 3 is a two 20

layer configuration for rigidity with a total board thick-

ness of 0.030 inches. The signal layer is the top layer 0
which is 0.010 inch thick RO-4350 while the bottom
layer is 0.020 inch thick FR-4. The RF input and output

dB(S(2,1))
-20
connectors, J1 and J2, are designed for 0.031-inch thick
printed circuit boards. The center pin is trimmed to
-40
about 0.040 inches in length and then the connectors
are installed such that the center pin lays down directly
on the printed circuit board with no gap between the -60

printed circuit board and center pin. Be sure to solder 0 2 4 6 8 10 12 14 16 18 20

freq, GHz
both the top and bottom ground pins of the connectors
to the printed circuit board. Figure 4. Broadband Gain Plot for the MGA-665P8 Amplifier
The demonstration board was designed originally for 5
-10
to 6 GHz applications, which are covered in Application
Note AN5081. The demonstration board is modified for -20

3.5 GHz by disconnecting the input stub to the left of -30

C1. This is accomplished by removing the stub at the
-40
point at which it connects to the input transmission
line. The input stub is replaced by a small surface mount dB(S(1,2)) -50

0402 inductor designated by L2. As shown in Figure 3, -60

L2 bridges the gap between the input transmission line
-70
and the ground pad.
-80

Performance 0 2 4 6 8 10
freq, GHz
12 14 16 18 20

The power supply voltage is +3 V with a nominal cur- Figure 5. Broadband Isolation Plot for the MGA-665P8 Amplifier
rent of 20 mA. The plot of Figure 4 shows that the
demonstration board has greater than 14 dB gain from
2 to 6 GHz. Gain at 3.5 GHz is a nominal 16 dB. The plot
shown in Figure 5 shows the exceptional S12 of the Powerdown Mode
MGA-665P8. Good S12 allows the MGA-665P8 to be The MGA-665P8 can be externally controlled by
used as a buffer for a local oscillator to minimize pull- applying a voltage to the POWERDOWN terminal at
ing on the local oscillator due to load changes. Figure pin 5. With pin 5 left open or connected to ground, the
6 shows the input and output return loss to be greater MGA-665P8 will operate normally. As the control pin is
than 15 dB at 3.5 GHz. increased past about 1.2 V, the gain and device current
Of equal importance is amplifier stability. The MGA- will start to decrease.
665P8 is unconditionally stable through 20 GHz.
The OIP3 is typically +18 dBm at 3.5 GHz. The measured
noise figure of the completed demonstration board is
typically 1.6 dB at 3.5 GHz.

3
 0

(S(2,2))
(S(1,1))

-10
dB

-20

-30
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
freq, GHz

Figure 6. Input and Output Return Loss for the MGA-665P8 Amplifier

Conclusion
The MGA-665P8 has been shown to provide low noise
amplification at 3.5 GHz. The MGA-665P8 provides a
nominal 16 dB gain, a 1.6 dB noise figure, very good
S11 and S22 and an OIP3 of +18 dBm at a power supply
voltage of 3 V at 20 mA.

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Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes 5989-3043EN
AV02-2054EN - August 31, 2010