SKEL 4743: Basic Digital VLSI Design

CMOS Combinational Logic

These set of transparencies are adapted from

lecture notes CSE477 VLSI Digital Circuits at Penn. State Univ., taught by Mary Jane
Irwin and Vijay Narayanan
slides for text J. M. Rabaey et al., Digital Integrated Circuits: A Design Perspective, 2nd
ed. ©2002, J. Rabaey et al.

CSE477 Static CMOS, Ratioed Logic.1 Irwin&Vijay, PSU, 2002

 CMOS Circuit Styles

q  Static complementary CMOS - except during switching, output

connected to either VDD or GND via a low-resistance path
  high noise margins
-  full rail to rail swing
-  VOH and VOL are at VDD and GND, respectively
  low output impedance, high input impedance
  no steady state path between VDD and GND (no static power
consumption)
  delay a function of load capacitance and transistor resistance
  comparable rise and fall times (with appropriate transistor sizing)

CSE477 Static CMOS, Ratioed Logic.2 Irwin&Vijay, PSU, 2002

 Static Complementary CMOS
q  Pull-up network (PUN) and pull-down network (PDN)

VDD
PMOS transistors only
In1
pull-up: make a connection from VDD to F
In2 PUN
…

when F(In1, In2, …, InN) = 1

InN
F(In1, In2, …, InN)
In1
pull-down: make a connection from F to GND
In2 PDN
…

when F(In1, In2, …, InN) = 0

InN
NMOS transistors only

PUN and PDN are dual logic networks

CSE477 Static CMOS, Ratioed Logic.3 Irwin&Vijay, PSU, 2002

 Threshold Drops

VDD VDD
PUN
S D
VDD

D 0 → VDD S 0 → VDD - VTn

VGS
CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD

S D

CSE477 Static CMOS, Ratioed Logic.4 Irwin&Vijay, PSU, 2002

 REVISION: MOSFET AS A SWITCH

5
CSE477 Static CMOS, Ratioed Logic.5 Irwin&Vijay, PSU, 2002
 6
CSE477 Static CMOS, Ratioed Logic.6 Irwin&Vijay, PSU, 2002
 EXERCISE

7
CSE477 Static CMOS, Ratioed Logic.7 Irwin&Vijay, PSU, 2002
 Construction of PDN
q  NMOS devices in series implement a NAND function

A•B
A

q  NMOS devices in parallel implement a NOR function

A+B
A B

CSE477 Static CMOS, Ratioed Logic.8 Irwin&Vijay, PSU, 2002

 Dual PUN and PDN
q  PUN and PDN are dual networks
  DeMorgan’s theorems

A+B=A•B

A•B=A+B

  a parallel connection of transistors in the PUN corresponds to a

series connection of the PDN, and vice versa.

q  Complementary gate is naturally inverting (NAND, NOR,

AOI, OAI)
q  Number of transistors for an N-input logic gate is 2N

CSE477 Static CMOS, Ratioed Logic.9 Irwin&Vijay, PSU, 2002

 CMOS NAND

A B F
0 0 1
A B
0 1 1
1 0 1
A•B
A 1 1 0

A
B

CSE477 Static CMOS, Ratioed Logic.10 Irwin&Vijay, PSU, 2002

 CMOS NOR

A B F
B
0 0 1
A 0 1 0

A+B 1 0 0
1 1 0
A B

A
B

CSE477 Static CMOS, Ratioed Logic.11 Irwin&Vijay, PSU, 2002

 Complex CMOS Gate

B
A
C

D
OUT = ( D + A(B + C) )
A
D
B C

CSE477 Static CMOS, Ratioed Logic.12 Irwin&Vijay, PSU, 2002

 OAI21 Logic Graph

X PUN
A
j C
B C

X i VDD
X = ( C(A + B) )
C
i B A
j
A B
PDN
A GND
B
C

CSE477 Static CMOS, Ratioed Logic.13 Irwin&Vijay, PSU, 2002

 Euler Path and stick diagram

Step 1
Construct a logic diagram of the given function using
NMOS and PMOS
Step 2
Identify each transistor by its gate signal, A, B, C, D
Step 3
Identify each connection between transistors only and
give them a unique name
Step 4
The euler path is defined by tracing a path through the
Circuit so that it tranverses each transistor once
CSE477 Static CMOS, Ratioed Logic.14 Irwin&Vijay, PSU, 2002
 Two Stick Diagrams of !( C(A + B) )

A C B A B C

VDD VDD

X X

GND GND

uninterrupted diffusion strip

CSE477 Static CMOS, Ratioed Logic.15 Irwin&Vijay, PSU, 2002

 Consistent Euler Path
q  An uninterrupted diffusion strip is possible only if there exists
a Euler path in the logic graph
  Euler path: a path through all nodes in the graph such that each edge
is visited once and only once.
X

C
i
X VDD

B A
j A, B, C ordering

GND
q  For a single poly strip for every input signal, the Euler paths in
the PUN and PDN must be consistent (the same).
CSE477 Static CMOS, Ratioed Logic.16 Irwin&Vijay, PSU, 2002
 OAI22 Logic Graph

X PUN
A C

B D D C

X VDD
X = ( (A+B)(C+D) )’

C D
B A

A B PDN
A GND
B
C
D

CSE477 Static CMOS, Ratioed Logic.17 Irwin&Vijay, PSU, 2002

 OAI22 Stick Diagram

A B D C

VDD

GND

q  Some functions have no consistent Euler path. For example:

y = (a + bc + de)’.

CSE477 Static CMOS, Ratioed Logic.18 Irwin&Vijay, PSU, 2002

 VTC is Data-Dependent
3 0.5 µm/0.25 µm NMOS
0.75 µm/0.25 µm PMOS
A, B: 0 -> 1
A M3 B M4 B = 1, A: 0 -> 1
2 A = 1, B: 0 -> 1
For this case, both
F= A • B PMOS are either on or
D off together. When on,
A M2 1
Wp effectively is
doubled (wrt to
S inverter circuit). Hence
VGS2 = VA –VDS1 D VTC moves to the
Cint right.
B M1
VGS1 = VB S 0
0 1 2

q  The threshold voltage of M2 is higher than M1 due to the body

effect (γ)
VTn1 = VTn0
V Tn 2 = V Tn 0 + γ ( )
− 2φ F + V SB 2 − − 2φ F = V Tn 0 + γ ( − 2φ F + V DS1 − − 2φ F )
VSB of M2 is not zero (when VB = 0) due to the presence of Cint
CSE477 Static CMOS, Ratioed Logic.19 Irwin&Vijay, PSU, 2002
 Switch Delay Model

A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
A Rn CL
A Rn Rn CL
Rn
Cint
A B
B
NOR2
NAND2 INV

CSE477 Static CMOS, Ratioed Logic.20 Irwin&Vijay, PSU, 2002

 Input Pattern Effects on Delay
q  Delay is dependent on the pattern
of inputs
q  Low to high output transition
Rp Rp   both inputs go low
A B -  delay is 0.69 Rp/2 CL
  one input goes low
Rn CL -  delay is 0.69 Rp CL

A q  High to low output transition

  both inputs go high
Rn
Cint -  delay is 0.69 2Rn CL
B

CSE477 Static CMOS, Ratioed Logic.21 Irwin&Vijay, PSU, 2002

 Delay Dependence on Input Patterns

Input Data Delay

Pattern (psec)
A=B=0→1 80

A=1, B=0→1 70

A= 0→1, B=1 70

A=B=1→0 80

A=1, B=1→0 150

A= 1→0, B=1 130

- v(B) waveform is exactly similar to v(A) NMOS = 0.9 µm/0.3 µm

- v(OutBTran) is output waveform when PMOS = 0.75 µm/0.3 µm
A = VDD and B = v(B) CL = 10 fF
CSE477 Static CMOS, Ratioed Logic.22 Irwin&Vijay, PSU, 2002
 Transistor Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

CSE477 Static CMOS, Ratioed Logic.23 Irwin&Vijay, PSU, 2002

 Transistor Sizing of Complex CMOS Gate

B 8
A 4
C 8

D 4
OUT = D + A • (B + C)
A 2
D 1
B 2 C 2

CSE477 Static CMOS, Ratioed Logic.24 Irwin&Vijay, PSU, 2002

 Fan-In Considerations

A B C D

A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.

CSE477 Static CMOS, Ratioed Logic.25 Irwin&Vijay, PSU, 2002

 tp as a Function of Fan-In

NAND gate
1250
quadratic
1000
Gates with a
750 tpHL fan-in greater
tp (psec)

500
than 4 should
be avoided
250 tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

CSE477 Static CMOS, Ratioed Logic.26 Irwin&Vijay, PSU, 2002

 Fast Complex Gates: Design Technique 1

q  Transistor sizing

  As long as fan-out capacitance dominates. Otherwise no delay
gain because while we reduce resistance, we also increase
capacitance!

q  Progressive sizing

M1 > M2 > M3 > … > MN

InN MN CL (the FET closest to the output
is the smallest)

In3 M3 C3 Can reduce delay by more than

20%; decreasing gains as
In2 M2 C2 technology shrinks
In1 M1 C1

CSE477 Static CMOS, Ratioed Logic.27 Irwin&Vijay, PSU, 2002

 Fast Complex Gates: Design Technique 2
q  Transistor ordering

critical path critical path

0→1
1 In1 CL charged
In3 M3 CL charged M3
1 1
In2 In2 M2 C2 discharged
M2 C2 charged
1
In1 In3 M1 C1 discharged
M1 C1 charged
0→1

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL only

CSE477 Static CMOS, Ratioed Logic.28 Irwin&Vijay, PSU, 2002

 Fast Complex Gates: Design Technique 3

q  Alternative logic structures

F = ABCDEFGH

Alternative 2

Alternative 1
CSE477 Static CMOS, Ratioed Logic.29 Irwin&Vijay, PSU, 2002