LTC6655/LTC6655LN

0.25ppm Noise, Low Drift

Precision References
FEATURES DESCRIPTION
nn Low Noise: The LTC®6655 is a complete family of precision bandgap
nn 0.25ppm
P-P (0.1Hz to 10Hz) 625nVP-P for the voltage references, offering exceptional noise and drift
LTC6655-2.5 performance. This low noise and drift is ideally suited
nn 0.21ppm
RMS (10Hz to 10kHz) for the for the high resolution measurements required by instru-
LTC6655LN-2.5 CNR = 100µF mentation and test equipment. In addition, the LTC6655
nn Low Drift: 2ppm/°C Max is fully specified over the temperature range of –40°C
nn High Accuracy: ±0.025% Max to 125°C, ensuring its suitability for demanding auto-
nn No Humidity Sensitivity (LS8 Package) motive and industrial applications. Advanced curvature
nn Thermal Hysteresis (LS8): 30ppm (–40°C to 85°C) compensation allows this bandgap reference to achieve a
nn Long-Term Drift (LS8): 20ppm/√kHr drift of less than 2ppm/°C with a predictable temperature
nn 100% Tested at –40°C, 25°C and 125°C characteristic and an output voltage accurate to ±0.025%,
nn Load Regulation: <10ppm/mA reducing or eliminating the need for calibration.
nn Sinks and Sources Current: ±5mA
The LTC6655LN Low Noise comes with a noise reduction
nn Low Dropout: 500mV
pin that enables reduction of wideband noise with the
nn Maximum Supply Voltage: 13.2V
addition of a single capacitor.
nn Low Power Shutdown: <20µA Max
nn Available Output Voltages: 1.25V, 2.048V, 2.5V, 3V, The LTC6655 can be powered from as little as 500mV
3.3V, 4.096V, 5V above the output voltage to as much as 13.2V. Superior
nn Available in an 8-Lead MSOP and High Stability load regulation with source and sink capability, coupled
Hermetic 5mm × 5mm LS8 Packages with exceptional line rejection, ensures consistent per-
formance over a wide range of operating conditions. A
APPLICATIONS shutdown mode is provided for low power applications.
nn Instrumentation and Test Equipment The LTC6655 references are offered in an 8-lead MSOP
nn High Resolution Data Acquisition Systems package and an 8-lead LS8 package. The LS8 is a
nn Weigh Scales 5mm × 5mm surface mount hermetic package that pro-
nn Precision Battery Monitors vides outstanding stability.
nn Precision Regulators All registered trademarks and trademarks are the property of their respective owners.
nn Medical Equipment

TYPICAL APPLICATION
Basic Connection
LTC6655-2.5
Low Frequency 0.1Hz to 10Hz Noise (LTC6655-2.5)
3V < VIN ≤ 13.2V VIN VOUT_F VOUT
CIN SHDN VOUT_S
0.1µF COUT
GND 10µF
6655 TA01a

500nV/DIV
Basic Connection with Noise Reduction
LTC6655LN-2.5
3V < VIN ≤ 13.2V VIN VOUT VOUT
CIN SHDN NR COUT
0.1µF 10µF 6655 TA01b
GND CNR 1s/DIV
10µF 6655 TA01c

Rev. G

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LTC6655/LTC6655LN
ABSOLUTE MAXIMUM RATINGS (Note 1)

Input Voltage Operating Temperature Range (Note 2).. –40°C to 125°C

VIN to GND........................................... –0.3V to 13.2V Storage Temperature Range (Note 2)...... –65°C to 150°C
SHDN to GND............................ –0.3V to (VIN + 0.3V) Lead Temperature Range (Soldering, 10 sec)
Output Voltage: (Note 3).................................................................. 300°C
VOUT_F....................................... –0.3V to (VIN + 0.3V)
VOUT_S...................................................... –0.3V to 6V
NR............................................................ –0.3V to 6V
Output Short-Circuit Duration....................... Indefinite

PIN CONFIGURATION
LTC6655 LTC6655LN
TOP VIEW TOP VIEW
SHDN 1 8 GND SHDN 1 8 GND
VIN 2 7 VOUT_F VIN 2 7 VOUT_F
GND 3 6 VOUT_S GND 3 6 NR
GND 4 5 GND GND 4 5 GND
MS8 PACKAGE MS8 PACKAGE
8-LEAD PLASTIC MSOP 8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 300°C/W TJMAX = 150°C, θJA = 300°C/W
STAR ALL GND CONNECTIONS AT PIN 4 STAR ALL GND CONNECTIONS AT PIN 4

LTC6655
TOP VIEW
GND

8
SHDN 1 7 VOUT_F

VIN 2 6 VOUT_S

GND 3 5 GND
4

GND
LS8 PACKAGE
8-PIN LEADLESS CHIP CARRIER (5mm × 5mm)
TJMAX = 150°C, θJA = 120°C/W
STAR ALL GND CONNECTIONS AT PIN 4

Rev. G

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 LTC6655/LTC6655LN
ORDER INFORMATION
PART
LEAD FREE FINISH TAPE AND REEL MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6655BHMS8-1.25#PBF LTC6655BHMS8-1.25#TRPBF LTFDG 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-1.25#PBF LTC6655CHMS8-1.25#TRPBF LTFDG 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-2.048#PBF LTC6655BHMS8-2.048#TRPBF LTFDH 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-2.048#PBF LTC6655CHMS8-2.048#TRPBF LTFDH 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-2.5#PBF LTC6655BHMS8-2.5#TRPBF LTFCY 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-2.5#PBF LTC6655CHMS8-2.5#TRPBF LTFCY 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-3#PBF LTC6655BHMS8-3#TRPBF LTFDJ 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-3#PBF LTC6655CHMS8-3#TRPBF LTFDJ 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-3.3#PBF LTC6655BHMS8-3.3#TRPBF LTFDK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-3.3#PBF LTC6655CHMS8-3.3#TRPBF LTFDK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-4.096#PBF LTC6655BHMS8-4.096#TRPBF LTFDM 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-4.096#PBF LTC6655CHMS8-4.096#TRPBF LTFDM 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-5#PBF LTC6655BHMS8-5#TRPBF LTFDN 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-5#PBF LTC6655CHMS8-5#TRPBF LTFDN 8-Lead Plastic MSOP –40°C to 125°C
LTC6655LNBHMS8-2.5#PBF LTC6655LNBHMS8-2.5#TRPBF LTHFK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655LNCHMS8-2.5#PBF LTC6655LNCHMS8-2.5#TRPBF LTHFK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHLS8-2.5 #PBF† N/A 665525 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655CHLS8-2.5 #PBF† N/A 665525 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655BHLS8-4.096#PBF† N/A 554096 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655CHLS8-4.096#PBF† N/A 554096 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655BHLS8-5 #PBF† N/A 66555 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655CHLS8-5 #PBF† N/A 66555 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
†This product is only offered in trays.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev. G

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LTC6655/LTC6655LN
AVAILABLE OPTIONS
OUTPUT VOLTAGE INITIAL ACCURACY TEMPERATURE COEFFICIENT PART NUMBER†
1.250 0.025% 2ppm/°C LTC6655BHMS8-1.25
0.05% 5ppm/°C LTC6655CHMS8-1.25
2.048 0.025% 2ppm/°C LTC6655BHMS8-2.048
0.05% 5ppm/°C LTC6655CHMS8-2.048
2.500 0.025% 2ppm/°C LTC6655BHMS8-2.5
0.05% 5ppm/°C LTC6655CHMS8-2.5
0.025% 2ppm/°C LTC6655BHLS8-2.5
0.05% 5ppm/°C LTC6655CHLS8-2.5
0.025% 2ppm/°C LTC6655LNBHMS8-2.5
0.05% 5ppm/°C LTC6655LNCHMS8-2.5
3.000 0.025% 2ppm/°C LTC6655BHMS8-3.0
0.05% 5ppm/°C LTC6655CHMS8-3.0
3.300 0.025% 2ppm/°C LTC6655BHMS8-3.3
0.05% 5ppm/°C LTC6655CHMS8-3.3
4.096 0.025% 2ppm/°C LTC6655BHMS8-4.096
0.05% 5ppm/°C LTC6655CHMS8-4.096
0.025% 2ppm/°C LTC6655BHLS8-4.096
0.05% 5ppm/°C LTC6655CHLS8-4.096
5.000 0.025% 2ppm/°C LTC6655BHMS8-5
0.05% 5ppm/°C LTC6655CHMS8-5
0.025% 2ppm/°C LTC6655BHLS8-5
0.05% 5ppm/°C LTC6655CHLS8-5
†See Order Information section for complete part number listing.

Rev. G

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 LTC6655/LTC6655LN
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT + 0.5V, VOUT_S connected to VOUT_F , unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage LTC6655B –0.025 0.025 %
LTC6655C –0.05 0.05 %
Output Voltage Temperature Coefficient LTC6655B l 1 2 ppm/°C
(Note 4) LTC6655C l 2.5 5 ppm/°C
Line Regulation VOUT + 0.5V ≤ VIN ≤ 13.2V, SHDN = 2V 5 25 ppm/V
l 40 ppm/V
Load Regulation (Note 5) ISOURCE = 5mA LTC6655MS8 3 ppm/mA
l 15 ppm/mA
LTC6655LS8 3 ppm/mA
l 15 ppm/mA
LTC6655LNMS8 6 ppm/mA
l 20 ppm/mA
ISINK = 5mA LTC6655MS8 10 ppm/mA
l 30 ppm/mA
LTC6655LS8 20 ppm/mA
l 45 ppm/mA
LTC6655LNMS8 14 ppm/mA
l 35 ppm/mA
Operating Voltage (Note 6) LTC6655-1.25, LTC6655-2.048, LTC6655-2.5
ISOURCE = 5mA, VOUT Error ≤ 0.1% l 3 13.2 V
LTC6655-3, LTC6655-3.3, LTC6655-4.096, LTC6655-5
ISOURCE = ±5mA, VOUT Error ≤ 0.1% l VOUT + 0.5 13.2 V
IOUT = 0mA, VOUT Error ≤ 0.1% l VOUT + 0.2 13.2 V
Output Short-Circuit Current Short VOUT to GND 20 mA
Short VOUT to VIN 20 mA
Shutdown Pin (SHDN) Logic High Input Voltage l 2.0 V
Logic High Input Current, SHDN = 2V l 12 µA
Logic Low Input Voltage l 0.8 V
Logic Low Input Current, SHDN = 0.8V l 15 µA
Supply Current No Load 5 7 mA
l 7.5 mA
Shutdown Current SHDN Tied to GND l 20 µA

Rev. G

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LTC6655/LTC6655LN
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT + 0.5V, VOUT_S connected to VOUT_F , unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Noise (Note 7) LTC6655
0.1Hz ≤ f ≤ 10Hz 0.25 ppmP-P
10Hz ≤ f ≤ 1kHz 0.67 ppmRMS
LTC6655LN
0.1Hz ≤ f ≤ 10Hz, CNR = 100µF 0.12 ppmP-P
10Hz ≤ f ≤ 1kHz, CNR = 100µF 0.21 ppmRMS
Turn-On Time 0.1% Settling, COUT = 2.7µF 400 µs
Long-Term Drift of Output Voltage (Note 8) LTC6655MS8 60 ppm/√kHr
LTC6655LS8 20 ppm/√kHr
Hysteresis (Note 9) LTC6655MS8
∆T = 0°C to 70°C 20 ppm
∆T = –40°C to 85°C 30 ppm
∆T = –40°C to 125°C 60 ppm
LTC6655LS8
∆T = 0°C to 70°C 5 ppm
∆T = –40°C to 85°C 30 ppm
∆T = –40°C to 125°C 80 ppm

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Precision may be affected if the parts are stored outside of the
specified temperature range. Large temperature changes may cause
changes in device performance due to thermal hysteresis. For best
performance, extreme temperatures should be avoided whenever possible.
Note 3: The stated temperature is typical for soldering of the leads during
manual rework. For detailed IR reflow recommendations, refer to the
Applications Information section.
Note 4: Temperature coefficient is measured by dividing the maximum
change in output voltage by the specified temperature range.
Note 5: Load regulation is measured on a pulse basis from no load to
the specified load current. Load current does not include the 2mA sense
current. Output changes due to die temperature change must be taken into
account separately.
Note 6: Excludes load regulation errors. Minimum supply for the
LTC6655‑1.25, LTC6655-2.048 and LTC6655-2.5 is set by internal
circuitry supply requirements, regardless of load condition. Minimum
supply for the LTC6655-3, LTC6655-3.3, LTC6655-4.096 and LTC6655-5
is specified by load current.
Note 7: Peak-to-peak noise is measured with a 2-pole highpass filter at
0.1Hz and 3-pole lowpass filter at 10Hz. The unit is enclosed in a still-air
environment to eliminate thermocouple effects on the leads, and the
test time is 10 seconds. Due to the statistical nature of noise, repeating
noise measurements will yield larger and smaller peak values in a given
measurement interval. By repeating the measurement for 1000 intervals,
each 10 seconds long, it is shown that there are time intervals during
which the noise is higher than in a typical single interval, as predicted by
statistical theory. In general, typical values are considered to be those for
which at least 50% of the units may be expected to perform similarly or
better. For the 1000 interval test, a typical unit will exhibit noise that is
less than the typical value listed in the Electrical Characteristics table in
more than 50% of its measurement intervals. See Application Note 124 for
noise testing details. RMS noise is measured with a spectrum analyzer in a
shielded environment.
Note 8: Long-term stability typically has a logarithmic characteristic and
therefore, changes after 1000 hours tend to be much smaller than before
that time. Total drift in the second thousand hours is normally less than
one-third that of the first thousand hours with a continuing trend toward
reduced drift with time. Long-term stability is also affected by differential
stresses between the IC and the board material created during board
assembly.
Note 9: Hysteresis in output voltage is created by mechanical stress
that differs depending on whether the IC was previously at a higher or
lower temperature. Output voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis is roughly proportional to the square of the
temperature change. For instruments that are stored at well controlled
temperatures (within 20 or 30 degrees of operational temperature),
hysteresis is usually not a significant error source. Typical hysteresis is the
worst case of 25°C to cold to 25°C or 25°C to hot to 25°C, preconditioned
by one thermal cycle.

Rev. G

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 LTC6655/LTC6655LN
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.

1.25V Low Frequency 1.25V Output Voltage

0.1Hz to 10Hz Noise Temperature Drift 1.25V Load Regulation (Sourcing)
1.2504 20
3 TYPICAL UNITS 125°C
25°C

OUTPUT VOLTAGE CHANGE (ppm)

10 –40°C
1.2502

OUTPUT VOLTAGE (V)

0

200nV/ 1.2500 –10

DIV

–20
1.2498
–30

6655 G01
1.2496 –40
1s/DIV –50 –25 0 25 50 75 100 125 0.001 0.01 0.1 1 10
TEMPERATURE (°C) OUTPUT CURRENT (mA)
6655 G03
6655 G02

1.25V Output Voltage Noise 1.25V Sinking Current with a

1.25V Load Regulation (Sinking) Spectrum 3.3µF Output Capacitor
200 40
125°C
25°C 35
OUTPUT VOLTAGE CHANGE (ppm)

160 –40°C
5mA
30 IOUT
NOISE VOLTAGE (nV/√Hz)

0mA
120 25

20
VOUT
80 15 10mV/DIV

10
40
2.7µF COUT = 3.3µF 200µs/DIV 6655 G06
5 10µF
100µF
0 0
0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000
OUTPUT CURRENT (mA) FREQUENCY (kHz)
6655 G04 6655 G05

1.25V Sourcing Current with a 1.25V Shutdown Supply Current

3.3µF Output Capacitor vs Input Voltage 1.25V VOUT Distribution
14 60
125°C TA = 25°C
25°C
12 50
–40°C
0mA
IOUT
SUPPLY CURRENT (µA)

–5mA 10
NUMBER OF PARTS

40
8
30
VOUT 6
10mV/DIV
20
4

COUT = 3.3µF 200µs/DIV 6655 G07

2 10

0 0
0 2 4 6 8 10 12 14 1.2495 1.2498 1.2500 1.2503 1.2505
INPUT VOLTAGE (V) VOUT (V)
6655 G08 6655 G09

Rev. G

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LTC6655/LTC6655LN
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.

2.5V Low Frequency 2.5V Output Voltage

0.1Hz to 10Hz Noise Temperature Drift 2.5V Load Regulation (Sourcing)
2.5010 10
3 TYPICAL UNITS

OUTPUT VOLTAGE CHANGE (ppm)

2.5005

OUTPUT VOLTAGE (V)

–10

500nV/ 2.5000 –20

DIV

–30
2.4995
–40 125°C
25°C
–40°C
6655 G10 2.4990 –50
1s/DIV –50 0 50 100 150 0.001 0.01 0.1 1 10
TEMPERATURE (°C) OUTPUT CURRENT (mA) 6655 G12
6655 G11

2.5V Supply Current 2.5V Shutdown Supply Current

2.5V Load Regulation (Sinking) vs Input Voltage vs Input Voltage
160 8 14
125°C
140 25°C 7
–40°C 12
OUTPUT VOLTAGE CHANGE (ppm)

120
6
SUPPLY CURRENT (mA)

SUPPLY CURRENT (µA) 10

100
5
80 8
4
60 6
3
40
4
20 2
125°C 125°C
1 25°C 2
0 25°C
–40°C –40°C
–20 0 0
0.001 0.01 0.1 1 10 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
OUTPUT CURRENT (mA) 6655 G13
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
6655 G14 6655 G15

2.5V Minimum VIN – VOUT 2.5V Minimum VIN – VOUT 2.5V Output Voltage Noise
Differential (Sourcing) Differential (Sinking) Spectrum
10 120
10
COUT = 2.7µF
100
OUTPUT CURRENT (mA)

NOISE VOLTAGE (nV√Hz)

OUTPUT CURRENT (mA)

1 80 COUT = 10µF
1

COUT = 100µF
60

0.1 0.1 40

125°C 125°C 20
25°C 25°C
–40°C –40°C
0.01 0.01 0
0.01 0.1 1 –0.15 –0.05 0.05 0.15 0.01 0.1 1 10 100 1000
INPUT – OUTPUT VOLTAGE (V) INPUT – OUTPUT VOLTAGE (V) 6655 G17
FREQUENCY (kHz)
6655 G16 6655 F01

Rev. G

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 LTC6655/LTC6655LN
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.

2.5V Temperature Drift 2.5V SHDN Input Voltage

2.5V VOUT Distribution Distribution Thresholds vs VIN
100 14 2.5
TA = 25°C –40°C TO 125°C
90
12
80 2.0
70 10 VTH_UP
NUMBER OF PARTS

NUMBER OF PARTS
60 1.5

VTRIP (V)
8
50
VTH_DN
40 6 1.0
30 4
20 0.5
2
10
0 0 0.0
2.4992 2.4996 2.5000 2.5004 2.5008 0 0.4 0.8 1.2 1.6 2 2.4 2.8 2 4 6 8 10 12 14
VOUT (V) DRIFT (ppm/C) VIN (V) 6655 G21
6655 G19 6655 G20

2.5V Power Supply Rejection 2.5V Output Impedance

Ratio vs Frequency vs Frequency 2.5V Line Regulation
120 10 2.502
COUT = 2.7µF
POWER SUPPLY REJECTION RATIO (dB)

COUT = 10µF
100 COUT = 100µF
2.501
OUTPUT IMPEDENCE (Ω)

OUTPUT VOLTAGE (V)

80 1

60 2.500

40 0.1
2.499
20 COUT = 2.7µF 125°C
COUT = 10µF 25°C
COUT = 100µF –40°C
0 0.01 2.498
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000 0 2 4 6 8 10 12 14
FREQUENCY (kHz) 6655 G22
FREQUENCY (kHz) INPUT VOLTAGE (V)
6655 G23 6655 G24

Rev. G

For more information www.analog.com 9

LTC6655/LTC6655LN
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.

5V Low Frequency 5V Output Voltage

0.1Hz to 10Hz Noise Temperature Drift 5V Load Regulation (Sourcing)
5.0010 10
3 TYPICAL UNITS

OUTPUT VOLTAGE CHANGE (ppm)

5.0005

OUTPUT VOLTAGE (V)

–10
5.0000
500nV/ –20
DIV
4.9995
–30

4.9990
–40 125°C
25°C
–40°C
6655 G25
4.9985 –50
1s/DIV –50 –25 0 25 50 75 100 125 0.01 0.1 1 10
TEMPERATURE (°C) OUTPUT CURRENT (mA)
6655 G26 6655 G27

5V Supply Current 5V Output Voltage Noise

5V Load Regulation (Sinking) vs Input Voltage Spectrum
100 6 200
125°C
25°C 180
80 5
OUTPUT VOLTAGE CHANGE (ppm)

–40°C
160
NOISE VOLTAGE (nV/√Hz)
SUPPLY CURRENT (mA)

140
60 4
120
40 3 100
80
20 2 60
40
0 1 125°C 2.7µF
25°C 20 10µF
–40°C 100µF
–20 0 0
0.01 0.1 1 10 0 2 4 6 8 10 12 14 0.01 0.1 1 10 100 1000
OUTPUT CURRENT (mA) INPUT VOLTAGE (V) FREQUENCY (kHz)
6655 G28 6655 G29 6655 G30

5V Minimum VIN-VOUT 5V Minimum VIN-VOUT 5V Start-Up Response with a

Differential (Sourcing) Differential (Sinking) 3.3µF Output Capacitor
10 10

VIN
2V/DIV
OUTPUT CURRENT (mA)

OUTPUT CURRENT (mA)

1 1

VOUT
2V/DIV
0.1 0.1

125°C 125°C COUT = 3.3µF 400µs/DIV 6655 G33

25°C 25°C
–40°C –40°C
0.01 0.01
0.01 0.1 1 –0.3 –0.2 –0.1 0 0.1
INPUT-OUTPUT VOLTAGE (V) INPUT-OUTPUT VOLTAGE (V)
6655 G31 6655 G32
Rev. G

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 LTC6655/LTC6655LN
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves shown below are the LTC6655NL option.

LTC6655LN-2.5 Output Voltage LTC6655LN-2.5 Output

Noise Spectrum Integrated Noise
70 5
COUT = 2.7µF COUT = 2.7µF
60
4

INTEGRATED NOISE (µVRMS)

CNR = 10µF
NOISE VOLTAGE (nV/√Hz)

50 CNR = 0.1µF
CNR = 1µF
CNR = 0.1µF 3
40
CNR = 1µF
30
2
CNR = 10µF
20
1
10
CNR = 100µF
CNR = 100µF
0 0
0.01 0.1 1 10 100 1k 0.01 0.1 1 10
FREQUENCY (kHz) FREQUENCY (kHz)
6655 G34 6655 G35

LTC6655LN-2.5 Effect of NR Pin

Leakage on VOUT
1000
800
600
CHANGE IN VOUT (µV)

400
200
0
–200
–400
–600
–800
–1000
–1000 –750 –500 –250 0 250 500 750 1000
CURRENT INJECTED INTO THE NR PIN (nA)

6655 G36

Rev. G

For more information www.analog.com 11

LTC6655/LTC6655LN
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. This active low input
powers down the device to <20µA. If left open, an internal
pull-up resistor puts the part in normal operation. It is
recommended to tie this pin high externally for best
performance during normal operation.
VIN (Pin 2): Power Supply. Bypass VIN with a 0.1µF, or
larger, capacitor to GND.
GND (Pin 4): Device Ground. This pin is the main ground
and must be connected to a noise-free ground plane.
VOUT_S (Pin 6 – LTC6655): VOUT Sense Pin. Connect
this pin at the load and route with a wide metal trace
to minimize load regulation errors. This pin sinks 2mA.
Output error is RTRACE • 2mA, regardless of load current.
For load currents <100µA, tie directly to VOUT_F pin.
NR (Pin 6 – LTC6655LN): Noise Reduction Pin. To band
limit noise, connect a capacitor between this pin and
ground. See Applications Information section.
VOUT_F (Pin 7 – LTC6655): VOUT Force Pin. This pin
sources and sinks current to the load. An output capacitor
of 2.7µF to 100µF is required.
VOUT_F (Pin 7 – LTC6655LN): VOUT Pin. This pin sources
and sinks current to the load. An output capacitor of 2.7µF
to 100µF is required.
GND (Pins 3, 5, 8): Internal Function. Ground these pins.

BLOCK DIAGRAM
LTC6655
VIN
2

+
SHDN VOUT_F
1 BANDGAP 7

–
VOUT_S
6

GND
4 6655 BD

GND
3,5,8

LTC6655LN
NR
6
VIN
2

+
SHDN VOUT_F
1 BANDGAP 7

GND
4 6655LN BD

GND
3,5,8
Rev. G

12 For more information www.analog.com


APPLICATIONS INFORMATION
Bypass and Load Capacitors
The LTC6655 voltage references require a 0.1µF or larger
input capacitor located close to the part to improve power
supply rejection. An output capacitor with a value between
2.7µF and 100µF is also required.
The output capacitor has a direct effect on the stability,
turn-on time and settling behavior. Choose a capacitor
with low ESR to insure stability. Resistance in series
with the output capacitor (ESR) introduces a zero in the
output buffer transfer function and could cause instabil-
ity. The 2.7μF to 100μF range includes several types of
capacitors that are readily available as through-hole and
surface mount components. It is recommended to keep
ESR less than or equal to 0.1Ω. Capacitance and ESR are
both frequency dependent. At higher frequencies capaci-
tance drops and ESR increases. To insure stable operation
the output capacitor should have the required values at
100kHz.
In order to achieve the best performance, caution should
be used when choosing a capacitor. X7R ceramic capaci-
tors are small, come in appropriate values and are rela-
tively stable over a wide temperature range. However,
for a low noise application X7R capacitors may not be
suitable since they may exhibit a piezoelectric effect. The
mechanical vibrations cause a charge displacement in the
ceramic dielectric and the resulting perturbation can look
like noise. If X7R capacitors are necessary, a thorough
bench evaluation should be completed to verify proper
performance.
Table 1. Film Capacitor Companies
COMPANY DIELECTRIC AVAILABLE CAPACITANCE
Cornell Dublier Polyester
Dearborn Electronics Polyester
Tecate Polyester
Wima Polyester
Vishay Polyester
Vishay Polycarbonate
Dearborn Electronics Polyphenylene Sulfide (PPS)
Wima Polyphenylene Sulfide (PPS)
For more information www.analog.com
LTC6655/LTC6655LN
For very low noise applications where every nanovolt
counts, film capacitors should be considered for their
low noise and lack of piezoelectric effects. Film capaci-
tors such as polyester, polystyrene, polycarbonate, and
polypropylene have good temperature stability. Additional
care must be taken as polystyrene and polypropylene have
an upper temperature limit of 85°C to 105°C. Above these
temperatures, the working voltages need to be derated
according to manufacturer’s specifications. Another type
of film capacitor is polyphenylene sulfide (PPS). These
devices work over a wide temperature range, are stable,
and have large capacitance values beyond 1μF. In general,
film capacitors are found in surface mount and leaded
packages. Table 1 is a partial list of capacitor companies
and some of their available products.
In voltage reference applications, film capacitor lifetime is
affected by temperature and applied voltage. When poly-
ester capacitors are operated beyond their rated tempera-
tures (some capacitors are not rated for operation above
85°C) they need to be derated. Voltage derating is usually
accomplished as a ratio of applied voltage to rated volt-
age limit. Contact specific film capacitor manufacturers to
determine exact lifetime and derating information.
The lifetime of X7R capacitors is long, especially for refer-
ence applications. Capacitor lifetime is degraded by oper-
ating near or exceeding the rated voltage, at high tem-
perature, with AC ripple or some combination of these.
Most reference applications have AC ripple only during
transient events.
TEMPERATURE RANGE TYPE
0.5µF to 10µF –55°C to 125°C DME
0.1µF to 12µF –55°C to 125°C 218P, 430P, 431P, 442P, and 410P
0.01µF to 18µF –40°C to 105°C 901, 914, and 914D
10µF to 22µF –55°C to 100°C MKS 4, MKS 2-XL
1000pF to 15µF –55°C to 125°C MKT1820
0.01µF to 10µF –55°C to 100°C MKC1862, 632P
0.01µF to 15µF –55°C to 125°C 820P, 832P, 842P, 860P, and 880P
0.01µF to 6.8µF –55°C to 140°C SMD-PPS
Rev. G
13
LTC6655/LTC6655LN
APPLICATIONS INFORMATION
The choice of output capacitor also affects the bandwidth 120

of the reference circuitry and resultant noise peaking. As 100

COUT = 2.7µF

shown in Figure 1, the bandwidth is inversely proportional

NOISE VOLTAGE (nV√Hz)

to the value of the output capacitor. 80 COUT = 10µF

Noise peaking is related to the phase margin of the out- 60

COUT = 100µF

put buffer. Higher peaking generally indicates lower phase

margin. Other factors affecting noise peaking are tem- 40

perature, input voltage, and output load current. 20

Start-Up and Load Transient Response 0

0.01 0.1 1 10 100 1000
Results for the transient response plots (Figures 3 to 8) FREQUENCY (kHz)
6655 F01

were produced with the test circuit shown in Figure 2 Figure 1. Output Voltage Noise Spectrum
unless otherwise indicated.
The turn-on time is slew limited and determined by the VOUT 100Ω
7
short-circuit current, the output capacitor, and output volt- VIN 1,2
LTC6655-2.5 6
age as shown in the equation: 3V
CIN COUT VGEN 0.5V
0.1µF 3.3µF
6655 F02
3,4,5,8
COUT
tON = VOUT •
ISC Figure 2. Transient Load Test Circuit

For example, the LTC6655-2.5V, with a 3.3µF output
capacitor and a typical short-circuit current of 20mA, the
start-up time would be approximately: VIN
2V/DIV

3.3 • 10 –6 F
2.5V • = 412µs
0.02A VOUT
1V/DIV

The resulting turn-on time is shown in Figure 3. Here the

output capacitor is 3.3µF and the input capacitor is 0.1µF. 6655 F03
COUT = 3.3µF 200µs/DIV
Figure 4 shows the output response to a 500mV step on
VIN. The output response to a current step sourcing and Figure 3. Start-Up Response
sinking is shown in Figures 5 and 6, respectively.
Figure 7 shows the output response as the current goes
3.5V
from sourcing to sinking. VIN
3V

Shutdown Mode
The LTC6655 family of references can be shut down by
VOUT
tying the SHDN pin to ground. There is an internal pull-up 50mV/DIV
resistor tied to this pin. If left unconnected this pin rises to
VIN and the part is enabled. Due to the low internal pull-up 6655 F04
COUT = 3.3µF 400µs/DIV
current, it is recommended that the SHDN pin be pulled
high externally for normal operation to prevent accidental Figure 4. Output Response with a 500mV Step On VIN

Rev. G

14 For more information www.analog.com

 LTC6655/LTC6655LN
APPLICATIONS INFORMATION
0mA
shutdown due to system noise or leakage currents. The
IOUT
–5mA
turn-on/turn-off response due to shutdown is shown in
Figure 8.
To control shutdown from a low voltage source, a MOSFET
VOUT
can be used as a pull-down device as shown in Figure 9.
10mV/DIV Note that an external resistor is unnecessary. A MOSFET
with a low drain-to-source leakage over the operating tem-
COUT = 3.3µF 200µs/DIV
6655 F05
perature range should be chosen to avoid inadvertently
pulling down the SHDN pin. A resistor may be added from
Figure 5. Output Response with a 5mA Load Step Sourcing
SHDN to VIN to overcome excessive MOSFET leakage.
The SHDN thresholds have some dependency on VIN
5mA
IOUT and temperature as shown in the Typical Performance
0mA
Characteristics section. Avoid leaving SHDN at a voltage
between the thresholds as this will cause an increase in
supply current due to shoot-through current.
VOUT
10mV/DIV
3V ≤ VIN ≤ 13.2V
C1
1µF VIN
6655 F06 VOUT_F VOUT
COUT = 3.3µF 200µs/DIV
LTC6655-2.5
C2
Figure 6. Output Response with 5mA Load Step Sinking SHDN GND VOUT_S 10µF
TO µC 2N7002

6655 F09

2mA
IOUT Figure 9. Open-Drain Shutdown Circuit
–2mA

Long-Term Drift
VOUT
10mV/DIV
Long-term drift cannot be extrapolated from accelerated
high temperature testing. This erroneous technique gives
6655 F07
drift numbers that are wildly optimistic. The only way
COUT = 3.3µF 200µs/DIV
long-term drift can be determined is to measure it over
Figure 7. Output Response Showing a the time interval of interest.
Sinking to Sourcing Transition
The LTC6655 long-term drift data was collected on 80
parts that were soldered into printed circuit boards similar
to a real world application. The boards were then placed
SHDN
2V/DIV
into a constant temperature oven with a TA = 35°C, their
outputs were scanned regularly and measured with an
8.5 digit DVM. Typical long-term drift is illustrated in
VOUT Figure 10a. The hermetic LS8 package provides additional
1V/DIV
stability as shown in Figure 10b.

6655 F08
COUT = 3.3µF 1ms/DIV

Figure 8. Shutdown Response with 5mA Source Load

Rev. G

For more information www.analog.com 15

LTC6655/LTC6655LN
APPLICATIONS INFORMATION
120 30
4 TYPICAL UNITS
LTC6655-2.5
MS8 PACKAGE 25
80
LONG-TERM DRIFT (ppm)

NUMBER OF UNITS
20
40
15
0
10

–40
5

–80 0
0 500 1000 1500 2000 2500 –90 –70 –50 –30 –10 10 30 50 70 90 110
HOURS DISTRIBUTION (ppm)
6655 F11
6655 F10a

Figure 10a. Long-Term Drift MS8 Figure 11. Hysteresis Plot –40°C to 125°C

200
concern. However, PC board material may absorb water
LTC6655-2.5
160 LS8 PACKAGE
and apply mechanical stress to the LTC6655LS8. Proper
120 board materials and layout are essential.
LONG-TERM DRIFT (ppm)

80
For best stability, the PC board layout is critical. Change
40
in temperature and position of the PC board, as well as
0
aging, can alter the mechanical stress applied to compo-
–40
nents soldered to the board. FR4 and similar materials
–80
–120
also absorb water, causing the board to swell. Even con-
–160
formal coating or potting of the board does not always
–200
eliminate this effect, though it may delay the symptoms
0 600 1200 1800 2400 3000 by reducing the rate of absorption.
HOURS
6655 F10b
Power and ground planes should be omitted under the
Figure 10b. Long-Term Drift LS8 voltage reference IC for best stability. Figure 12a shows
a tab cut through the PC board on three sides of an
Hysteresis LTC6655, which significantly reduces stress on the IC,
Thermal hysteresis is a measure of change of output as described in Application Note 82. For even better per-
voltage as a result of temperature cycling. Figure  11 formance, Figure 12b shows slots cut through the PC
illustrates the typical hysteresis based on data taken from board on all four sides. The slots should be as long as
the LTC6655-2.5. A proprietary design technique mini- possible, and the corners just large enough to accom-
mizes thermal hysteresis. modate routing of traces. It has been shown that for PC
boards designed in this way, humidity sensitivity can
Humidity Sensitivity be reduced to less than 35ppm for a change in relative
humidity of approximately 60%. Mounting the reference
Plastic mould compounds absorb water. With changes in
near the center of the board, with slots on four sides, can
relative humidity, plastic packaging materials change the
further reduce the sensitivity to less than 10ppm.
amount of pressure they apply to the die inside, which
can cause slight changes in the output of a voltage refer- An additional advantage of slotting the PC board is that the
ence, usually on the order of 100ppm. The LS8 package is LTC6655 is thermally isolated from surrounding circuitry.
hermetic, so it is not affected by humidity, and is therefore This can help reduce thermocouple effects and improve
more stable in environments where humidity may be a accuracy.
Rev. G

16 For more information www.analog.com

 LTC6655/LTC6655LN
APPLICATIONS INFORMATION
0.14

0.12
5mA LOAD
0.10

POWER (W)
LS8 0.08

0.06
NO LOAD

0.04

0.02
6655 F12a

0
Figure 12a. 3-Sided PCB Tab Cutout 0 5 10 15
VIN (V)
6655 F13

Figure 13. LTC6655-2.5 Power Consumption

125

115
NO LOAD
OPERATING TEMPERATURE (°C)
LS8 105
MAXIMUM AMBIENT

5mA LOAD
95

85

75

6655 F12b 65

Figure 12b. 4-Sided PCB Cutout 55

0 3 6 9 12 15
VIN (V)
Power Dissipation 6655 F14

Figure 14. LTC6655-2.5 Maximum

Power dissipation for the LTC6655 depends on VIN and
load current. Figure 13 illustrates the power consump-
tion versus VIN under a no-load and 5mA load condition
at room temperature for the LTC6655-2.5. Other voltage
options display similar behavior.
The MSOP8 package has a thermal resistance (θJA)
equal to 300°C/W. Under the maximum loaded condition,
the increase in die temperature is over 35°C. If operated
at these conditions with an ambient temperature of 125°C,
the absolute maximum junction temperature rating of
the device would be exceeded. Although the maximum
junction temperature is 150°C, for best performance it
is recommended to not exceed a junction temperature
of 125°C. The plot in Figure 14 shows the recommended
Ambient Operating Temperature
maximum ambient temperature limits for differing VIN and
load conditions using a maximum junction temperature
of 125°C.
PC Board Layout
The LTC6655 reference is a precision device that is fac-
tory trimmed to an initial accuracy of ±0.025%, as shown
in the Typical Performance Characteristics section. The
mechanical stress caused by soldering parts to a printed
circuit board may cause the output voltage to shift and
the temperature coefficient to change.

Rev. G

For more information www.analog.com 17

LTC6655/LTC6655LN
APPLICATIONS INFORMATION
To reduce the effects of stress-related shifts, mount the The VOUT_S pin sinks 2mA, which is unusual for a Kelvin
reference near the short edge of a printed circuit board connection. However, this is required to achieve the
or in a corner. In addition, slots can be cut into the board exceptional low noise performance. The I • R drop on the
on two sides of the device to reduce mechanical stress. VOUT_S line directly affects load regulation. The VOUT_S
A thicker and smaller board is stiffer and less prone to trace should be as short and wide as practical to minimize
bend. Finally, use stress relief, such as flexible standoffs, series resistance The VOUT_S trace adds error as RTRACE
when mounting the board. • 2mA, so a 0.1Ω trace adds 200µV error. The VOUT_F pin
is not as important as the VOUT_S pin in this regard. An
Additional precautions include making sure the solder
I • R drop on the VOUT_F pin increases the minimum supply
joints are clean and the board is flux free to avoid leak-
voltage when sourcing current, but does not directly affect
age paths. Sample PCB layouts are shown in Figures 15a
load regulation. For light loading of the output (maximum
and 15b.
output current <100µA), VOUT_S should be tied to VOUT_F
VIN
by the shortest possible path to reduce errors caused by
resistance in the sense trace.
Careful attention to grounding is also important, espe-
cially when sourcing current. The return load current can
produce an I • R drop causing poor load regulation. Use
GND VOUT
6655 F15a
a “star” ground connection and minimize the ground to
load metal resistance. Although there are several pins that
Figure 15a. Sample LTC6655 PCB Layout are required to be connected to ground, Pin 4 is the actual
ground for return current.
VOUT
VIN
Optimal Noise Performance
The LTC6655 offers extraordinarily low noise for a band-
gap reference—only 0.25ppm in 0.1Hz to 10Hz. As a
GND result, system noise performance may be dominated by
system design and physical layout.
6655 F15b

Figure 15b. Sample LTC6655LN PCB Layout

Some care is required to achieve the best possible noise
Load Regulation performance. The use of dissimilar metals in compo-
nent leads and PC board traces creates thermocouples.
To take advantage of the VOUT Kelvin force/sense pins, Variations in thermal resistance, caused by uneven air
the VOUT_S pin should be connected separately from the flow, create differential lead temperatures, thereby caus-
VOUT_F pin as shown in Figure 16. ing thermoelectric voltage noise at the output of the refer-
ence. Minimizing the number of thermocouples, as well
7
as limiting airflow, can substantially reduce these errors.
2 6 2mA
+ LTC6655-2.5 LOAD Additional information can be found in Analog Devices
4
STAR Application Note 82. Position the input and load capaci-
6655 F16 tors close to the part. Although the LTC6655 has a DC
MINIMIZE RESISTANCE PSRR of over 100dB, the power supply should be as
OF METAL
stable as possible to guarantee optimal performance. A
Figure 16. Kelvin Connection for Good Load Regulation plot of the 0.1Hz to 10Hz low frequency noise is shown
in the Typical Performance Characteristics section. Noise

Rev. G

18 For more information www.analog.com


APPLICATIONS INFORMATION
performance can be further improved by wiring several
LTC6655s in parallel as shown in the Typical Applications
section. With this technique the noise is reduced by √N,
where N is the number of LTC6655s in parallel.
Noise Specification
Noise in any frequency band is a random function based
on physical properties such as thermal noise, shot noise,
and flicker noise. The most precise way to specify a ran-
dom error such as noise is in terms of its statistics, for
example as an RMS value. This allows for relatively simple
maximum error estimation, generally involving assump-
tions about noise bandwidth and crest factor. Unlike wide-
band noise, low frequency noise, typically specified in
a 0.1Hz to 10Hz band, has traditionally been specified
in terms of expected error, illustrated as peak-to-peak
error. Low frequency noise is generally measured with
an oscilloscope over a 10 second time frame. This is a
pragmatic approach, given that it can be difficult to mea-
sure noise accurately at low frequencies, and that it can
also be difficult to agree on the statistical characteristics
of the noise, since flicker noise dominates the spectral
density. While practical, a random sampling of 10 second
intervals is an inadequate method for representation of
low frequency noise, especially for systems where this
noise is a dominant limit of system performance. Given
the random nature of noise, the output voltage may be
observed over many time intervals, each giving different
results. Noise specifications that were determined using
this method are prone to subjectivity, and will tend toward
a mean statistical value, rather than the maximum noise
that is likely to be produced by the device in question.
Because the majority of voltage reference data sheets
express low frequency noise as a typical number, and as it
tends to be illustrated with a repeatable plot near the mean
of a distribution of peak-to-peak values, the LTC6655 data
sheet provides a similarly defined typical specification in
order to allow a reasonable direct comparison against
similar products. Data produced with this method gener-
ally suggests that in a series of 10 second output voltage
measurements, at least half the observations should have
a peak-to-peak value that is below this number. For exam-
ple, the LTC6655-2.5 measures less than 0.25ppmP-P in
at least 50% of the 10 second observations.
For more information www.analog.com
LTC6655/LTC6655LN
As mentioned above, the statistical distribution of noise
is such that if observed for long periods of time, the
peak error in output voltage due to noise may be much
larger than that observed in a smaller interval. The likely
maximum error due to noise is often estimated using
the RMS value, multiplied by an estimated crest factor,
assumed to be in the range of 6 to 8.4. This maximum
possible value will only be observed if the output volt-
age is measured for very long periods of time. Therefore,
in addition to the common method, a more thorough
approach to measuring noise has been used for the
LTC6655 (described in detail in Analog Devices’s AN124)
that allows more information to be obtained from the
result. In particular, this method characterizes the noise
over a significantly greater length of time, resulting in a
more complete description of low frequency noise. The
peak-to-peak voltage is measured for 10 second intervals
over hundreds of intervals. In addition, an electronic peak-
detect circuit stores an objective value for each interval.
The results are then summarized in terms of the fraction
of measurement intervals for which observed noise is
below a specified level. For example, the LTC6655-2.5
measures less than 0.27ppmP-P in 80% of the measure-
ment intervals, and less than 0.295ppmP-P in 95% of
observation intervals. This statistical variation in noise
is illustrated in Table 2 and Figure 18. The test circuit is
shown in Figure 17.
Table 2.
Low Frequency Noise (ppmP-P)
50% 0.246
60% 0.252
70% 0.260
80% 0.268
90% 0.292
This method of testing low frequency noise is superior to
more common methods. The results yield a comprehen-
sive statistical description, rather than a single observa-
tion. In addition, the direct measurement of output voltage
over time gives an actual representation of peak noise,
rather than an estimate based on statistical assumptions
such as crest factor. Additional information can be derived
from a measurement of low frequency noise spectral den-
sity, as shown in Figure 19.
Rev. G
19
 1N4697 0.1µF

20
15V 0.15µF 10V

+ A = 100 AND
1µF A1 10k 0.1Hz TO 10Hz FILTER
LT1012 0.1µF
– Q3 –
2N2907 15V 2k A4
A = 104 –15V
+ LT1012
–15V 1k* 200Ω* A3 124k* 124k*
LOW NOISE 1µF
LT1012 +
PRE-AMP
1µF 450Ω* 900Ω* 0.1µF
– 1M*
– 330µF
+
9V
100k 100k A2 16V
LT1097
1300µF T 10k*
SHIELD + 330µF
5 16V
S Q1 Q2 0.022µF
+
LTC6655

+
IN 100k* 330Ω* 100Ω*
2.5V F
SD **1.2k
IN OUT 10k
– INPUT
1µF 750Ω* 10Ω* +
330µF ROOT-SUM-SQUARE
LTC6655/LTC6655LN

16V CORRECTION
REFERENCE –15V SEE TEXT
UNDER TEST 330µF
16V
AC LINE GROUND SHIELDED CAN
+
APPLICATIONS INFORMATION

RESET PULSE
GENERATOR
0.22µF 10k
PEAK TO PEAK +15V
4.7k NOISE DETECTOR +15V
C2 RC2
RST = Q2 BAT-85
+V B2
– + 74C221
RST A5 + PEAK A7
1µF P BAT-85
1/4 LT1058 1/4 LT1058
+ –
1k
CLR2 A2 10k +15V
+15V

For more information www.analog.com

10k
–15V + TO OSCILLOSCOPE INPUT
VIA ISOLATED PROBE, FROM OSCILLOSCOPE
0.005µF O TO 1V =
100k 0.1µF DVM 1V/DIV = 1µV/DIV, SWEEP GATE OUTPUT
O TO 1µV
REFERRED TO INPUT, VIA ISOLATION
– SWEEP = 1s/DIV PULSE TRANSFORMER

4.7k + 1k
– PEAK A8 * = 1% METAL FILM Q1, Q2 = THERMALLY MATED
1/4 LT1058 ** = 1% WIREWOUND, ULTRONIX105A 2SK369 (MATCH VGS 10%)
OR LSK389 DUAL T = TANTALUM,WET SLUG
– – = 1N4148 THERMALLY LAG ILEAK < 5nA
RST A6 SEE TEXT SEE TEXT/APPENDIX B
1µF P 100k
1/4 LT1058
= 2N4393 P = POLYPROPELENE
+
A4 330µF OUTPUT CAPACITORS = <200nA LEAKAGE
= 1/4 LTC202 AT 1VDC AT 25°C
10k
15V
SEE APPENDIX C FOR POWER, SHIELDING
0.005µF AND GROUNDING SCHEME 6655 F17

Figure 17. Detailed Noise Test Circuitry. See Application Note 124

Rev. G
 LTC6655/LTC6655LN
APPLICATIONS INFORMATION
35 the typical application circuit with a capacitor on the NR
30 pin. When a capacitor is placed between NR and ground,
a LPF is formed.
NUMBER OF OBSERVATIONS

25

20 2
VIN LTC6655LN
15
R3
VOUT
10 BANDGAP +
7
5
– R1 2.7µF

0
450 550 650 750 850 950 R2
PEAK-TO-PEAK NOISE (nV)
6655 F18
GND NR
6
Figure 18. LTC6655-2.5 Low Frequency Noise Histogram 3, 4, 5, 8 6655 F20

CNR

200

Figure 20. The LTC6655LN Typical Application Circuit

160
NOISE VOLTAGE (nV/√Hz)

The LPF reduces the wide band noise from the bandgap
120
circuit before it reaches the output buffer. This is very
80
different from placing a LPF after the reference. A LPF
following the buffer would cause poor load regulation and
40
slow down the response affecting dynamic performance.
With the LPF internally placed before the low noise buffer,
0 the buffer response is not impeded by the LPF. Placing
0.1 1 10 100
FREQUENCY (Hz)
anything between the output buffer and the converter will
6655 F19 likely add noise or cause an error such as a load regulation
Figure 19. LTC6655-2.5 Low Frequency Noise Spectrum
error, or a dynamic response error.
The value of resistor R3 is slightly different depending
It should be noted from Figure 19 that the LTC6655 has on the voltage option. Tables 3 and 4 below list the resis-
not only a low wideband noise, but an exceptionally low tance values of R3 for the three available voltage options
flicker noise corner of 1Hz! This substantially reduces along with the 3dB cutoff frequencies for four decades of
low frequency noise, as well as long-term variation in capacitor values.
peak noise. Table 3. Resistance Value of R3 for the Three Voltage Options
2.500 4.096 5.000 V
Noise Reduction and the NR Pin
R3 ±15% 5305 4233 3969 Hz
The LTC6655LN provides access to an internal circuit
node preceding the output buffer so that dynamic per- Table 4. The 3dB Cutoff Frequencies for Different Values of CNR
formance is not affected. This facilitates the use of a low CNR 2.500 4.096 5.000 V
pass filter (LPF) to reduce wide band noise.
0.1µF 5305 4233 3969 Hz
The Block Diagram section illustrates the LTC6655LN 1µF 531 423 397 Hz
architectural differences. The Low Noise version trades 10µF 53 423 397 Hz
out the Kelvin sense pin for the NR pin. Figure 20 shows 100µF 5.3 4.2 4.0 Hz
Rev. G

For more information www.analog.com 21

LTC6655/LTC6655LN
APPLICATIONS INFORMATION
Internally the NR pin connects to a sensitive node. Any is reduced to 16nV/√Hz. The noise corner frequency pro-
leakage to this pin can cause excessive shift and drift. duced by the LPF decreases as the capacitor increases.
Leakage of 10nA will cause a shift of 9μV in VOUT. It is A plot of the total integrated noise for the same three
recommended to use high quality, low leakage capacitors. conditions is shown in Figure 22. A large value of CNR can
A guard ring may also be employed to control leakage. have a large impact on the total integrated noise.
The nominal pin voltage of NR is 1.000V or 1.024V.
The LTC6655LN-2.5 output noise for three conditions is Start-Up with CNR
shown in Figure 21. Without a capacitor on the NR pin the The CNR capacitor will require time to charge. The
wideband noise extends past 10kHz at 50nV/√Hz. When LTC6655 has an initial accuracy of 0.025%. A single RC
a 1μF or 100μF capacitor is included, the wideband noise time constant circuit will require approximately 8.3τ to
reach 0.025% settling. For example, assume R3 = 300Ω
70
COUT = 2.7µF and CNR = 10μF; the time constant is R • C = 300Ω • 10μF
60 = 3ms. For 0.025% settling multiply 8.3 • 3ms to get
CNR = 10µF
24.9ms. This is the time required for the signal at the NR
NOISE VOLTAGE (nV/√Hz)

50
CNR = 1µF
pin to settle to 0.025% of its final value. The output buffer
40 CNR = 0.1µF
will follow the NR pin signal with some delay depending
30 on the capacitive loading on the VOUT pin.
20 Example start-up measurements are shown in Figures 23a,
10 23b, and 23c. Figure 23a shows the difference between
CNR = 100µF
using no capacitor and a 1μF capacitor on the NR pin.
0
0.01 0.1 1 10 100 1k Figures 23b and 23c show the start-up with CNR = 10μF
FREQUENCY (kHz)
6655 F21 and 100μF, respectively.
Figure 21. The LTC6655LN-2.5 Output Voltage
Noise Spectrum Using the CNR Capacitor IR Reflow Shift
The mechanical stress of soldering a part to a board can
5
COUT = 2.7µF
cause the output voltage to shift. Moreover, the heat of
an IR reflow or convection soldering oven can also cause
4 the output voltage to shift. The materials that make up a
INTEGRATED NOISE (µVRMS)

CNR = 0.1µF
semiconductor device and its package have different rates
3
CNR = 1µF
of expansion and contraction. After a part undergoes the
extreme heat of a lead-free IR reflow profile, like the one
2
CNR = 10µF shown in Figure 24, the output voltage shifts. After the
1
device expands, due to the heat, and then contracts, the
stresses on the die have changed position. This shift is
0
CNR = 100µF similar, but more extreme than thermal hysteresis.
0.01 0.1 1 10
FREQUENCY (kHz) Experimental results of IR reflow shift are shown below
in Figure 25. These results show only shift due to reflow
6655 F22

Figure 22. Total Integrated Noise of the and not mechanical stress.

LTC6655LN-2.5 Using the CNR Capacitor

Rev. G

22 For more information www.analog.com

 LTC6655/LTC6655LN
APPLICATIONS INFORMATION
VIN 300
5V/DIV 380s
TP = 260°C
CNR = OPEN
RAMP
TL = 217°C DOWN
225
VNR TS(MAX) = 200°C

TEMPERATURE (°C)
500mV/DIV tP
TS = 190°C 30s
150 T = 150°C
CNR = 1µF
VOUT tL
1V/DIV RAMP TO 130s
150°C
COUT = 2.7µF
75
6655 F23a 40s
1ms/DIV
120s
Figure 23a. CNR = Open and 10µF 0
0 2 4 6 8 10
MINUTES 6655 F24
VIN
5V/DIV
Figure 24. Lead-Free Reflow Profile

VNR
500mV/DIV 8

7
VOUT
1V/DIV 6
CNR = 10µF
NUMBER OF UNITS

COUT = 2.7µF 5
6655 F23b
10ms/DIV 4

Figure 23b. CNR = 10µF 3

VIN 1
5V/DIV
0
–0.029 –0.023 –0.017 –0.011 –0.005
VNR OUTPUT VOLTAGE SHIFT DUE TO IR REFLOW (%)
500mV/DIV 6655 F25

Figure 25. Output Voltage Shift Due to IR Reflow

VOUT
1V/DIV CNR = 100µF
COUT = 2.7µF
6655 F23c
50ms/DIV

Figure 23c. CNR = 100µF

Figure 23. The LTC6655LN-2.5 Start-Up Response with a) No
CNR Capacitor and CNR = 1µF, b) CNR = 10µF, and c) CNR = 100µF

Rev. G

For more information www.analog.com 23

LTC6655/LTC6655LN
TYPICAL APPLICATIONS
Extended Supply Range Reference Extended Supply Range Reference

4V TO 30V 6V TO 80V
R1 R2
R1 100k 4.7k ON SEMI
LTC6655-2.5 MMBT5551
VIN VOUT_F VOUT C1
BZX84C12
0.1µF
C1 SHDN VOUT_S C2
BZX84C12 0.1µF
0.1µF 10µF
GND
6655 TA02 VIN SHDN
VOUT_F VOUT
LTC6655-2.5
VOUT_S C2
GND 10µF
6655 TA03

Boosted Output Current Boosted Output Current

4V TO 13.2V VOUT + 1.8V TO 13.2V

C1 R1 C4
1µF 220Ω 1µF
LTC6655-2.5 R2
Q1 1k
SHDN VOUT_F 2N2222 2N2905
C3 35mA MAX
VIN VOUT_S VOUT 0.1µF VIN SHDN
C1 GND C2
0.1µF 4.7µF VOUT_F VOUT
LTC6655-2.5
6655 TA05
IMAX SET BY NPN VOUT_S C2
GND 10µF
6655 TA04

Rev. G

24 For more information www.analog.com

 LTC6655/LTC6655LN
TYPICAL APPLICATIONS
Output Voltage Boost

VIN VOUT
VIN VOUT_F
VOUT + 0.5V TO 13.2V 2.5V TO 4.5V
C1 LTC6655-2.5 R C2
1µF 10µF
SHDN VOUT_S
R = 0k to 1k
GND 6655 TA07

VOUT = VOLTAGE OPTION + 0.002 • R FOR R USE A POTENTIOMETER THAT

THIS EXAMPLE USES 2.5V AS THE CAN HANDLE 2mA, IS LOW NOISE AND
VOLTAGE OPTION HAS A LOW TEMPERATURE COEFFICIENT

Low Noise Precision Voltage Boost Circuit

VIN VOUT
VIN VOUT_F
VOUT + 0.5V TO 13.2V VIN 5V
C1 LTC6655-2.5 C2
1µF LT1677 + + R1 10µF
SHDN VOUT_S 10k
RLOAD
GND
––
R2
10k
R3 6655 TA08

5k
VOUT = VOLTAGE OPTION • (1 + R1/R2) FOR R1, R2 AND R3 USE LT5400-1.
THIS EXAMPLE USES 2.5V AS THE WITH A PRECISION ARRAY THE
VOLTAGE OPTION MATCHING AND LOW TC WILL HELP
PRESERVE LOW DRIFT. R3 = R1||R2
R3 IS MADE WITH TWO PRALLEL 10k
RESISTORS, AVAILABLE IN THE
LT5400-1

Ultralow 1/f Noise Reference Buffer

IN LT3042
VIN
6V ±5%

4.7µF 100µA
–
EN/UV
+
PGFB OUT VOUT = 5V
1,2 IOUT(MAX)
6,7 200mA
PG OUTS
LTC6655-5
SET GND ILIM 4.7µF
3,4,5,8
1k
6655 TA08

10µF 49.9k 4.7µF

Rev. G

For more information www.analog.com 25

LTC6655/LTC6655LN
TYPICAL APPLICATIONS
Low Noise Statistical Averaging Reference
e′N = eN/√N; Where N is the Number of LTC6655s in Parallel

LTC6655-2.5
3V TO SHDN VOUT_F
13.2V R1
32.4Ω VOUT
VIN VOUT_S
C1 GND C2 C9
0.1µF 2.7µF 4.7µF

LTC6655-2.5
SHDN VOUT_F R2
32.4Ω
VIN VOUT_S
C3 GND C4
0.1µF 2.7µF

LTC6655-2.5
SHDN VOUT_F R3
32.4Ω
VIN VOUT_S
C5 GND C6
0.1µF 2.7µF

LTC6655-2.5
SHDN VOUT_F R4
32.4Ω
VIN VOUT_S
6655 TA09a
C7 GND C8
0.1µF 2.7µF

Low Frequency Noise (0.1Hz to 10Hz)

with Four LTC6655-2.5 in Parallel

200nV/
DIV

6655 TA09b
1s/DIV
320nVP-P
0.1Hz to 10Hz

Rev. G

26 For more information www.analog.com

 LTC6655/LTC6655LN
PACKAGE DESCRIPTION

MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)

0.889 ±0.127
(.035 ±.005)

5.10
(.201) 3.20 – 3.45
MIN (.126 – .136)

3.00 ±0.102
0.42 ± 0.038 0.65 (.118 ±.004) 0.52
(.0165 ±.0015) (.0256) (NOTE 3) 8 7 6 5 (.0205)
TYP BSC REF
RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102
4.90 ±0.152
DETAIL “A” (.118 ±.004)
0.254 (.193 ±.006)
(NOTE 4)
(.010)
0° – 6° TYP
GAUGE PLANE
1 2 3 4
0.53 ±0.152
(.021 ±.006) 1.10 0.86
(.043) (.034)
DETAIL “A” MAX REF
0.18
(.007)
SEATING
PLANE 0.22 – 0.38 0.1016 ±0.0508
(.009 – .015) (.004 ±.002)
TYP 0.65 MSOP (MS8) 0213 REV G
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

Rev. G

For more information www.analog.com 27

LTC6655/LTC6655LN
PACKAGE DESCRIPTION
LS8 Package
8-Pin Leadless Chip Carrier (5mm × 5mm)
(Reference LTC DWG # 05-08-1852 Rev B)

2.50 ±0.15 PACKAGE OUTLINE

7
1

2 0.5 6
2.54 ±0.15

1.4

1.50 ±0.15
XYY ZZ

4 ABCDEF
Q12345

e4
0.70 ±0.05 × 8 COMPONENT
PIN “A1”
5.00 SQ ±0.15
5.80 SQ ±0.15
TRAY PIN 1
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BEVEL
PACKAGE IN TRAY LOADING ORIENTATION

5.00 SQ ±0.15
4.20 SQ ±0.10 1.45 ±0.10
5.00 SQ ±0.15
0.95 ±0.10 R0.20 REF
8 8

2.00 REF
PIN 1 1
1 TOP MARK 7 7
(SEE NOTE 5)

2 6 6 0.5 2
4.20 ±0.10 2.54 ±0.15

1.4
5 3
3 5 R0.20 REF

1.00 × 7 TYP

LS8 0113 REV B

4 4
NOTE: 0.70 TYP 0.10 TYP 0.64 × 8 TYP
1. ALL DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS PACKAGE DO NOT INCLUDE PLATING BURRS
PLATING BURRS, IF PRESENT, SHALL NOT EXCEED 0.30mm ON ANY SIDE
4. PLATING—ELECTO NICKEL MIN 1.25UM, ELECTRO GOLD MIN 0.30UM
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Rev. G

28 For more information www.analog.com

 LTC6655/LTC6655LN
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 02/10 Voltage Options Added (1.250, 2.048, 3.000, 3.300, 4.096, 5.000), Reflected Throughout the Data Sheet 1 to 22
B 12/12 Addition of 5mm x 5mm hermetic LS8 package 1, 2, 3, 12, 22
Update to Electrical Characteristics to include LS8 package 3, 4
Addition of long-term drift and hysteresis plots for LS8 package 13
Addition of Humidity Sensitivity information 13
Addition of Related Parts 22
C 06/13 TJMAX changed from 125°C to 150°C 2
Addition of 5V Option in the LS8 package 3, 4
Addition of PC board layout guidance 14, 15
D 01/14 Addition of 4.096V option in the LS8 package 3, 4
Changed Line Regulation Condition to SHDN = 2V 4
Updated PC board layout guidance 14
Corrected Polarity of 9V battery in Figure 17 18
Updated captions for Figures 10, 12, 18 14, 15, 19
Updated note for circuit “Low Noise Precision Voltage Boost Circuit” 21
E 9/14 Corrected LS8-4.096 part marking 3
F 08/17 Trademark information updated. 1
Web links updated. 3, 23, 24
Addition of Ultralow 1/f Noise Reference Buffer schematic. 21
G 02/19 Addition of LTC6655LN Specifications and Features. 1 to 6, 11, 12,
18, 22, 23

Rev. G

29
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For moreby
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices.
LTC6655/LTC6655LN
TYPICAL APPLICATION
Low Noise Precision 24-Bit Analog-to-Digital Converter Application

2.5k

VREF 5V
7.5V
RREF
1nF

VCC
5k 400Ω CH0
CH1
MUXOUTN –
50Ω 1/2
CH2 ADCINN LTC6241
CH3
RTD +
CH4
CH5 –2.5V
CH6 MUXOUTP
CH7 2.5k
CH8 ADCINP

THERMOCOUPLE CH9 0.01µF 0.01µF

CH10 LTC2449
CH11 1nF
CH12 –
SDI 50Ω 1/2
CH13 LTC6241
SCK
CH14 SPI INTERFACE
CH15
SDO +
CS
COM

LTC6655 VREF BUSY

2 7
VIN VOUT_F REF+ EXT
0.1µF 1 6 REF– fO
SHDN VOUT_S
GND GND 10µF
GND
GND
GND
GND
GND

GND
GND

3,5,8 4
6655 TA10

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT®1236 Precision Low Drift Low Noise Reference 0.05% Max, 5ppm/°C Max, 1ppm (Peak-to-Peak) Noise
LT1236LS8 Precision Low Noise, Low Profile Hermetic Voltage Reference 0.05% Max, 5ppm/°C Max, 0.3µVP-P Noise, 5mm × 5mm Hermetic
Package
LT1460 Micropower Series References 0.075% Max, 10ppm/°C Max, 20mA Output Current
LT1461 Micropower Series Low Dropout 0.04% Max, 3ppm/°C Max, 50mA Output Current
LT1790 Micropower Precision Series References 0.05% Max, 10ppm/°C Max, 60mA Supply, SOT23 Package
LT6650 Micropower Reference with Buffer Amplifier 0.5% Max, 5.6µA Supply, SOT23 Package
LTC6652 Precision Low Drift Low Noise Reference 0.05% Max, 5ppm/°C Max, –40°C to 125°C, MSOP8
LT6660 Tiny Micropower Series Reference 0.2% Max, 20ppm/°C Max, 20mA Output Current, 2mm × 2mm DFN
LTC6652LS8 High Precision, Buffered Voltage Reference Family in 0.05% Max Initial Error, 5ppm/°C Max Drift, Shutdown Current <2µA,
5mm × 5mm Hermetic QFN Package –40°C to 125°C Operation
LT6654LS8 Precision, Low Noise, High Output Drive Voltage Reference 1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz, Sink/Source ±10mA,
Family in 5mm × 5mm Hermetic QFN Package 5ppm/°C Max Drift, –40°C to 125°C Operation

Rev. G

30
2/19
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