VLSITD SREENIDHI INSTITUTE OF SCIENCE AND TECHNOLOGY

DEBOUNCING BUTTONS ON FPGA USING VERILOG

16311A0410-BUDIDI SAI PALLAVI

16311A0428-KORAMUTLA VENKATA SRINIDHI

ECE-A 4th year

ABSTRACT:

In this project the unwanted signals are removed. when the button on FPGA is pressed,
there are unpredictable bounces which are unwanted. This verilog code is to debounce buttons on
FPGA by only generating a single pulse with a period of the input clock when the button on
FPGA is pressed, held long enough, and released. Debouncing, of course, is the process of
removing the bounces, of converting the brutish realities of the analog world into pristine ones
and zeros. Both hardware and software solutions exist, though by far the most common are those
done in a snippet of code.

We presented a simple Verilog code for debouncing buttons on FPGA. This is a

parameterized debouncer which can debounce width signals at a time. The debouncer receives a
vector of synchronized 1-bit signals and it outputs a debounced version of those signals. when a
button on FPGA is pressed and released, there are many unexpected up-and-down bounces in
push button signal. The debouncing circuit only generates a single pulse with a period of the slow
clock without bouncing as we expected.

1. AIM OF PROJECT: To perform Debouncing buttons on FPGA using verilog code

2.SOFTWARE USED: Vivado software
3. BACKGROUND THEORY:

In this project, a simple debouncing circuit is implemented in Verilog to generate only a

single pulse when pressing a button on FPGA. Debouncing Circuit for buttons on FPGA.
when a button on FPGA is pressed and released, there are many unexpected up-and-down
bounces in push button signal. The debouncing circuit only generates a single pulse with a
period of the slow clock without bouncing as we expected.only a single pulse is generated
when a button is pressed and released as expected. It is noted that this code is about to
create another clock domain in the design, so we have to take care of the multi-clock
domain issues while designing such as interfacing signals between different clock domains
(synchronizers needed, etc.). Instead of creating another slow clock in the design, we can
generate the clock enable signal to drive the two debouncing flip-flops.

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4. BLOCK DIAGRAM:

5. SOFTWARE CODE:
Following is the Verilog code for debouncing button.

// Verilog code for button debouncing on FPGA

// debouncing module without creating another clock domain
// by using clock enable signal
module debounce_better_version(input pb_1,clk,output pb_out);
wire slow_clk_en;wire Q1,Q2,Q2_bar;
clock_enable u1(clk,pb_1,slow_clk_en);
my_dff_en d1(clk,slow_clk_en,pb_1,Q1);
my_dff_en d2(clk,slow_clk_en,Q1,Q2);
assign Q2_bar = ~Q2;
assign pb_out = Q1 & Q2_bar;endmodule
// Slow clock enable for debouncing button
module clock_enable(input Clk_100M,pb_1, output slow_clk_en);
reg [26:0]counter=0;
always @(posedge Clk_100M, negedge pb_1)
begin
if(pb_1==0)
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counter <= 0;
else
counter <= (counter>=249999)?0:counter+1;
end
assign slow_clk_en = (counter == 249999)?1'b1:1'b0;
endmodule
// D-flip-flop with clock enable signal for debouncing
module module my_dff_en(input DFF_CLOCK, clock_enable,D, output reg Q=0);
always @ (posedge DFF_CLOCK) begin
if(clock_enable==1)
Q <= D;
end
endmodule

Testbench Verilog code for debouncing buttons:

`timescale 1ns / 1ps
// testbench verilog code for debouncing button without creating another clock
module debounce_better_version_tb;
// Inputs
reg pb_1;
reg clk;
// Outputs
wire pb_out;
// Instantiate the debouncing Verilog code
debounce_better_version uut (
.pb_1(pb_1),
.clk(clk),
.pb_out(pb_out)
);
initial begin
clk = 0;
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forever #10 clk = ~clk;

end
initial begin
pb_1 = 0;
#10;
pb_1=1;
#20;
pb_1 = 0;
#10;
pb_1=1;
#30;
pb_1 = 0;
#10;
pb_1=1;
#40;
pb_1 = 0;
#10;
pb_1=1;
#30;
pb_1 = 0;
#10;
pb_1=1;
#400;
pb_1 = 0;
#10;
pb_1=1;
#20;
pb_1 = 0;
#10;
pb_1=1;
#30;
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pb_1 = 0;
#10;
pb_1=1;
#40;
pb_1 = 0;
end
endmodule
6. RESULTS:
RTL SCHEMATIC:

SYNTHESIS SCHEMATIC:

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STIMULATION RESULT:

PROJECT SUMMARY:

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7.APPLICATIONS:

 The debouncing button on fpga applications include the following.

 A debouncing circuit removes the resulting ripple signal, and provides a clean transition at
its output.

 These are used to prevent switch bounce.

8. CONCLUSION:

Debouncing buttons on fpga is a method used to prevent bouncing. It is any kind of hardware
device or software that ensures that only a single signal will be acted upon for a single
opening or closing of a contact. It will ensure that it prevent ripple in the signal and allow to
provide a clear transition of the signal.

9. REFERENCES:
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1. https://my.eng.utah.edu/~cs5780/debouncing.pdf (by Jack G. Ganssle)

2. http://www.ganssle.com/debouncing-pt2.htm
3. https://www.quora.com/the-best-book-to-study-verilog-coding