AND GATE.

module USAMAFAISAL_AND(
input A,
input B,
output C
);
wire d;
nand(d,A,B);
nand(C,d,d);

endmodule
AND TEST FILE
module AND_TEST;

// Inputs
reg A;
reg B;

// Outputs
wire C;

// Instantiate the Unit Under Test (UUT)

USAMAFAISAL_AND uut (
.A(A),
.B(B),
.C(C)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
 #100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;

// Add stimulus here

end

endmodule

NOT .VERILOG
module USAMAFAISAL_NOT(
input A,
output B
);
nand(C,A,A);

endmodule
NOT.TEST FILE
module NOT_TEST;

// Inputs
reg A;

// Outputs
wire B;

// Instantiate the Unit Under Test (UUT)

USAMAFAISAL_NOT uut (
.A(A),
.B(B)
);

initial begin
// Initialize Inputs
A = 0;
#100;
A = 1;
#100;
 A = 0;
#100;
A = 1;
#100;
A = 0;
#100;
A = 1;
#100;
A = 0;
#100;
A = 1;
#100;
A = 0;
#100;
A = 1;
#100;
A = 0;
#100;A = 1;
#100;
A = 0;
#100;
A = 1;
#100;

// Add stimulus here

end

endmodule

OR.VERILOG
module USAMAFAISAL_OR(
input A,
input B,
output C
);
wire d;
wire e;
nand(d,A,A);
nand(e,B,B);
nand(C,d,e);

endmodule

OR.TEST FILE

module OR_TEST;

// Inputs
reg A;
reg B;

// Outputs
wire C;

// Instantiate the Unit Under Test (UUT)

USAMAFAISAL_OR uut (
.A(A),
 .B(B),
.C(C)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;

// Add stimulus here

 end

endmodule

XOR.VERILOG

//////////////////////////////////////////////////////////////////////////////////
module USAMAFAISAL_XOR(
input A,
input B,
output C
);
wire d;
wire f;
wire g;
wire h;

USAMAFAISAL_NOT not1(d,A);
USAMAFAISAL_NOT not2(f,B);
USAMAFAISAL_AND aa1(g,A,f);
USAMAFAISAL_AND aa2(h,B,d);
USAMAFAISAL_OR o2(C,g,h);
endmodule

XOR.TEST FILE

module xor_test;

// Inputs
reg A;
reg B;

// Outputs
wire C;

// Instantiate the Unit Under Test (UUT)

USAMAFAISAL_XOR uut (
.A(A),
.B(B),
.C(C)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
 B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;
A = 0;
B = 0;
#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;
#100;

// Add stimulus here

end

endmodule