VLSI

T.E.
(ELECTRONICS) SEMESTER VI
(ELX -603)
VLSI Design
Lectures: 4 hours / week

Theory Paper: 3 hours and 80 marks
Practical: 2 hours / week
Internal Test: 20 marks
(ELXL-603)
Term-Work : 25 marks
Practical/Oral : 25 marks
Prepared by YP Sir (VESIT)
Course Objectives
1. To teach fundamental principles of VLSI circuit

design and layout techniques.
2. To highlight the circuit design issues in the context

of VLSI technology.

Course Outcomes
1. To demonstrate a clear understanding of choice

of technology and technology scaling.
2. To design MOS based circuits and draw layout.
3. To realize logic circuits with different design

styles.
4. To demonstrate a clear understanding of system

level design issues such as protection, timing and
power dissipation. Prepared by YP Sir (VESIT)
Ch-1 : Technology Trend
1.1 Technology Comparison: Comparison of

BJT, NMOS and CMOS technology .
1.2 MOSFET Scaling: Types of scaling, Level 1

and Level 2 MOSFET Models, MOSFET
capacitances

Ch-2 : MOSFET Inverters
2.1 Circuit Analysis: Static and dynamic

analysis (Noise, propagation delay and power
dissipation) of resistive load and CMOS inverter,
comparison of all types of MOS inverters, design
of CMOS inverters, CMOS Latch-up
2.2 Logic Circuit Design: Analysis and design of

2-I/P NAND and NOR using equivalent CMOS
inverter

Ch-3 : MOS Circuit Design Styles
3.1 Design Styles: Static CMOS, pass transistor

logic, transmission gate, Pseudo NMOS, Domino,
NORA, Zipper, C2MOS, sizing using logical effort.
3.2 Circuit Realization: SR Latch, JK FF, D FF, 1

Bit Shift Register, MUX, decoder using above
design styles.

Ch-4 : Semiconductor Memories
4.1 SRAM: ROM Array, SRAM (operation,

design strategy, leakage currents, read/write
circuits), DRAM (Operation 3T, 1T, operation
modes, leakage currents, refresh operation,
Input-Output circuits), Flash (mechanism, NOR
flash, NAND flash)
4.2 Peripheral Circuits: Sense amplifier,

decoder

Ch-5 : Data Path Design
4.1 Adder: Bit adder circuits, ripple carry

adder, CLA adder.
4.2 Multipliers and shifter: Partial-product

generation, partial-product accumulation, final
addition, barrel shifter.

Ch-6 : VLSI Clocking and System Design
6.1 Clocking: CMOS clocking styles, Clock

generation, stabilization and distribution.
6.2 Low Power CMOS Circuits: Various

components of power dissipation in CMOS,
Limits on low power design, low power design
through voltage scaling.
6.3 I/O pads and Power Distribution and

Interconnection
Reference Books
[1] Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated

Circuits Analysis and Design”, Tata McGraw Hill, 3rd Edition.
[2] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital
Integrated Circuits: A Design Perspective”, Pearson Education, 2nd Edition.
[3] Etienne Sicard and Sonia Delmas Bendhia, “Basics of CMOS Cell Design”, Tata
McGraw Hill, First Edition.
[4] Neil H. E. Weste, David Harris and Ayan Banerjee, “CMOS VLSI Design: A
Circuits and Systems Perspective”, Pearson Education, 3rd Edition.
[5] Debaprasad Das, “VLSI Design”, Oxford, 1st Edition.
[6] Kaushik Roy and Sharat C. Prasad, “Low-Power CMOS VLSI Circuit Design”,
Wiley, Student Edition.
[7]John Uyemura , “ Introduction toVLSI Circuits and Systems”,
Wiley Student Edition.

Ch-1 Technology Trend
Silicon IC Technology
Bipolar MOS
NMOS PMOS CMOS

BJT Technology MOS Technology
Low Input Impedance High Input Impedance
High Power Dissipation Low Power Dissipation
Low Noise Margin High Noise Margin
Limitations in Scaling Can be scaled down

easily
Low packaging Density High packaging Density
IC Generations
Level of Integration No. of gates / chip

SSI 1-20
MSI 20-200
LSI 200-2000
VLSI > 1Million transistors
ULSI > 1Billion transistors

Moore’s Prediction
In the year 1960 ,he predicted that the number
of transistors that can be implemented per chip
doubles every 1 ½ years because of the shrinking
feature size and growing die size.

Figure :- Impact of Different VLSI design styles

Figure :- Progressive performance improvement

Figure :- General Architecture of FPGA

Figure :- Processing steps required for gate array
2 input
NAND gate
array
Figure :- Structural Decomposition of 4 bit Adder

Figure :- Regular design of (a) 2:1 Mux and (b) D-F/F

Simplified
View of
VLSI
design
flow

Scaling
Q. Define scaling? Explain various types of scaling in
detail. May-16 (10M)
Q. Define scaling and explain its significance in VLSI

circuits. Dec-15 (5M)
Q. Compare constant voltage and constant field

scaling with their merits and demerits
May-15 (10M)
Q. Explain the effect on drain current due to channel length
modulation and velocity saturation May-15/ (5M)
Parameter Name SPICE Unit
Name
Threshold Voltage Vto V
Transconductance Kp A/V2
Substrate-Bias Coefficient GAMMA V1/2
Surface Potential PHI V
Channel Length Modulation LAMBDA 1/V
Coefficient
Drain resistance RD Ώ
Source resistance RS Ώ
Sheet resistance of source /Drain RSH Ώ/sq

Diffusion Prepared by YP Sir (VESIT)
Name
Zero Bias drain bulk junction CBD F
capacitance
Zero Bias source bulk junction VT F
capacitance
Zero bias junction capacitance CJ F/m2
Bulk junction grading coefficient MJ -
Gate to source overlap capacitance CGSO F
Gate to drain overlap capacitance CGDO F

Gate oxide Thickness Tox M
Lateral Diffusion Prepared by YP Sir (VESIT)
LD M
Name
Saturation Current of the junction Is A
diode
Junction depth of source and drain Is A

Channel width effect on VT DELTA
Surface state density NSS Cm-2
Exponent coefficient for mobility UTRA
degradation


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T.E.

Lectures: 4 hours / week

1. To teach fundamental principles of VLSI circuit

2. To highlight the circuit design issues in the context

Prepared by YP Sir (VESIT)

1. To demonstrate a clear understanding of choice

2. To design MOS based circuits and draw layout.

3. To realize logic circuits with different design

4. To demonstrate a clear understanding of system

1.1 Technology Comparison: Comparison of

1.2 MOSFET Scaling: Types of scaling, Level 1

Prepared by YP Sir (VESIT)

2.1 Circuit Analysis: Static and dynamic

2.2 Logic Circuit Design: Analysis and design of

Prepared by YP Sir (VESIT)

3.1 Design Styles: Static CMOS, pass transistor

3.2 Circuit Realization: SR Latch, JK FF, D FF, 1

Prepared by YP Sir (VESIT)

4.1 SRAM: ROM Array, SRAM (operation,

4.2 Peripheral Circuits: Sense amplifier,

Prepared by YP Sir (VESIT)

4.1 Adder: Bit adder circuits, ripple carry

4.2 Multipliers and shifter: Partial-product

Prepared by YP Sir (VESIT)

6.1 Clocking: CMOS clocking styles, Clock

6.2 Low Power CMOS Circuits: Various

6.3 I/O pads and Power Distribution and

[1] Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated

Prepared by YP Sir (VESIT)

NMOS PMOS CMOS

High Power Dissipation Low Power Dissipation

Low Noise Margin High Noise Margin

Limitations in Scaling Can be scaled down

Level of Integration No. of gates / chip

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Prepared by YP Sir (VESIT)

Q. Define scaling and explain its significance in VLSI

Q. Compare constant voltage and constant field

Sheet resistance of source /Drain RSH Ώ/sq

Gate to drain overlap capacitance CGDO F

Junction depth of source and drain Is A

Prepared by YP Sir (VESIT)

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