Digital Signal Processing

EL/EE 405
Department of Electrical Engineering,
Delhi Technological University
September 2018
Course Instructor : Dr. Anup Kumar Mandpura

1
Outline
• Introduction to Digital Signal Controller
• Architecture of TMS320F2407
• System Initialization
• Addressing Modes
• ADC and DAC
• Event Manager
• Applications of TMS320F24x in Filter Design and other Domains.

2
What is Digital Signal Controller?

To begin with, let’s introduce some definitions:

• Microprocessor (µP)
• Micro Computer
• Microcontroller (µC)
• Digital Signal Processor (DSP)
• Digital Signal Controller (DSC)

3
Microprocessor (µP)
• Central Device of a multi chip Micro Computer System
• Two basic architectures: Von Neumann / Harvard
• Von Neumann : Shared memory space between code and data;
Shared memory busses between code and data; Example: Intel’s x86
Pentium Processor family
• Harvard : Two independent memory spaces for code and data; Two
memory bus systems for code and data
• A µP to operate needs additional devices
• To use a µP one has to add memory and additional external devices to
the Microprocessor.

4
Micro Computer
• Micro Computer = Microprocessor(µP) + Memory + Peripherals

• Example: Desktop -PC

• Peripherals include:
– Analogue to Digital Converter (ADC)
– Digital to Analogue Converter (DAC)
– Timer / Counter units
– Pulse Width Modulation ( PWM) Output Lines

5
Micro Computer Contd…
- Network Interface Units:
Serial Communication Interface (SCI) - UART
Serial Peripheral Interface ( SPI)
Inter Integrated Circuit ( I2C) – Bus
Controller Area Network (CAN)
Local Interconnect Network (LIN)
Universal Serial Bus (USB)
Local / Wide Area Networks (LAN, WAN)
Graphical Output Devices

6
Microcontroller (µC)
• A single chip computer
• All computing power AND input/output channels that are required to
design a real time control system are „on chip“
• Guarantee cost efficient and powerful solutions for embedded control
applications
• Backbone for almost every type of modern product
• Over 200 independent families of µC
• Both µP – Architectures (Von Neumann and Harvard) are used inside
Microcontrollers

7
Digital Signal Processor

• A specific device that is designed around the typical mathematical

operations to manipulate digital data that are measured by signal
sensors.
• The objective is to process the data as quickly as possible to be able to
generate an output stream of ‘new’ data in “real time”.
• Similar to a Microprocessor(µP), e.g. core of a computing
system

8
Digital Signal Processor Contd…

Additional Hardware Units to speed up computing of sophisticated

mathematical operations:
• Additional Hardware Multiply Unit(s)
• Additional Pointer Arithmetic Unit(s)
• Additional Bus Systems for parallel access
• Additional Hardware Shifter for scaling and/or multiply/divide by 2

9
Typical DSP Algorithms

10
A Digital Signal Controller
• A new type of microcontroller, where the processing power is delivered by a
DSP
• Digital Signal Controller (DSC) is a single chip Microcomputer with a
Digital Signal Processor (DSP) as core unit.
• By combining the computing power of a DSP with memory and peripherals
in one single device we derive the most effective solution for embedded real
time control solutions that require lots of math operations.
• DSC –Example: Texas Instruments C2000 family.

11
Architectural Overview of
TMS320F2407

12
Overview
• In 1982, Texas Instruments introduced the TMS32010, the first fixed-point
DSP in the TMS320 family.

• The TMS320 family consists of fixed-point, floating-point, multiprocessor

digital signal processors (DSPs), and fixed-point DSP controllers.

• TMS320 DSPs have an architecture designed specifically for real-time

signal processing.

• The F/C240 is a member of the C2000 DSP platform, and is optimized for
control applications.

13
Overview Contd…

• C2407 offers 40 Million instructions per second performance

• This real-time processing capability with controller peripherals creates
an ideal solution for control system applications.
• The following characteristics make the TMS320 family the right
choice for a wide range of processing applications:
1. Very flexible instruction set
2. Inherent operational flexibility
3. High-speed performance
4. Innovative parallel architecture
5. Cost effectiveness
14
Potential of DSPs
• Design of robust controllers for a new generation of inexpensive
motors, such as AC induction, DC permanent magnet, and switched-
reluctance motors.
• Full variable-speed control of brushless motor types that have lower
manufacturing cost and higher reliability
• Energy savings through variable-speed control, saving up to 25% of the
energy used by fixed-speed controllers
• Increased fuel economy, improved performance, and elimination of
hydraulic fluid in automotive electronic power steering (EPS) systems
Reduced manufacturing and maintenance costs by eliminating hydraulic
fluids in automotive electronic braking systems

15
Potential of DSPs Contd…
• More efficient and quieter operation due to less generation of torque
ripple, resulting in less loss of power, lower vibration, and longer life
• Elimination or reduction of memory lookup tables through real-time
polynomial calculation, thereby reducing system cost
• Use of advanced algorithms that can reduce the number of sensors
required in a system
• Control of power switching inverters, along with control algorithm
processing
• Single-processor control of multi-motor systems

16
TMS320 Device Nomenclature

17
TMS320F/C240x

18
Device Overview

19
Pin Functions

20
Pin Functions

21
Pin Functions

22
Pin Functions

23
Pin Functions

24
Pin Functions

25
Pin Functions

26
Pin Functions

27
Fig. Mapping External Devices to C2xx Core and Peripheral Interface
28
LF2407 Peripheral Set
• Two Event Managers (A and B)
• General Purpose (GP) timers
• PWM generators for digital motor control
• Analog-to-digital converter
• Controller Area Network (CAN) interface
• Serial Peripheral Interface (SPI) – synchronous serial port
• Serial Communications Interface (SCI) – asynchronous serial port
• General-Purpose bi-directional digital I/O (GPIO) pins
• Watchdog Timer (“time-out” DSP reset device for system integrity)

29
 Brief Introduction to Peripherals
Event Managers (EVA, EVB)

• The Event Manager is the most important peripheral in digital motor

control.
• Each EV is composed of functional “blocks” including timers, comparators,
capture units for triggering on an event, PWM logic circuits, quadrature-
encoder–pulse (QEP) circuits, and interrupt logic.

30
 Brief Introduction to Peripherals Contd…
The Analog-to-Digital Converter (ADC)

• Used whenever an external analog signal needs to be sampled and converted

to a digital number.
• The ADC is useful in motor control applications because it allows for
current sensing using a shunt resistor instead of an expensive current sensor.

31
 Brief Introduction to Peripherals Contd…
The Control Area Network (CAN) Module

• The CAN module is used for multi-master serial communication between

external hardware.
• The CAN bus has a high level of data integrity and is ideal for operation in
noisy environments such as in an automobile, or industrial environments
that require reliable communication and data integrity.

32
Brief Introduction to Peripherals Contd…
Serial Peripheral Interface (SPI) and Serial Communications Interface (SCI)

• The SPI is a high-speed synchronous communication port that is mainly used for
communicating between the DSP and external peripherals or another DSP device.
• Typical uses of the SPI include communication with external shift registers, display
drivers, or ADCs.
• The SCI is an asynchronous communication port that supports asynchronous serial
(UART) digital communication between the CPU and other asynchronous
peripherals that use the standard NRZ (non-return-to-zero) format.
• It is useful in communication between external devices and the DSP.

33
 Architecture Summary
• The C24x DSP architecture is based on a modified Harvard architecture,
which supports separate bus structures for program space and data space
• Separate program and data spaces allow simultaneous access to program
instructions and data.
• For example, while data is multiplied, a previous product can be added to
the accumulator, and at the same time, a new address can be generated.
• Such parallelism supports a set of arithmetic, logic, and bit-manipulation
operations that can all be performed in a single machine cycle.
• The C24x also includes control mechanisms to manage interrupts,
repeated operations, and function/subroutine calls.
• Devices within a generation of the TMS320 family have the same CPU
structure but different on-chip memory and peripheral configurations.
34
35
TMS320C2xx core CPU

• 32-bit central arithmetic logic unit (CALU)

• 32-bit accumulator
• 16-bit × 16-bit parallel multiplier with a 32-bit product capability
• Three scaling shifters
• Eight 16-bit auxiliary registers with a dedicated arithmetic unit for
indirect addressing of data memory

36
The Components of the C2xx DSP Core

Central Arithmetic Logic Unit (CALU)

• The C2xx performs 2s-complement arithmetic using the 32-bit CALU.

• The CALU uses 16-bit words taken from data memory, derived from an
immediate instruction, or from the 32-bit multiplier result.
• CALU is “transparent” in that it is not accessed directly by the user.
• The user only needs to write the command and later read the output from
the appropriate register

37
The Components of the C2xx DSP Core
Accumulator

• The accumulator stores the output from the CALU and also serves as
another input to the CALU .
• The accumulator is 32 bits wide and is divided into two sections, each
consisting of 16 bits.
• Assembly language instructions are provided for storing the high- and
low-order accumulator words to data memory.

38
C24xx Block Diagram
•

Controller
Program Memory
A(15-0) Mapped
• Memory
Registers

D(15-0)

Data Bus

Peripherals Multiplier
(Event Mgr)
Data
Memory
Peripherals
(Non-Event Mgr) ALU/Shifters

Fig. Block Diagram of C24xx DSP controller [4] 39

Peripherals Event Manager
GP Timers
Compare Unit
PWM Outputs
Dead-Band Logic
Capture Unit
Quadrature
Encoder

Data Bus
Pulse (QEP)

Non-EV Manager
Watchdog Timer
SPI
SCI
A/D Converter
I /O Pins
CAN
TMS320C2xx Memory
• 544 words × 16 bits of on-chip data/program dual-access RAM
• 16K words × 16 bits of on-chip program ROM or flash EEPROM
• 224K words × 16 bits of maximum addressable memory space
(64K words of program space, 64K words of data space, 64K
words of I/O space, and 32K words of global space)
• External memory interface module with a software wait-state
generator, a 16-bit address bus, and a 16-bit data bus

41
TMS320C2xx Memory Contd…
• Three different allocations of memory : Data, Program, and I/O memory space.
• Data space is used for program calculations, look-up tables, and any other memory used by an
algorithm.
• Data memory can be in the form of the on-chip random access memory (RAM) or external
RAM.
• Program memory is the location of user’s program code.
• Program memory on the LF2407 is either mapped to the off-chip RAM (MP/MC- pin =1) or to
the on-chip flash memory (MP/MC- = 0), depending on the logic value of the MP/MC-pin.
• I/O space is not really memory but a virtual memory address used to output data to peripherals
external to the LF2407
• For example, the digital-to-analog converter (DAC) is accessed with I/O memory.

42
Types of Physical Memory
Random Access Memory (RAM)

• The LF2407 has 544 words of 16 bits each in the on-chip Double Access Random
Access Memory (DARAM)
• These 544 words are partitioned into three blocks: B0, B1, and B2.
• Blocks B1 and B2 are allocated for use only as data memory.
• B0 memory can be configured as program or data memory depending on the value of
the core level “CNF” bit in status register one.
• There are also 2000 16-bit words of Single Access Random Access Memory
(SARAM).
• The main difference between DARAM and SARAM is that DARAM memory can
be accessed twice per clock cycle and SARAM can only be accessed once per cycle.

43
Types of Physical Memory Contd…
Non-volatile Flash Memory

• 32K of on-chip flash memory that can be mapped to program space if the MP/MC-
pin is made logic 0
• The flash memory can be electronically programmed and erased many times to
allow for code development.
• Unlike RAM, the Flash memory does not lose its contents when the LF2407 loses
power.
• It is only necessary to use the Flash memory if the DSP is to be run independently
from a PC and JTAG interface.
• Example, if F2407 in a DSP control solution to an automobile braking system. It
would be some what impractical to have a JTAG/PC interface in a car that is
undergoing performance testing.

44
Multiplier and ALU / Shifters
Program Bus
16
Data Bus
16 16 16
16 TREG (16) MUX
16 MULTIPLIER
PREG (32) 16

SHIFTER (0-16) 32
SHIFTER (-6, 0, 1, 4)

32
32
MUX
32 32
ALU (32)
32
C ACCH (16) ACCL (16)
• 32
SFL (0-7)
16
Data Bus
45
Multiplier
• The multiplier performs 16-bit, 2s-complement multiplication and creates a 32-
bit result.
• C2xx uses the 16-bit temporary register (TREG) and the 32-bit product register
(PREG).
• The TREG always needs to be loaded with one of the numbers that are to be
multiplied.
• The output of the multiply is stored in the PREG, which can later be read by the user
code

46
Scaling Shifters
Three 32-bit shifters that allow for scaling, bit extraction, extended arithmetic, and
overflow-prevention operations.
• Input data-scaling shifter (input shifter): This shifter left-shifts 16-bit input data
by 0 to 16 bits to align the data to the 32-bit input of the CALU
• Output data-scaling shifter (output shifter): This shifter left-shifts data from the
accumulator by 0 to 7 bits before the output is stored to data memory. The content
of the accumulator remains unchanged
• Product-scaling shifter (product shifter): The product shifter shifts the output of
the PREG before that output is sent to the input of the CALU. The product shifter
has four product shift modes (no shift, left shift by one bit, left shift by four bits,
and right shift by six bits).
47
Program Memory Program Bus
16

MUX
16 16
PC
16 16
• • 16
12-15
Address STACK
(8x16)
Program
ROM /
16 FLASH
A(15-0) •
MUX

16 Instruction
16
D(15-0) 16
MUX

16
16
Data Bus

To Data Memory
Data Memory
Data Bus
16 16 Program Bus
From Program Memory AR0(16)
3 AR1(16) 9
7 LSB
AR2(16) From IR
3 DP(9)
ARP(3) AR3(16)
9
AR4(16)
16 16
3 AR5(16)
16 MUX
AR6(16)
16
ARB(3) AR7(16) •
• 16

MUX ARAU(16) MUX

3
16
16
Data / Program
RAM
Data
RAM
16
MUX
16 16 16
Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers

• The ARAU generates data memory addresses when an instruction uses

indirect addressing to access data memory.
• Eight auxiliary registers (AR0-AR7) support the ARAU, each of which
can be loaded with a 16-bit value from data memory or directly from an
instruction.
• Each auxiliary register value can also be stored in data memory.
• The auxiliary registers are mainly used as “pointers” to data memory
locations to more easily facilitate looping or repeating algorithms.
• The auxiliary register pointer (ARP) embedded in status register ST0
references the auxiliary register.
• The status registers (ST0, ST1) are core level registers where values
such as the Data Page (DP) and ARP located.

50
Pipeline Process
Cycle
100 101 102 103 104 105 106
Add F1 D1 R1 E1
Sub F2 D2 R2 E2
Mpy F3 D3 R3 E3
Store F4 D4 R4 E4

Fully loaded pipeline

(normal operation)
TMS320C24xx Family
TMS320 ROM / PWM Compares / GP I/O
Devices Flash SARAM Channels Captures Timers QEP CAN SPI Pins

C/F240 16K - 12 9/4 3 2 No Yes 28

F241 8K - 8 5/3 2 2 Yes Yes 26

C242 4K - 8 5/3 2 2 No No 26

F243 8K - 8 5/3 2 2 Yes Yes 32

LF2401 8K 0.5K 7 4/1 2 2 No No 13

LC/F2402 6 / 8K - 8 5/3 2 2 No No 21

LF2403 16K 0.5K 8 5/3 2 2 Yes Yes 21

LC2404 16K 1K 16 10 / 6 4 4 No Yes 41

LC/F2406 32K 2K 16 10 / 6 4 4 Yes Yes 41

LF2407 32K 2K 16 10 / 6 4 4 Yes Yes 41

ONLY - C/F240, F243, and F2407 includes an external memory interface

All Devices Include - 544 Words of DARAM, Watchdog Timer, SCI (UART), and ADC
System Initialization

53
C240x PLL Clock Module
XTAL1 /CLKIN

XTAL OSC
Fin PLL 1 / 512 WDCLK
crystal Clock Module Prescaler
Watchdog
3-bit PLL Select
CPU Core Memory CAN
XTAL2
Event Manager SCI SPI
External Memory Interface
CLKOUT ADCCLK
Prescaler ADC

CLK PS2 CLK PS1 CLK PS0 Clock Frequency

0 0 0 4 x Fin
0 0 1 2 x Fin
0 1 0 1.33 x Fin
0 1 1 1 x Fin
1 0 0 0.8 x Fin
1 0 1 0.66 x Fin
1 1 0 0.57 x Fin
1 1 1 0.5 x Fin (default)
PLL Clock Module

The PLL clock module interfaces to the peripheral bus and provides all of the clocks required for the entire device.
There are four sets of clocks, all running at different frequencies:

• CPUCLK – This is the highest frequency clock provided by the module and is used by the CPU, all memories
and any peripherals tied directly to the CPUs buses, including an external memory interface if used. All other
clocks are derived by dividing this clock down to a lower frequency.

• SYSCLK – This clock is a half or a quarter the rate of CPUCLK. It is used to clock all the peripherals on the TI
peripheral bus.

• WDCLK – This is the low power clock used by the watchdog timer/realtime interrupt module. It has a nominal
frequency of 16 kHz with a 25% duty cycle.

55
Fig. PLL Clock Module Block Diagram 56
Clock Control Register 0 (CKCR0)
@ 702Bh

57
58
59
Low Power Modes
Peripheral /
Low Power CPU Logic Interrupt Watchdog PLL / Typical
Mode Clock Logic Clock Clock OSC Power
Normal Run on on on on ~ 90 mA

IDLE1 off on on on ~ 40 mA

IDLE2 off off on on ~ 30 mA

HALT off off off off ~ 10 A

Clock Control Register 1 (CKCR1)
@ 702D h

61
62
63
Watchdog Timer
• Resets the C240x if the CPU crashes
1. Watchdog counter runs independent of CPU
2. If counter overflows, reset is triggered
3. CPU must write correct data key sequence to reset the counter before
overflow
• Watchdog must be serviced (or disabled) within ~3.28ms after reset (40
MHz device) in TMS320F2812
• This translates into 131,072 instructions!
Watchdog Timer Module
/64 111
7 - Bit /32 110
/16 101 WDPS (Watch Dog Pre-scale)
Free -
WDCLK • /8 100 WDCR . 2 - 0
Running •
/4 011
Counter /2 010
System • CLR WDCR . 6
001
Reset 000 WDDIS
•
•
WDCNTR . 7 - 0
WDFLAG
8 - Bit Watchdog WDCR . 7
One-Cycle
Counter
CLR Delay
•
WDKEY . 7 - 0
WDCR . 5 - 3 WDCHK 2-0 System
Watchdog Reset
55 + AA Good Key
Reset Key • • 3 Request
Detector Bad Key • • /
Register / Bad WDCR Key
3
1 0 1
Watchdog Period Selection
WDPS FRC C240x timeout
Bits rollover period @ 40 MHz
00x: 1 3.28 ms
010: 2 6.55 ms
011: 4 13.11 ms
100: 8 26.21 ms
101: 16 52.43 ms
110: 32 104.86 ms
111: 64 209.72 ms

• WDPS set to 000 after any CPU reset

• Watchdog starts counting immediately after reset is
released
Watchdog Timer Control Register
WDCR @ 7029h
WD Flag Bit
Gets set when the WD causes a reset
• Writing a 1 clears this bit
• Writing a 0 has no effect

15 - 8 7 6 5 4 3 2 1 0

reserved WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0

Logic Check Bits WD Prescale

Write as 101 or reset Selection Bits
immediately triggered
Watchdog Disable Bit
(Functions only if WD OVERRIDE
bit in SCSR2 is equal to 1)
 Resetting the Watchdog
WDKEY @ 7025h

15 - 8 7 6 5 4 3 2 1 0

reserved D7 D6 D5 D4 D3 D2 D1 D0

• Allowable write values:

55h - counter enabled for reset on next AAh write
AAh - counter set to zero if reset enabled
• Writing any other value immediately triggers a CPU reset
• Watchdog should not be serviced solely in an ISR
1. If main code crashes, but interrupt continues to execute, the watchdog will not
catch the crash
2. Could put the 55h WDKEY in the main code, and the AAh WDKEY in an ISR;
this catches main code crashes and also ISR crashes
WDKEY Write Results
Sequential Value Written
Step to WDKEY Result

1 AAh No action
2 AAh No action
3 55h WD counter enabled for reset on next AAh write
4 55h WD counter enabled for reset on next AAh write
5 55h WD counter enabled for reset on next AAh write
6 AAh WD counter is reset
7 AAh No action
8 55h WD counter enabled for reset on next AAh write
9 AAh WD counter is reset
10 55h WD counter enabled for reset on next AAh write
11 23h CPU reset triggered due to improper write value
System Control and Status Register 1
SCSR1 @ 7018h
CLKOUT Pin Source Select
0 = CPU clock
1 = Watchdog Clock
PLL Clock Prescale
15 14 13 12 11 10 9 8
reserved CLKSCR LPM1 LPM0 CLK_PS2 CLK_PS1 CLK_PS0 reserved

7 6 5 4 3 2 1 0
ADC SCI SPI CAN EVB EVA
reserved ILLADR
CLKEN CLKEN CLKEN CLKEN CLKEN CLKEN

Illegal Address Detect Bit

Module Clock Enable Bit • Gets set when an illegal address is accessed
0 = Disabled • An illegal address event also triggers an NMI
• This bit it is not cleared by reset
1 = Enabled
• Writing a 1 clears this bit
• Writing a 0 has no effect
System Control and Status Register 2
SCSR2 @ 7019h
WD Override (protect bit)
After RESET - bit gives user ability to disable WD by Boot Enable
setting WDDIS bit=1 in WDCR 0 = Enable Boot ROM
• clear only bit and defaults to 1 after reset 1 = Disable Boot ROM
0 = protects WD from being disabled by s/w
• bit cannot be set to 1 by s/w (clear-only by writing 1) SARAM
1 = (default value) allows WD to be disabled using Program / Data
WDDIS bit in WDCR
Space Select
• once cleared, bit cannot set to 1 by s/w

15 - 6 5 4 3 2 1 0
WD
reserved XMIF_HI-Z BOOT_EN MP / MC DON PON
OVERRIDE

Microprocessor/Microcontroller mode
XMIF_Hi-Z Control 0 = on-chip program memory
0 = normal mapped (i.e. on-chip Flash)
1 = Hi-Z state 1 = off-chip program memory
mapped (i.e. external memory device)
72
73
74
Low Power Modes
Peripheral /
Low Power CPU Logic Interrupt Watchdog PLL / Typical
Mode Clock Logic Clock Clock OSC Power
Normal Run on on on on ~ 90 mA

IDLE1 off on on on ~ 40 mA

IDLE2 off off on on ~ 30 mA

HALT off off off off ~ 10 A

Low Power Mode Entering
SCSR1 @ 7018h
15 - 14 13 12 11 - 0

LPM 1 LPM 0

Low Power Mode Selection

00 = Idle 1
01 = Idle 2
1x = Halt

1. Set LPM bits

2. Enable desired exit interrupt(s)
3. Execute IDLE instruction
4. The Power down sequence of the hardware
depends on LP mode
References
[1] “TMS320F/C24x DSP Controllers Reference Guide CPU and Instruction Set” Texas Instruments,
Literature Number: SPRU160C, June 1999
[2] “ TMS320F2812 Digital Signal Processor, Implementation Tutorial”, Texas Instruments.
[3] “ TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811,
TMS320C2812 Digital Signal Processors” Data Manual” Texas Instruments, Literature Number:
SPRS174O April 2001 - Revised July 2007.
[4] “ C28x DSP Design Workshop” Texas Instruments Technical Training Organization, 2005.

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