A Highly-Accurate Low-Power CMOS Potentiostat
for Implantable BioSensors
Milad Razzaghpour Saul Rodriguez
School of ICT School of ICT
Royal Inst. of Tech. (KTH) Royal Inst. of Tech. (KTH) Tech. Univ. of Catalunya
Stockholm, Sweden. Stockholm, Sweden. Barcelona, Spain.
Email: razzaghpour@ieee.org Email: saul@kth.se Email: eduard.alarcon@upc.edu
Abstract— Current-mirror-based potentiostats suffer from sys-
tematic and random errors causing offset, gain and linearity
error in reading out the sensor data. In this work, a new
potentiostat topology is proposed to eliminate the systematic
error via an error-cancellation loop. The loop takes advantage
of an error-tracking amplifier connected to a transimpedance
amplifier with adjustable input common-mode voltage. Due to
the enhanced loop gain, the potentiostat is able to accurately
copy the sensor current which will then be converted into the
proportional voltage. Additionally, a theoretical discussion of
the proposed topology is given and a thorough study on the
effect of random error sources is carried out. The potentiostat is
designed and simulated in a 150nm CMOS process. The results
verify a highly-linear highly-accurate performance in a low-noise
condition, while consuming only 32 µW.
I. I NTRODUCTION
In the context of medical diagnostic, there has been many
advances in approaches to monitor biological compounds such
as glucose, cholesterol, etc. [1], [2]. In such monitoring, one
of the most popular approaches involves using amperometric
biosensors [3]. Basically, an amperometric biosensor generates
a current proportional to the concentration of the under-
measurement compound. By means of an analog front-end
circuitry, the current is measured and converted into a desired
signal depending on the application. Fig. 1 illustrates a generic
block diagram of the analog front-end for an amperometric
biosensor. As seen in the figure, the main block is the poten-
tiostat which is responsible of two main functions [4]: First,
to ensure that the sensor is biased at the required potential
which can vary for different sensors. Second, to extract the
sensor output current for subsequent processing.
There are several challenges in designing a low-power
potentiostat [5]. Since biosensors have a highly variable in-
ternal impedance, stability becomes an important issue when
a negative feedback configuration is used. Additionally, the
potentiostat has to guarantee that the sensor cell potential
tracks a reference DC voltage which enables the required
electrochemical reaction. Moreover, low noise operation is
needed in order to process weak signals with large enough
resolution. Finally, the accuracy as well as the linearity of the
potentiostat response has to be maximized.
Several current-measurement-based potentiostats have been
proposed in literature [3], [5], [6]. All these approaches make
978-1-4577-1470-2/11/$26.00 ©2011 IEEE
Eduard Alarcon Ana Rusu
Dept. of EE School of ICT
Royal Inst. of Tech. (KTH)
Stockholm, Sweden.
Email: arusu@kth.se
Amperometric
BioSensor
Vsensor
Isensor
Vref Sensor Isensor I-to-V Vout
Interface Converter
Potentiostat
Fig. 1. Block diagram of the analog front-end for an amperometric biosensor.
use of more than two opamps, which potentially leads to high
power consumption and large area [3]. Recently, a current-
mirror-based approach has been reported [7] which is shown in
Fig. 2. Since the number of opamps (especially in the negative
feedback loop) is decreased, this topology is potentially more
stable, low-power, and low-noise. It is also well-suited for
CMOS integration since the area is reduced to the minimum
possible level.
Considering Fig. 2, the main idea is to mirror the sensor
current into another circuitry and process the mirrored current
instead of the sensor current directly. The sources of error
of this configuration can be classified into systematic and
random errors. The systematic error is caused by channel-
length modulation in M1 and M2 , and can be calibrated
out from the potentiostat response. However, there remains
a calibration error which degrades the accuracy of reading out
the sensor data. Also, random errors such as device mismatch
and temperature variations cannot be calibrated which reduce
the accuracy and degrade the linearity.
In this paper, a new topology is proposed to eliminate the
systematic error in current-mirror-based potentiostats. Addi-
tionally, a thorough study on random error sources is carried
out.
II. E LECTROCHEMICAL S ENSOR
Considering Fig. 1, a two- or three-electrode sensor can be
used as the amperometric sensor. However, a three-electrode
sensor is preferred because of its highly-controllable interfacial
potential difference of the main sensor electrode [3]. As shown
in Fig. 3(a), the sensor is composed of three electrodes,
namely, working electrode (WE), counter electrode (CE) and
5
 VDD VDD

+
+
Vcell WE
- Vcell WE
-
RE Rf
RE CE
CE VDS(feedback) -
IF + - IF1 OP3
IF IF1 + + +
+ Vref OP1 Vout
-
Vref -OP1
M1 M2 -
M1 M2 -

+
OP2

Fig. 2. The state-of-the-art current-mirror-based potentiostat.

Fig. 4. The proposed potentiostat topology.

CWE CCE
WE Rs1 Rs2
WE CE
RWE RRE RCE
+ -
Vcell RE IF RE
(a) (b)
Fig. 3. Three-electrode amperometric biosensor. (a) Schematic representa-
tion. (b) Lumped equivalent circuit.
reference electrode (RE) [4]. The main chemical reaction takes
place at the WE in a certain cell potential Vcell . The RE is
used to generate a potential reference for measurement. Thus,
no chemical polarization should occur on the surface of this
electrode and no current should pass through this electrode.
The CE is merely an auxiliary electrode used to counterbalance
the current which sinks from (sources into) WE.
Fig. 3(b) depicts the lumped equivalent circuit of the am-
perometric sensor [7]. RW E , RCE and RRE represent the
resistance of the working, counter and reference electrode,
respectively. CW E and CCE denote the capacitance of the
working and counter electrode, respectively. Rs1 and Rs2 are
the chemical solution resistances.
In this work, the electrochemical biosensor for measuring
blood glucose concentration reported in [8] is used. The sensor
operates at a Vcell of 0.6V, and for a current range of [1nA-
1µA], RW E changes from 10MΩ to 100kΩ. RCE , RRE , and
Rs1,2 are 1kΩ, 6.3kΩ, and 10Ω, respectively. Also, CW E and
CCE are 1µF and 1nF, respectively.
III. P ROPOSED P OTENTIOSTAT T OPOLOGY
A. Circuit Description
The proposed potentiostat topology is shown in Fig. 4. It
is composed of two main sub-circuits. First, the conventional
potential-control loop through which the potential of RE is
stabilized at Vref . Second, an introduced error-cancellation
loop to maximize the accuracy of current-copying operation
from IF to IF 1 .
The potential-control loop consists of OP1 followed by a
common-source stage M1 , and the sensor cell itself as the
feedback network. This loop ensures that VRE tracks the
reference DC voltage, Vref , for the entire range of sensor
current (so, Vcell = VDD − Vref ). To study the accuracy of
tracking, the small-signal transfer function from Vref to Vcell
is extracted and can be expressed as
CE Vcell 1
≃ 1 (1)
Vref 1+ A1 gm1 (RW E ||rds1 )
where A1 is the open-loop gain of OP1, gm1 and rds1 are
the transconductance and output resistance of transistor M1 ,
respectively. Also, since the CE is designed to be much
larger than WE [8] (i.e., RCE ≪ RW E ), it is assumed
that RCE ≪ RW E rds1 A1 gm1 . Considering (1), the term
A1 gm1 (RW E ||rds1 ) determines the deviation of (1) from
the ideal value of 1. Since the sensor current along with
RW E varies several decades, and M1 is biased merely with
this current, gm1 and rds1 change considerably. Therefore, a
sufficiently large A1 should be designed to guarantee that (1)
is set close to the ideal value of 1 for the whole range of
sensor current.
Transistor M1 is biased with the sensor output current, IF ,
and mirrors the current to M2 . In order to increase the accuracy
of current-copying, M1 and M2 can be realized as cascode
topologies. However, the channel-length modulation effect still
causes current mismatch. In order to overcome this problem an
error-cancellation loop is introduced. The loop is formed by an
error-tracking amplifier OP2, and a transimpedance amplifier
(TIA) consisting of OP3 and Rf with an adjustable input
common-mode voltage. It is worth mentioning that OP2 could
have conventionally been connected to the gate of M1,2 to
control the current mismatch. However, this node is already
under the control of the potential-control loop and cannot be
re-used. Instead, OP2 is connected to the common-mode termi-
nal of the TIA. This configuration introduces a global feedback
and thus enhances the loop gain of the error-cancellation loop
considerably. Therefore, the TIA biases M2 via Rf to match
the current of M1 eliminating the VDS mismatch. The TIA
also provides a current-to-voltage conversion such that
Vout = Rf IF 1 (2)
where in ideal case IF 1 =IF .
To evaluate the contribution of OP2 and OP3 in eliminating
the channel-length modulation effect, (2) is re-calculated in
presence of VDS mismatch between M1 and M2 as
Vout = Rf IF 1 − ∆VDS(f eedback) (3)
where
 
1
∆VDS(f eedback) = ∆VDS , (4)
1 + A2 A3 β3

6
∆VDS(f eedback) , as noticed in Fig. 4, represents ∆VDS (=
VDS1 − VDS2 ) after adding the error-cancellation loop, the
feedback factor β3 = rds1 /(rds1 + Rf ), and Ax is the open-
loop gain of OPx .
As noticed in (3), ∆VDS(f eedback) causes offset error in the
transfer function. However, following (4), a sufficiently large
A2 and A3 can almost set this error to zero increasing the
accuracy in reading out the sensor current.
B. Design Considerations
The potentiostat was designed and simulated using the Ca-
dence environment in a commercial 150nm CMOS process. In
order to provide large signal swing and high gain to maintain
the potential-control loop, OP1 is realized as a folded cascode
operational transconductance amplifier (OTA) shown in Fig. 5.
A loop-gain of 70 dB and a phase margin of 65 degree for
the potential-control loop was achieved. Therefore, following
(1), we have VVcell
ref
=0.99971 for the worst case condition. This
guarantees that Vcell tracks Vref for the whole range of sensor
current. OP1 consumes only 11.7 µW from a VDD of 1.8V.
A single-stage differential amplifier was used for OP2 and
OP3. A loop-gain of 50 dB with 60 degree of phase margin
was obtained for the error-cancellation loop. Resulted from
power consumption versus gain optimization, OP2 and OP3
consume only 9.25 µW and 10.8 µW, respectively. Resistor
Rf was set to 400 kΩ providing adequate signal swing under
the maximum sensor current, and 112 dB gain from the sensor
current to the output voltage.
C. Device Mismatch Analysis
If it is designed carefully, the proposed topology eliminates
the channel-length modulation effect maximizing the accuracy
of copying the sensor current. However, random errors such
as device mismatch still remain which are investigated in this
section.
The output voltage in presence of device mismatch between
M1 and M2 can be expressed as
 
∆β p
Vout ≃ Rf IF 1 1 + − Rf ∆VT 2IF 1 β1 (5)
β1
where ∆VT = VT 2 − VT 1 , ∆β = β2 − β1 , and β1,2 is
the current gain factor of M1,2 . To simplify the calculations,
VDD
Vb2
M7 M6
it is assumed that there is no VDS mismatch between M1
and M2 due to the high enough loop-gain of the error-
cancellation loop. Also, the following assumptions introduced
q for 150nm technology have been used, ∆β ≪
in [9] validated
β1 , ∆VT ≪ 2IβDS1 , and λ1 VDS1 , λ2 VDS2 ≪ 1.
1
As it can be noticed in (5), ∆β and ∆VT cause gain (first
term) and linearity (second term) error, respectively. Note that,
these errors cannot be eliminated by OP2 and OP3.
IV. R ESULTS AND D ISCUSSIONS
The calibration curve of the potentiostat is shown in Fig. 6.
In this figure, a regression line is fitted over the simulation
results in order to examine the accuracy and linearity. The
figure reveals an overall accuracy of 0.02% with high linearity
in reading out the sensor current.
Mismatch parameters for the current-mirror transistors M1
and M2 were extracted from the statistical data of the process.
The threshold voltage mismatch σVT =0.4mV, and the beta
mismatch σβ /β=0.2%. Fig. 7 demonstrates the validity of (5)
under the worst case condition where a 3σ mismatch for both
VT (=1.2mV) and β (=0.6%) were applied to M1 and M2 . The
result indicates that (5) can estimate the simulation results with
an accuracy better than 0.1%.
Fig. 8 demonstrates the linearity versus VT -mismatch (Fig. 8
(a)), β-mismatch (Fig. 8 (b)) and temperature (Fig. 8 (c)). As
it was expected from (5), this figure reveals that the linearity
degrades mostly by increasing ∆VT instead of ∆β. Also,
it can be noticed that temperature variations has the least
influence on the linearity compared to ∆VT and ∆β. Accuracy
in reading out the sensor current was also analyzed under
the same mismatch condition and the result is summarized
in Table I. The worst case situation is considered where the
minimum resolvable current is measured. As it can be seen in
the table, the worst accuracy value belongs to the maximum
TABLE I
VARIATIONS OF ACCURACY FOR D IFFERENT R ANDOM E RRORS
Accuracy (%)
Parameter Range
Best Worst
VT (mV) [0.4-1.2] 0.13 1.46
!/! (%) [0.2-0.6] 0.10 0.21
Temp. (C) [20-60] 0.10 0.28
-6
10
y=1.049x+2.19 10-10
Sensor Current (A)

Vb3 R2= 0.999998

M9 M8 -7 20nA
10
Vi- Vi+ Vout
Vb4
M11 M10
M3 M4
10nA
-8 10nA 20nA
M5 M13 M12 10 -8 -7 -6
Vb1 10 10 10
Output Current (A)

Fig. 5. Schematic of the folded-cascode OTA. Fig. 6. Simulated calibration curve of the proposed potentiostat.

7
 TABLE II
T HE P OTENTIOSTAT P ERFORMANCE B ENCHMARK I NDICATOR

Performances This work [8] [3] [4] [10]

Technology (µm) 0.15 0.18 0.18 0.18 0.18
Supply Voltage 1.8 1.8 1.8 1.8 1.8
Input Current Range 10nA-1µA 1nA-1µA 1nA-1µA - 1nA-200nA
Power consumption ( W) 32 50 50.4 15840 95
a
Integrated Input Referred Noise ( V) 26.6 - - - 38
NO. of Opamps 3 1 1 5 1
Vcell/Vref 0.99971 - - 0.944 -
R2 0.99993 0.9984 - 0.97 -
Integral Nonlinearity Error 0.02% 0.1% 0.3% - -
Bandwidth (kHz) (CL=1µF) 1 - - 370 1
Simulation or Measurement S M M M S
a
(10mHz-100Hz)

-6
10 works’ measurement results, enough margin is considered,
Simulation (3 mismach)
Sensor Current (A)

Analytical (3 mismach) that if it is fabricated, the performance will not degrade

Analytical (no mismach)
-7
significantly.
10 20nA
V. C ONCLUSION
10nA In order to overcome the systematic error problem in
-8 10nA 20nA
10 -8 -7 -6
current-mirror-based potentiostats, a new topology was pro-
10 10 10 posed. Due to the high-loop-gain error-cancellation loop, the
Output Current (A)
potentiostat generates a precise copy of the sensor current
Fig. 7. Sensor current versus output current for the worst case mismatch eliminating the channel-length modulation effect. Analytical
condition. expressions verified by simulation in a 150nm CMOS process
"10-6
were presented to calculate the effect of systematic and
random errors. The achieved accuracy as well as high linearity,
R2 (dB)

0
-20 (a) low power and low noise features of the proposed topology
-40 makes it a potential candidate for bioimplantable sensors.
0 0.2 0.4 0.6 0.8 1 1.2
V (mV)
"10 -6 T ACKNOWLEDGMENT
R2 (dB)

-1.5 The authors would like to thank the Swedish Research

-2 (b)
-2.5
Council (VR) and the Spanish Ministry of Education (2008-
0 0.1 0.2 0.3 0.4 0.5 0.6 2011 I+D+i National Program) for funding this research.
!/! (%)
"10-6 R EFERENCES
R2 (dB)

-1.5
-2
-2.5
20 25 30 35 40 45
Temprature (C)
Fig. 8. Linearity versus (a) VT -mismatch, (b) β-mismatch, and (c) Temper-
ature variation.
∆VT . Also, unlike the case for linearity, temperature has more
effect on accuracy compared to ∆β. As a final conclusion,
among all the random sources of error, ∆VT is the major
source degrading both the linearity and accuracy.
Finally, Table II shows a result comparison with recent
published potentiostats. As it can be seen in the table, although
the proposed potentiostat employs more opamps compared
to [7], it achieves higher linearity and accuracy at lower
power consumption. In comparison with [6], the magnitude
of Vcell /Vref and also the linearity are improved considerably.
Finally, compared to [10] with equal bandwidth, the proposed
topology shows better noise performance and less power
consumption. Although this work is mostly compared to other
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