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Impact of I/O buffer configuration

on the ESD performance of a 0.5pm CMOS process

T.Nikolaidis’”, C.Papadas’, M.Varrot’, P.Mortini’ and G.Pananakakis2

1 SGS-THOMSON Microelectronics,
850, rue Jean Monnet - B.P. 16 - 38921 Crolles cedex - France
Fax:+ 33 76 92 64 44 Phone:+ 33 76 92 64 00

2L.P.C.S. -E.N.S.E.R.G
23,rue des martyrs - B.P. 257 - 38016 Grenoble cedex 1 - France
Fax:+ 33 76 85 60 70 Phone:+ 33 76 85 60 39

Abstract: 1. Introduction
The purpose of this paper is to The Electro-Static Discharge (ESD),
comment on the ESD performance of various widely recognized as one of the major
I/O buffer configurations implemented with a reliability threats of the microelectronics
general purpose, triple-metal, silicided industry, becomes more and more severe as
diffusion, 0.5pm LDD CMOS process. More the devices scale down [1,2]. More
specifically, several U 0 configurations are especially, in the case of the advanced
studied and, in addition to that, the influence submicron CMOS processes, the ESD has
of specific process steps (i.e. over-doped become a critical reliability concern, mainly
p-well) to the ESD performance are also due to the smaller geometrical parameters
addressed. Finally, it is demonstrated that the (oxide thickness, junction depth) as well as to
configuration which guarantees an ESD the impact of some advanced technological
performance over 8kV consists of a clamp options (graded junctions, silicided difisions)
formed on an over-doped p-well between pad [3,4]. Since an ESD pulse applied to an IC
and Vss, a diode in-between pad and Vdd and leads to irreversible damage, robust clamp
a similar clamp between the power and devices have been developed, in order to
ground supplies. increase the ESD performance [5,6,7]. These
devices play the role of protection

components by evacuating the discharge field-oxide gateless n-channel MOSFET
current to ground and limiting the overstress (hereinafter refered as CL2), with L=l pm,
voltage to safe values. W=15!5pm and DS=8pm. In order to study
The purpose of this paper is to study the influence of the substrate doping
the impact of standard clamp devices, concerktration on the ESD performance, both
fabricated with classical or specific process CL1 and CL2 have been fabricated: i) in a
steps (over-doped p-well) and implemented in Classical P-Well (CPW), with a doping
different 1/0buffer configuration schemes, on conceritration of about 2* l O ” ~ m -and
~ ii) in
the ESD performance of a 0.5pm CMOS an Over-Doped P-Well (ODPW), with a
process. Section 2 deals with the description doping concentration of about 10’8~m-3.
of the clamp devices and the different I/O The above described CL1 and CL2
buffer configurations used in these structures, implemented either in CPW or
experiments as well as with the presentation ODPW, constitute the main ESD protection
of the experimental set-up. The results and a components of the examined input and output
discussion on the ESD behavior of the buffers. For noise considerations, the Vdd
stressed buffers are reported in the section 3 power supply has been split to external
followed by the conclusion (section 4). (Vdde) and internal (Vddi) as well as the Vss
ground rail (Vsse: external ground, Vssi:
internal ground). The location of CL1 and
2. Test structures and experimental set-up. CL2 between the I/O pad and the power and
The test structures used throughout ground rails, in combination with the location
this study have been fabricated with a general of prlotection diodes, led to different 1/0
purpose, triple-metal, silicided diffusion, buffer configurations. In the case of input
0.5pm LDD CMOS process. Two clamp buffers (see Fig. l), the first configuration
devices have been considered. The first one is (11) consists of the components 1, 2 and 3,
a thin oxide, n-channel, LDD-free, MOSFET which are the main clamp, a 400Q
non-silicided resistor and a P+/N-well diode
(hereinafter refered as CLI), with a 0.5pm
channel length (L), 155pm width (W), a respectively. A second configuration (12)
consists of the I1 with the addition of two
distance between the silicide edge and the
P+/N-well diodes between the pad and the
diffusion edge in the drain (DS) of 8pm and
power supplies (Vdde and Vddi), components
with the gate and the source connected to
1, 2, 3, 4 and 5 in Fig.1. A third input
ground [SI, while the second one is a
configuration (13) is similar to the second one

Fig. 1 Input configuration

(12) with the addition of a main clamp self-protected output buffer (components 1
(component 6, Fig. 1) between Vdde and and 2, Fig. 2). The second one (02) has an
Vssi. Concerning the output buffers (see Fig. additional diode, represented by the
2), five different configurations have been component 3 in Fig. 2, in parallel with the
examined. The first one (01) is a PMOS transistor, while the third one (03)

Fig. 2 Output configuration

has a main clamp (component 4, Fig. 2 ) in norm lum STD 883C 3015.7. Different
parallel with the draidsubstrate diode of the stress conditions have been applied on the YO
NMOS pull-down transistor. A fourth pads with respect to the ground (Vsse and
configuration (04) consists of two identical Vssi) or to the power supplies (Vdde and
clamps located between pad and Vssi Vddi). The evaluation of the ESD
(component 4,Fig. 2) and between Vdde and performance of every I/O configuration is
Vssi (component 5, Fig. 2). Finally, the last based on the monitoring of the leakage
configuration (05) is similar to the 0 4 with current.
an additional diode (component 3, Fig. 2) in
parallel with the PMOS. Unless otherwise
specified, the NMOS output transistor 3. Results and discussion
parameters are L=lpm, W=8*30pm and 3a. Input buffers
DS=8pm. The above I/O configurations are Table 2 summarizes the ESD failure
summarized in the Table 1. level of the three input configurations for

1 1Input
(see Fig.1) 1 1
(see Fig. 2) 1 different stress conditions: i) positive pulses
with respect to Vsse (+/Vsse), ii) positive
I1 1,293 01 1, 2 pulses with respect to Vssi (+/Vssi) and iii)
I2 1,2,3,4, 5 02 1, 2, 3
negative pulses with respect to Vdde
I3 1, 2, 3,4, 5 , 6 03 L2,4
04 1, 2,4, 5 (-/Vdcle). It results that for the configuration
05 1, 2 , 3 , 4 , 5 11, WE: obtain the poorest performance, since
the oinly available current path during the
discharge is through the clamp 1, which
constitutes the energy absorbing component.
step-stressed with HBM pulses up to failure ThereFore, this clamp determines the ESD
which is defined as an excess leakage current performance of the input buffer, when
of lOnA at 3.3V. This failure criterion positive pulses are applied on the pad with
corresponds to the first significant change in respect to the ground rails, while for -/Vdde
the I(V) characteristic of the stressed buffer. stresses, this clamp is forward biased and the
The incremental step for successive stresses is discharge current goes to ground through the
1kV. Each stress consists of three HBM line capacitance. For this stress condition the
pulses generated by a commercial HBM tester ESD performance depends on the robustness
which conforms to the specifications of the of the output buffers connected between the

power and ground rails. In the high current the ODPW clamps will fail at a higher critical
regime both CL1 and CL2 work as lateral temperature due to the increased substrate
NPN Bipolar Junction Transistors @JT) in doping [12]. Consequently, the ESD
the snap-back mode [9]. The static I(V) performance of the ODPW clamps will be
snap-back characteristics of these clamps higher in comparison with CPW clamps, as it
(Figs. 3 and 4) have been traced using the is clearly shown in the Table 3 . All of the
4145 Semiconductor Parameter Analyzer and above reasons demonstrate that the ODPW is
the main snap-back parameters (avalanche an efficient technological option suitable for
voltage Va, triggering voltage Vtr and protecting thin gate oxides and small core
current Itr, snap-back voltage Vsb and transistors, while offering a high ESD
current Isb) have been extracted. Table 3 performance.
reads the extracted snap-back parameters as
well as the ESD performance of the stressed
clamp, which corresponds to positive stresses
with respect to Vssi. As it is clearly shown in
Figs. 3 and 4 as well as in Table 3, ODPW
clamps exhibit a significant decrease of the
avalanche and triggering voltages, in
comparison with clamps implemented in
CPW. Therefore, the ODPW process option
Fig. 3 Snap-back characteristic of CL 1
results in a faster activation of the standard
protection devices. On the other hand, despite
the fact that the lateral BJT gain in ODPW is I -1
lower than in CPW [lo], resulting in a
80.0 -
difference Vtr-Vsb smaller in ODPW than in
CPW, the snap-back voltage Vsb is lower for
v - ODPW
clamps implemented in ODPW for the chosen 40.0

doping levels. As a consequence, under stress 20.0 -

conditions, the dissipated heat will be lower 0.0

in ODPW clamps. Furthermore, since the

failures observed in both CL1 and CL2 can be Fig. 4 Snap-back characteristic of CL2
attributed to local thermal breakdown [ 113,

I I Va I Itr I Vtr I Isb I Vsb I Failure) throu,gh the forward biased diode makes the
two clamp devices (components 1 and 6, Fig.
'CLl ODPW 7.1 35 8.2 36 6.1 6 1) to be effectively in parallel, thus doubling
lCL2 ODPW 7 37 8.3 38 6.2 5
the ESD performance (configurations I1 and
CLl CPW 11.6 16 12.4 17 6.6 4
(CL21 CPW (11.5) 15 )12.5) 16 16.8 I 3 1 I3 in Table 2). It is worth noticing, that

Table 3 Main clamp snap-back parameters according to the experimental results (Table
Returning back to Table 2, it is 2), ithe ODPW structures guarantee a
observed that the ESD performance of the performance higher than 8kV.
configuration I2 is higher than the
corresponding performance of the input
buffers with the I1 configuration, in the case 3b. Ohtput buffers
of +/Vsse as well as +/Vssi stress conditions. Table 4 shows the ESD performance
This is due to the fact that the additional of the examined output buffer configurations
diode between pad and Vdde, in series with for different stress conditions. In the case of
the large line capacitance between Vdde and self-protected output buffers (01 and 0 2
Vsse, creates a second path for the discharge configurations), the highest performance is
current. Since the failure location is still the observed when applying positive pulses with
clamp device (component 1, Fig. l), the fact respect to the external ground (+Nsse). As it
that there is a discharge current component has been mentioned previously, for noise
through the line capacitance leads to an consilderations, the sources of all the NMOS
increase of the ESD failure level. Obviously, pub1-clown transistors are connected to a
for -/Vdde stresses, the diode 4 (Fig. 1) is separate bus Vsse, while the sources of the
blocked leading to the same ESD interrial buffers as well as the substrate of the
performance with the I1 configuration. NMOS pull-down transistor are connected to
Adding a second clamp in-between an internal "clean" bus Vssi. For the above
the power (Vdde) and ground (Vssi) rails stress conditions, the substrate of the NMOS
(configuration I3), the ESD performance pull-down transistor is floating and
fbrther increases for all the examined stress const:quently during the transient phase,
conditions. More precisely, when positive capacitive coupling [131 between the drain
pulses are applied on the pad with respect to and the substrate leads to a uniform turn on
the ground rails, during the transient phase, of most of the NMOS fingers , thus justiQing
capacitive coupling between pad and Vdde a high performance. Furthermore, comparing

0 2 with 0 1 for L=lpm, the addition of a during the transient phase both clamps are
diode (component 3, Fig. 2) in parallel with effectively in parallel. The addition of the
the PMOS transistor hrther increases the diode 3 (Fig. 2), parallel with the PMOS
performance, since the series resistance of the (configuration 05) fhrther improves the
diode 3 is significantly lower than the series results. Besides, the addition of the supply
resistance of the inherent PMOS diode clamp 5 (configurations 0 4 and 0 5 ),
(formed by the PHdrain and the N-well significantly improves the ESD performance
contact) [14]. In addition, the configuration in the case of -Ndde stresses.
0 2 with a L=0.7pm channel length NMOS Based on the results of the Table 4, it
pull-down transistor exhibits a higher ESD is observed that the ODPW structures give a
performance, which could be attributed to a higher performance in comparison with
better capacitive coupling between the drain clamps implemented in CPW, for the same
and the substrate of this transistor, induced by output buffer configuration. Since this result
the channel length L reduction. concerns also the input buffers, clamps
For the configurations 0 1 and 02, the fabricated in ODPW are suitable for an
worst stress condition is when applying overall ESD reliability.
positive pulses with 'respect to Vssi. In this
case the draidsubstrate diode of the NMOS
transistor is unprotected. Consequently, 4. Conclusion
putting a clamp between pad and Vssi The impact of different I/O buffer
(component 4, Fig. 2), the ESD performance configurations as well as the effect of the
significantly increases, since this clamp specific process steps, i.e. over-doped p-well,
snaps-back and dissipates the major part of on the ESD performance of a 0.5pm CMOS
the ESD current. The results presented in the process has been analyzed. It is demonstrated
Table 4 (configuration 0 3 ) clearly veri@ this that the ODPW is a very eficient
issue. technological option for overall ESD
A higher ESD performance is reliability and that the configuration that
obtained, when adding a second clamp guarantees a performance over 8kV consists
(component 5, Fig. 2) between Vdde and of a clamp formed on an over-doped p-well, a
Vssi (configuration 04). As it has been diode in between pad and Vdd and a similar
previously mentioned in the case of input clamp between the power and ground
buffers, the performance increases, because supplies.

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Configuration Technological ESD failure level (kV)
(see Table 1) parameters +Nsse +Nssi -1Vdde
CL1 4 4 <4
CPW CL2 3 3 <4
CL1 6 6 <4
ODPW CL2 4 5 <4
CL1 >6 5 <4
CPW CL2 5 4 <4
I2 4
CL1 >6 >6 -4
ODPW CL2 >6 >6 <4
CLl >8 8 >8
CPW c12 7 5 >8
CL1 >8 >8 >8
ODPW c12 >8 >8 >8

(see Table 1)



CL1 7 7 >8
ODPW CL2 6 7 >8
CPW CL 1 8 >8 >8
05 ODPW CL2 >8 >8 >8