Reduces the Output Voltage Fluctuation to Less Than Half at the Point

of a Rapid Load Change as Compared with the Conventional Method

TECHNICAL Fast Pulse Width Modulation (FPWM) Technology
ANALYSIS for DC-DC Converter, Featuring High-speed
Response with a Clock-Synchronized Comparator
Control method
The comparator control method achieves extremely stable output voltage
compared with the voltage/current control method for rapid changes of
the load current.
Furthermore, Fujitsu's proprietary technology (FPWM) enables the converter
to fully synchronize with the clock. This means that the electromagnetic
compatibility (EMC), particularly a self-jamming noise for wireless devices,
can be reduced.

a reference voltage. Therefore, the changes can be reduced to less than

Introduction
　Fujitsu designed its power management
ICs with a focus on multi-channel
features for portable digital devices.
Fujitsu's clock-synchronized comparator
control method, the FPWM technology,
can be employed in those products.
　The comparator control method
performs switching operations by
changing the duty ratio every cycle, and
comparing the output voltage against
comparator control method features
“high speed load transient response
characteristics”
. However, this method
has a problem which oscillation
frequency changes according to input/
output condition or load current. The
FPWM method is compatible with fully
synchronized to the clock and high speed
load transient response characteristics.
　With this technology, voltage
fluctuation at the time of rapid load
half, as compared with the conventional
method. This technology reduces the
EMC for wireless devices, improves the
power consumption for portable devices,
and meets the recent requirement for high
voltage accuracy for the SOC. Furthermore,
a built-in Pulse Frequency Modulation
(PFM) function improves efficiency
under light loads, which is essential
for today's energy-efficient products.
Both stable-constant-voltage output
and high-energy efficiency can be

Figure 1　Block Diagram realized with this technology.

Features
DRVH
R Q
・Clock-synchronized comparator control
<Error Comp.> method
FB Comp out Drive
② VFB S Logic ・High-speed load transient response
③ VSLOPE Less than 20mV voltage fluctuation
DRVL
Vin Slope CLK with the change of 0 to 450mA/2μs
①
VR
(output capacitance 10μF)

FIND Vol.30 No.3 21

 Fast Pulse Width Modulation (FPWM) Technology

・Power supply voltage range: Figure 2　Timing Diagram frequency is stable. Therefore, this
2.9V to 5.5V comparator control method simplifies
FET Fixed ON period at low side
・Output voltage range: 0.7V to 1.4V ①
the design of wireless devices.
CLK
・Built-in PFM function
・Switching frequency: 3.0 MHz to 4.5 MHz
②
VFB VFB≒VR PFM function
・Built-in over-current protection circuit
VSLOPE
③
・E x t e r n a l p h a s e c o m p e n s a t i o n 　In the automatic PFM/PWM switching
components, not required Comp out mode, this device operates either in
・Capable of a maximum output current PFM or PWM mode, according to the
ILX
- 2 Amps load current.
・Buit-in Load-independent soft start High-side Pch 　In the PFM mode, the oscillation
FET gate
function frequency is reduced at light load to
Low-side Nch
・Built-in FET for output voltage discharge FET gate improve efficiency, increasing the
・Ceramic capacitors can be used battery life for portable devices.

FPWM (measured waveform)

Io=0ｍA → 450mA/2μs
Key Features Various protection functions
Figure 3　Load-Transient response Characteristics
VIN=3.6V
Io：0mA⇔450mA/2μs
　A block diagram is shown in Figure 1, a Vo（20mV/div DC） 　A built-in over-current protection
FPWM (measured waveform) fosc=3MHz
timing chart in Figure 2, and the load 21.2mV L=1.5μH (multilayer) circuit monitors output current enabling
Io=0ｍA → 450mA/2μs Co=10μF
transient response characteristics of engineers to design a highly reliable
Io（200mA/div） VIN=3.6V
this method in Figure 3. Io：0mA⇔450mA/2μs DC/DC converter.
Vo（20mV/div DC）
10μs fosc=3MHz
21.2mV L=1.5μH (multilayer)
Co=10μF

Clock-synchronized comparator Io（200mA/div） Evaluation Board

control method
10μs 　Fujitsu provides an evaluation
　This method enables stable operation board for single-chip evaluation of the
by synchronizing with the internally method. ■
generated clock. The method provides Current mode (measured waveform)
ultra-high-speed response by periodically Io=0ｍA → 450mA/2μs ＊The evaluation board does not support the

comparing and detecting the internal PFM function.

VIN=3.6V
Io：0mA⇔450mA/2μs
slope voltage and the output voltage, Vo（20mV/div DC）
Current mode (measured waveform) fosc=3MHz
with simultaneous feedback to the 41.2mV L=1.5μH (multilayer)
Io=0ｍA → 450mA/2μs Co=10μF
comparator. Highly accurate output
Io（200mA/div） VIN=3.6V
voltage is achieved because the Io：0mA⇔450mA/2μs
Vo（20mV/div DC）
10μs fosc=3MHz
output ripple voltage required for the L=1.5μH (multilayer)
41.2mV
Co=10μF
conventional comparator method is
Io（200mA/div）
unnecessary.
　In addition, because of the clock- 10μs

synchronized method, the higher

harmonic component of oscillated

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