© 2015 IJIRT | Volume 1 Issue 12 | ISSN: 2349-6002

Comparison between risc and cisc

Anurag parmar , Deepak Kumar, Indu bala

Abstract:RISC vs. CISC wars raged in the 1980s

when chip area and processor design complexity
were the primary constraints and desktops and
servers exclusively dominated the computing
landscape. The main difference between RISC and
CISC is in the number of computing cycles each of
their instructions take. The difference the number
of cycles is based on the complexity and the goal of
their instructions. The main goal of this paper is
to compare the RISC and CISC On the basis of
the various terms.in this paper we are describing
the RISC and CISC (reduced instructions set
computer and complex instruction set computer
resp.) using the two microcontroller that are 8051
and PIC.
Fig.1 risc architecture
INTRODUCTION:-
RISC is a microprocessor that is designed to carry
RISC and CISC stand for two different competing
out few instructions at the same time. Based on small
philosophies in designing modern computer
instructions, these chips require fewer transistors,
architecture. The debate between them has been
which make the transistors cheaper to design and
going on for a long time and will likely continue. The
produce. Some other features of RISC include:
difference between RISC and CISC can lays on many
•Less decoding demand
levels, lots of plausible arguments are put forward by
•Uniform instruction set
both sides, such as code density, transistor counts,
•Identical general purpose registers
memory compiler and decode complexity etc. RISC
•Simple addressing nodes
and CISC are two important philosophies in
•Few data types in hardware
designing the computer architecture these two terms
Also, while writing codes, RISC makes it easier by
are compared with each other in various terms that
allowing the programmer to remove unnecessary
are cycles, program, design, complexity, memory
codes and prevents wasting of cycles.
unit and pipelining etc.
RISC: History of risc:
The first RISC projects came from IBM, Stanford,
The term RISC stands for ‘Reduced Instruction Set
and UC-Berkeley in the late 70s and early 80s. The
Computer’. It is a CPU design strategy based on
IBM 801, Stanford MIPS, and Berkeley RISC 1 and
simple instructions and fast performance. RISC is
2 were all designed with a similar philosophy which
small or reduced set of instructions. Here, each
has become known as RISC. Certain design features
instruction is meant to achieve very small tasks. In a
have been characteristic of most RISC processors:
RISC machine, the instruction sets are simple and
one cycle execution time: RISC processors have a
basic, which help in composing more complex
CPI (clock per instruction) of one cycle. This is due
instructions. Each instruction is of the same length;
to the optimization of each instruction on the CPU
the instructions are strung together to get complex
and a technique called PIPELINING
tasks done in a single operation. Most instructions are
pipelining: a technique that allows for simultaneous
completed in one machine cycle. This pipelining is a
execution of parts, or stages, of instructions to more
key technique used to speed up RISC machines.
efficiently process instructions;

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Large number of registers: the RISC design

philosophy generally incorporates a larger number of
registers to prevent in large amounts of interactions
with memory
RISC processor pipeline operates in much the same
way, although the stages in the pipeline are different.
While different processors have different numbers of
steps, they are basically variations of these five, used
in the MIPS R3000 processor:
- fetch instructions from memory
- read registers and decode the instruction
- execute the instruction or calculate an address
- access an operand in data memory
- write the result into a register

Fig.3 cisc architecture

The CISC machines have good performances, based
on the simplification of program compilers; as the
range of advanced instructions are easily available in
one instruction set. They design complex instructions
in one simple set of instructions. They perform low
level operations such as an arithmetic operation, or a
load from memory and memory store. CISC makes it
Fig.2.1 without pipeline
easier to have large addressing nodes and more data
types in the machine hardware. However, CISC is
considered less efficient than RISC, because of it
inefficiency to remove codes which leads to wasting
of cycles. Also, microprocessor chips are difficult to
understand and program for, because of the
complexity of the hardware. CISC was developed to
make compiler development simpler. It shifts most of
the burden of generating machine instructions to the
Fig.2.2execution using pipeline processor. For example, instead of having to make a
compiler write long machine instructions to calculate
CISC: a square-root, a CISC processor would have a built-in
The term CISC stands for ‘Complex Instruction Set ability to do this.
Computer’. It is a CPU design strategy based on
single instructions, which are capable of per CISC
computers have shorted programs. It has a large COMPARISON BETWEEN RISC AND CISC IS
number of complex instructions, which takes long GIVEN BELOW:
time to execute. Here, a single set of instruction is RISC CISC
covered in multiple steps; each instruction set has
more than three hundred separate instructions. Most
Acronym It stands for It stands for
instructions are completed in two to ten machine
‘Reduced ‘Complex
cycles. In CISC, instruction pipelining is not easily
Instruction Set Instruction
implemented forming multi-step operations.
Computer’. Set
Computer’
Definition The RISC The CISC

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processors have a processors processing. systems,

smaller set of have a larger home
instructions with set of automations,
few addressing instructions etc.
nodes. with many • This given above is the comparison between
addressing RISC and CISC tabular form i.e.,
nodes. comparison between two on the basis of
Memory unit It has no memory It has a memory unit, program, design, calculations,
unit and uses a memory unit time, external memory, pipelining, stalling,
separate hardware to implement code extension and disc sConsider the the
to implement complex program fragments:
instructions. instructions • CISC: mov ax, 10
Program It has a hard-wired It has a mov bx, 5
unit of micro- mul bx, ax
programming. programming • RISC: mov ax, 0
unit. mov bx, 10
Design It is a complex It is an easy mov cx, 5
complier design. complier Begin add ax, bx
design loop Begin
Calculations The calculations are The • The total clock cycles for the CISC version
faster and precise. calculations might be:
are slow and • (2 movs × 1 cycle) + (1 mul × 30 cycles) =
precise. 32 cycles
Time Execution time is Execution • While the clock cycles for the RISC version
very less. time is very is:
high • (3 movs × 1 cycle) + (5 adds × 1 cycle) + (5
External It does not require It requires loops × 1 cycle) = 13
memory external memory external

Pipelining
for calculations.

Pipelining does
memory for
calculations.
Pipelining
cisc • example is
8051
function correctly. does not

risc
function
correctly. • example is
Stalling Stalling is mostly
reduced in
The
processors
PIC
processors. often stall
Code Code expansion can Code
expansion be a problem. expansion is CONCLUSION:
To conclude from the above comparison of risc and
not a
cisc (reduced instructions set computer and complex
problem.
instructions set computer resp.) we get that risc is
Disc space The space is saved. The space is
more preferable in terms of complexity that is from
wasted.
the above example we get that same instructions
Applications Used in high end Used in low
executes using risc takes less no. of cycles as
applications such as end
compared to cisc other comparison of both describe
video processing, applications
above
telecommunications such as
References:
and image security
1. www.wikipedia.com

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2. http://www.visionengineer.com/comp/why_cis
c.shtml
3. http://www.embedded.com/story/OEG200302
05S0025
4. http://www.heyrick.co.uk/assembler/riscvcisc.
html
5.http://www.aallison.com/history.htm
6.http://arstechnica.com/cpu/4q99/risc-cisc/rvc-
2.html

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