`timescale 1 ns / 1 ns

module histRGB_fixpt
(rr,
gg,
bb,
nbins,
rhist [0:255],
ghist [0:255],
bhist [0:255]);

input [7:0] rr; // ufix8

input [6:0] gg; // ufix7
input [5:0] bb; // ufix6
output [8:0] nbins; // ufix9
output rhist [0:255];
output ghist [0:255];
output bhist [0:255];
wire [8:0] nBins_1; // ufix9
wire signed [31:0] tmp; // int32
real idx; // double
wire tmp_1;
wire signed [7:0] y_y [0:255]; // int8 [256]
wire signed [31:0] tmp_2; // int32
reg signed [7:0] y_y_1 [0:255]; // int8 [256]
reg signed [7:0] y_y_2 [0:255]; // int8 [256]
wire signed [7:0] tmp_3 [0:255]; // int8 [256]
wire [0:255] tmp_4; // ufix1 [256]
wire signed [31:0] tmp_5; // int32
real idx_1; // double
wire tmp_6;
wire signed [7:0] y_y_3 [0:255]; // int8 [256]
wire signed [31:0] tmp_7; // int32
reg signed [7:0] y_y_4 [0:255]; // int8 [256]
reg signed [7:0] y_y_5 [0:255]; // int8 [256]
wire signed [7:0] tmp_8 [0:255]; // int8 [256]
wire [0:255] tmp_9; // ufix1 [256]
wire signed [31:0] tmp_10; // int32
real idx_2; // double
wire tmp_11;
wire signed [7:0] y_y_6 [0:255]; // int8 [256]
wire signed [31:0] tmp_12; // int32
reg signed [7:0] y_y_7 [0:255]; // int8 [256]
reg signed [7:0] y_y_8 [0:255]; // int8 [256]
wire signed [7:0] tmp_13 [0:255]; // int8 [256]
wire [0:255] tmp_14; // ufix1 [256]
reg signed [31:0] p0y_t_0; // int32
reg signed [31:0] p0y_t_01; // int32
reg signed [31:0] p0y_t_02; // int32
reg signed [31:0] p0y_t_03; // int32
reg signed [31:0] p0y_t_04; // int32
reg signed [31:0] p0y_t_05; // int32
integer i;
assign nBins_1 = 9'b100000000;
assign nbins = nBins_1;
assign tmp = {24'b0, rr};
always @* idx = (tmp * 255.0) + 0.5;
assign tmp_1 = idx > 255.0;
 for (i=0;i<=255;i=i+1)
begin
assign y_y[i] = 8'sd0;
end
assign tmp_2 = $rtoi(idx);
always @* begin
for(p0y_t_0 = 32'sd0; p0y_t_0 <= 32'sd255; p0y_t_0 = p0y_t_0 + 32'sd1) begin
y_y_1[p0y_t_0] = y_y[p0y_t_0];
end
y_y_1[tmp_2] = 8'sd1;
end
always @* begin
for(p0y_t_01 = 32'sd0; p0y_t_01 <= 32'sd255; p0y_t_01 = p0y_t_01 + 32'sd1)
begin
y_y_2[p0y_t_01] = y_y[p0y_t_01];
end
y_y_2[255] = 8'sd1;
end
for (i=0;i<=255;i=i+1)
assign tmp_3[i] = (tmp_1 == 1'b0 ? y_y_1[i] :
y_y_2[i]);
for (i=0;i<=255;i=i+1)
assign tmp_4[i] = tmp_3[i][0];
for (i=0;i<=255;i=i+1)
assign rhist[i] = tmp_4[i];
assign tmp_5 = {25'b0, gg};
always @* idx_1 = (tmp_5 * 255.0) + 0.5;
assign tmp_6 = idx_1 > 255.0;
for (i=0;i<=255;i=i+1)
assign y_y_3[i] = 8'sd0;
assign tmp_7 = $rtoi(idx_1);
always @* begin
for(p0y_t_02 = 32'sd0; p0y_t_02 <= 32'sd255; p0y_t_02 = p0y_t_02 + 32'sd1)
begin
y_y_4[p0y_t_02] = y_y_3[p0y_t_02];
end
y_y_4[tmp_7] = 8'sd1;
end
always @* begin
for(p0y_t_03 = 32'sd0; p0y_t_03 <= 32'sd255; p0y_t_03 = p0y_t_03 + 32'sd1)
begin
y_y_5[p0y_t_03] = y_y_3[p0y_t_03];
end
y_y_5[255] = 8'sd1;
end
for (i=0;i<=255;i=i+1)
assign tmp_8[i] = (tmp_6 == 1'b0 ? y_y_4[i] :
y_y_5[i]);

for (i=0;i<=255;i=i+1)
assign tmp_9[i] = tmp_8[i][0];
for (i=0;i<=255;i=i+1)
assign ghist[i] = tmp_9[i];
assign tmp_10 = {26'b0, bb};
always @* idx_2 = (tmp_10 * 255.0) + 0.5;
assign tmp_11 = idx_2 > 255.0;
for (i=0;i<=255;i=i+1)
assign y_y_6[i] = 8'sd0;
assign tmp_12 = $rtoi(idx_2);
 always @* begin
for(p0y_t_04 = 32'sd0; p0y_t_04 <= 32'sd255; p0y_t_04 = p0y_t_04 + 32'sd1)
begin
y_y_7[p0y_t_04] = y_y_6[p0y_t_04];
end
y_y_7[tmp_12] = 8'sd1;
end
always @* begin
for(p0y_t_05 = 32'sd0; p0y_t_05 <= 32'sd255; p0y_t_05 = p0y_t_05 + 32'sd1)
begin
y_y_8[p0y_t_05] = y_y_6[p0y_t_05];
end
y_y_8[255] = 8'sd1;
end
for (i=0;i<=255;i=i+1)
assign tmp_13[i] = (tmp_11 == 1'b0 ? y_y_7[i] :
y_y_8[i]);
for (i=0;i<=255;i=i+1)
assign tmp_14[i] = tmp_13[i][0];
for (i=0;i<=255;i=i+1)
assign bhist[i] = tmp_14[i];
endmodule // histRGB_fixpt

TESTBENCH:

`timescale 1 ns / 1 ns

module histRGB_fixpt_tb;
reg clk;
reg reset_x;
wire enb;
wire bhist_0_done; // ufix1
wire rdEnb;
wire bhist_0_done_enb; // ufix1
reg [3:0] nbins_addr; // ufix4
wire bhist_0_lastAddr; // ufix1
wire resetn;
reg check4_done; // ufix1
wire ghist_0_done; // ufix1
wire ghist_0_done_enb; // ufix1
wire ghist_0_lastAddr; // ufix1
reg check3_done; // ufix1
wire rhist_0_done; // ufix1
wire rhist_0_done_enb; // ufix1
wire rhist_0_lastAddr; // ufix1
reg check2_done; // ufix1
wire nbins_done; // ufix1
wire nbins_done_enb; // ufix1
wire nbins_active; // ufix1
wire snkDone;
wire snkDonen;
wire tb_enb;
wire ce_out;
wire nbins_enb; // ufix1
wire nbins_lastAddr; // ufix1
reg check1_done; // ufix1
wire [7:0] rawData_rr; // uint8
reg [7:0] holdData_rr; // uint8
wire [6:0] rawData_gg; // ufix7
reg [6:0] holdData_gg; // ufix7
wire [5:0] rawData_bb; // ufix6
reg [5:0] holdData_bb; // ufix6
reg [7:0] rr_offset; // uint8
wire [7:0] rr_1; // uint8
reg [6:0] gg_offset; // ufix7
wire [6:0] gg_1; // ufix7
reg [5:0] bb_offset; // ufix6
wire [5:0] bb_1; // ufix6
wire [8:0] nbins_1; // ufix9
wire rhist [0:255]; // ufix1
wire ghist [0:255]; // ufix1
wire bhist [0:255]; // ufix1
wire [8:0] nbins_expected_1; // ufix9
wire [8:0] nbins_ref; // ufix9
reg nbins_testFailure; // ufix
wire rhist_expected_1 [0:255]; // ufix1
wire rhist_ref [0:255]; // ufix1
reg rhist_testFailure [0:255]; // ufix1
wire ghist_expected_1 [0:255]; // ufix1
wire ghist_ref [0:255]; // ufix1
reg ghist_testFailure [0:255]; // ufix1
wire bhist_expected_1 [0:255]; // ufix1
wire bhist_ref [0:255]; // ufix1
reg bhist_testFailure [0:255]; // ufix1
reg testFailure; // ufix1
reg or_t; // ufix1
assign bhist_0_done_enb = bhist_0_done & rdEnb;
assign bhist_0_lastAddr = nbins_addr >= 4'b1001;
assign bhist_0_done = bhist_0_lastAddr & resetn;
// Delay to allow last sim cycle to complete
always @(posedge clk or posedge reset_x)
begin : checkDone_4
if (reset_x) begin
check4_done <= 0;
end
else begin
if (bhist_0_done_enb) begin
check4_done <= bhist_0_done;
end
end
end

assign ghist_0_done_enb = ghist_0_done & rdEnb;

assign ghist_0_lastAddr = nbins_addr >= 4'b1001;
assign ghist_0_done = ghist_0_lastAddr & resetn;
// Delay to allow last sim cycle to complete
always @(posedge clk or posedge reset_x)
begin : checkDone_3
if (reset_x) begin
check3_done <= 0;
end
else begin
if (ghist_0_done_enb) begin
check3_done <= ghist_0_done;
end
end
end
assign rhist_0_done_enb = rhist_0_done & rdEnb;
assign rhist_0_lastAddr = nbins_addr >= 4'b1001;
assign rhist_0_done = rhist_0_lastAddr & resetn;
// Delay to allow last sim cycle to complete
always @(posedge clk or posedge reset_x)
begin : checkDone_2
if (reset_x) begin
check2_done <= 0;
end
else begin
if (rhist_0_done_enb) begin
check2_done <= rhist_0_done;
end
end
end
assign nbins_done_enb = nbins_done & rdEnb;
assign nbins_active = nbins_addr != 4'b1001;
assign #2 enb = rdEnb;
assign snkDonen = ~ snkDone;
// Count limited, Unsigned Counter
// initial value = 0
// step value = 1
// count to value = 9
always
begin : clk_gen
clk <= 1'b1;
# (5);
clk <= 1'b0;
# (5);
if (snkDone == 1'b1) begin
clk <= 1'b1;
# (5);
clk <= 1'b0;
# (5);
$stop;
end
end
initial
begin : reset_x_gen
reset_x <= 1'b1;
# (20);
@ (posedge clk)
# (2);
reset_x <= 1'b0;
end
assign resetn = ~ reset_x;
assign tb_enb = resetn & snkDonen;
assign rdEnb = (snkDone == 1'b0 ? tb_enb :
1'b0);
assign ce_out = enb & (rdEnb & tb_enb);
assign nbins_enb = ce_out & nbins_active;
// Count limited, Unsigned Counter
// initial value = 0
// step value = 1
// count to value = 9
always @(posedge clk or posedge reset_x)
begin : nBins_process
if (reset_x == 1'b1) begin
nbins_addr <= 4'b0000;
 end
else begin
if (nbins_enb) begin
if (nbins_addr == 4'b1001) begin
nbins_addr <= 4'b0000;
end
else begin
nbins_addr <= nbins_addr + 4'b0001;
end
end
end
end
assign nbins_lastAddr = nbins_addr >= 4'b1001;
assign nbins_done = nbins_lastAddr & resetn;
// Delay to allow last sim cycle to complete
always @(posedge clk or posedge reset_x)
begin : checkDone_1
if (reset_x) begin
check1_done <= 0;
end
else begin
if (nbins_done_enb) begin
check1_done <= nbins_done;
end
end
end

assign snkDone = check4_done & (check3_done & (check1_done & check2_done));

// Data source for rr
assign rawData_rr = 8'b10000010;
// holdData reg for r
always @(posedge clk or posedge reset_x)
begin : stimuli_r
if (reset_x) begin
holdData_rr <= 8'bx;
end
else begin
holdData_rr <= rawData_rr;
end
end
// Data source for gg
assign rawData_gg = 7'b1010101;
// holdData reg for g
always @(posedge clk or posedge reset_x)
begin : stimuli_g
if (reset_x) begin
holdData_gg <= 7'bx;
end
else begin
holdData_gg <= rawData_gg;
end
end
// Data source for bb
assign rawData_bb = 6'b101100;
// holdData reg for b
always @(posedge clk or posedge reset_x)
begin : stimuli_b
if (reset_x) begin
holdData_bb <= 6'bx;
 end
else begin
holdData_bb <= rawData_bb;
end
end
always @(rawData_rr or rdEnb)
begin : stimuli_r_1
if (rdEnb == 1'b0) begin
rr_offset <= holdData_rr;
end
else begin
rr_offset <= rawData_rr;
end
end
assign #2 rr_1 = rr_offset;
always @(rawData_gg or rdEnb)
begin : stimuli_g_1
if (rdEnb == 1'b0) begin
gg_offset <= holdData_gg;
end
else begin
gg_offset <= rawData_gg;
end
end
assign #2 gg_1 = gg_offset;
always @(rawData_bb or rdEnb)
begin : stimuli_b_1
if (rdEnb == 1'b0) begin
bb_offset <= holdData_bb;
end
else begin
bb_offset <= rawData_bb;
end
end
assign #2 bb_1 = bb_offset;
histRGB_fixpt u_histRGB_fixpt (.rr(rr_1), // uint8
.gg(gg_1), // ufix7
.bb(bb_1), // ufix6
.nbins(nbins_1), // ufix9
.rhist (rhist[0:255]),
.ghist (ghist[0:255])
.bhist (bhist[0:255]) );

// Data source for nbins_expected

assign nbins_expected_1 = 9'b100000000;
assign nbins_ref = nbins_expected_1;
always @(posedge clk or posedge reset_x)
begin : nbins_1_checker
if (reset_x == 1'b1) begin
nbins_testFailure <= 1'b0;
end
else begin
if (ce_out == 1'b1 && nbins_1 !== nbins_ref) begin
nbins_testFailure <= 1'b1;
$display("ERROR in nbins_1 at time %t : Expected '%h' Actual '%h'",
$time, nbins_ref, nbins_1);
end
end
end
 // Data source for rhist_0_0_expected

for (i=0;i<=255;i=i+1)
begin
assign rhist_expected_1 [i] = 1'b0;
assign rhist_ref[i] =rhist_expected_1 [i];

always @(posedge clk or posedge reset_x)

begin : rhist_checker[i]
if (reset_x == 1'b1) begin
rhist_testFailure[i] <= 1'b0;
end
else begin
if (ce_out == 1'b1 && rhist[i] !== rhist_ref[i]) begin
rhist_testFailure[i]<= 1'b1;
$display("ERROR in rhist at time %t : Expected '%h' Actual '%h'", $time,
rhist_ref[i], rhist[i]);
end
end
end
for (i=0;i<=255;i=i+1)
begin
assign ghist_expected_1 [i] = 1'b0;
assign ghist_ref[i] =ghist_expected_1 [i];
always @(posedge clk or posedge reset_x)
begin : ghist_checker[i]
if (reset_x == 1'b1) begin
ghist_testFailure[i] <= 1'b0;
end
else begin
if (ce_out == 1'b1 && ghist[i] !== ghist_ref[i]) begin
ghist_testFailure[i]<= 1'b1;
$display("ERROR in ghist at time %t : Expected '%h' Actual '%h'", $time,
ghist_ref[i], ghist[i]);
end
end
end
for (i=0;i<=255;i=i+1)
begin
assign bhist_expected_1 [i] = 1'b0;
assign bhist_ref[i] =bhist_expected_1 [i];

always @(posedge clk or posedge reset_x)

begin : bhist_checker[i]
if (reset_x == 1'b1) begin
bhist_testFailure[i] <= 1'b0;
end
else begin
if (ce_out == 1'b1 && bhist[i] !== bhist_ref[i]) begin
bhist_testFailure[i]<= 1'b1;
$display("ERROR in bhist at time %t : Expected '%h' Actual '%h'", $time,
bhist_ref[i], bhist[i]);
end
end
end
always @(nbins_testFailure, rhist_testFailure[0:255], ghist_testFailure[0:255],
bhist_testFailure[0:255]) \
begin
for (i=2;i<=255;i=i+1)
begin
or_t = (rhist_testFailure[1] | rhist_testFailure[0]);
or_t = rhist_testFailure[i] | or_t;
end
for (i=0;i<=255;i=i+1)
begin
or_t = ghist_testFailure[i] | or_t;
end
for (i=0;i<=255;i=i+1)
begin
or_t = bhist_testFailure[i] | or_t;
end

testFailure = or_t;
end
always @(posedge clk)
begin : completed_msg
if (snkDone == 1'b1) begin
if (testFailure == 1'b0) begin
$display("**************TEST COMPLETED (PASSED)**************");
end
else begin
$display("**************TEST COMPLETED (FAILED)**************");
end
end
end

endmodule // histRGB_fixpt_tb