NGD18N40CLBT4

Ignition IGBT
18 Amps, 400 Volts
N−Channel DPAK
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features
monolithic circuitry integrating ESD and Over−Voltage clamped http://onsemi.com
protection for use in inductive coil drivers applications. Primary uses
include Ignition, Direct Fuel Injection, or wherever high voltage and 18 AMPS
high current switching is required. 400 VOLTS
• Ideal for Coil−on−Plug Applications VCE(on)  2.0 V @
• DPAK Package Offers Smaller Footprint for Increased Board Space IC = 10 A, VGE
4.5 V
• Gate−Emitter ESD Protection
•
C
Temperature Compensated Gate−Collector Voltage Clamp Limits
Stress Applied to Load
• Integrated ESD Diode Protection
• New Design Increases Unclamped Inductive Switching (UIS) Energy G RG
Per Area
• Low Threshold Voltage Interfaces Power Loads to Logic or RGE

Microprocessor Devices
• Low Saturation Voltage E
• High Pulsed Current Capability
4
• Optional Gate Resistor (RG) and Gate−Emitter Resistor (RGE) DPAK

•
CASE 369C
Emitter Ballasting for Short−Circuit Capability 1 2
STYLE 7
3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

MARKING
Rating Symbol Value Unit
DIAGRAM
Collector−Emitter Voltage VCES 430 VDC
1
Collector−Gate Voltage VCER 430 VDC Gate
Gate−Emitter Voltage VGE 18 VDC YWW 4
2
G18 Collector
Collector Current−Continuous IC 15 ADC Collector
N40B
@ TC = 25°C − Pulsed 50 AAC
ESD (Human Body Model) ESD kV 3
R = 1500 Ω, C = 100 pF 8.0 Emitter

ESD (Machine Model) R = 0 Ω, C = 200 pF ESD 800 V

G18N40B = NGD18N40CLB
Total Power Dissipation @ TC = 25°C PD 115 Watts Y = Year
Derate above 25°C 0.77 W/°C WW = Work Week
Operating and Storage Temperature Range TJ, Tstg −55 to °C
+175
ORDERING INFORMATION

Device Package Shipping†

NGD18N40CLB DPAK 75 Units/Rail

NGD18N40CLBT4 DPAK 2500/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

 Semiconductor Components Industries, LLC, 2003 1 Publication Order Number:

September, 2003 − Rev. 4 NGD18N40CLB/D
 NGD18N40CLBT4

UNCLAMPED COLLECTOR−TO−EMITTER AVALANCHE CHARACTERISTICS (−55° ≤ TJ ≤ 175°C)

Characteristic Symbol Value Unit
Single Pulse Collector−to−Emitter Avalanche Energy EAS mJ
VCC = 50 V, VGE = 5.0 V, Pk IL = 21.1 A, L = 1.8 mH, Starting TJ = 25°C 400
VCC = 50 V, VGE = 5.0 V, Pk IL = 16.2 A, L = 3.0 mH, Starting TJ = 25°C 400
VCC = 50 V, VGE = 5.0 V, Pk IL = 18.3 A, L = 1.8 mH, Starting TJ = 125°C 300
Reverse Avalanche Energy EAS(R) mJ
VCC = 100 V, VGE = 20 V, Pk IL = 25.8 A, L = 6.0 mH, Starting TJ = 25°C 2000
MAXIMUM SHORT−CIRCUIT TIMES (−55°C ≤ TJ ≤ 150°C)
Short Circuit Withstand Time 1 (See Figure 17, 3 Pulses with 10 ms Period) tsc1 750 s
Short Circuit Withstand Time 2 (See Figure 18, 3 Pulses with 10 ms Period) tsc2 5.0 ms
THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Case RθJC 1.3 °C/W
Thermal Resistance, Junction to Ambient DPAK (Note 1) RθJA 95 °C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds TL 275 °C

ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit
OFF CHARACTERISTICS
Collector−Emitter Clamp
Clam Voltage BVCES −40°C
TJ = −40 C to 380 395 420 VDC
IC = 2 0 mA
2.0
150°C
TJ = −40°C to 390 405 430
IC = 10 mA
150°C

Zero Gate Voltage

g Collector Current ICES TJ = 25°C − 2.0 20 µADC
µ
VCE = 350 V,
TJ = 150°C − 10 40*
VGE = 0 V
TJ = −40°C − 1.0 10
Reverse Collector−Emitter Leakage
g Current IECS TJ = 25°C − 0.7 2.0 mA
VCE = −24 V TJ = 150°C − 12 25*
TJ = −40°C − 0.1 1.0
Reverse Collector−Emitter Clamp Voltage
g BVCES(R) TJ = 25°C 27 33 37 VDC
IC = −75 mA TJ = 150°C 30 36 40
TJ = −40°C 25 32 35
Gate−Emitter Clamp Voltage BVGES TJ = −40°C to 11 13 15 VDC
IG = 5.0 mA
150°C
Gate−Emitter Leakage Current IGES TJ = −40°C to 384 640 1000 µADC
VGE = 10 V
150°C
Gate Resistor (Optional) RG TJ = −40°C to − 70 − Ω
−
150°C
Gate Emitter Resistor RGE TJ = −40°C to 10 16 26 kΩ
−
150°C
ON CHARACTERISTICS (Note 2)
g
Gate Threshold Voltage VGE(th) TJ = 25°C 1.1 1.4 1.9 VDC
IC = 1
1.0
0 mA,
A
TJ = 150°C 0.75 1.0 1.4
VGE = VCE
TJ = −40°C 1.2 1.6 2.1*
Threshold Temperature Coefficient − − − − 3.4 − mV/°C
(Negative)
1. When surface mounted to an FR4 board using the minimum recommended pad size.
2. Pulse Test: Pulse Width  300 µS, Duty Cycle  2%.
*Maximum Value of Characteristic across Temperature Range.

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 NGD18N40CLBT4

ELECTRICAL CHARACTERISTICS (continued)

Characteristic Symbol Test Conditions Temperature Min Typ Max Unit
ON CHARACTERISTICS (continued) (Note 3)
Collector−to−Emitter On−Voltage
g VCE(on) TJ = 25°C 1.0 1.4 1.6 VDC
IC = 6.0 A,
TJ = 150°C 0.9 1.3 1.6
VGE = 4.0 V
TJ = −40°C 1.1 1.45 1.7*
TJ = 25°C 1.3 1.6 1.9*
IC = 8.0 A,
TJ = 150°C 1.2 1.55 1.8
VGE = 4.0 V
TJ = −40°C 1.4 1.6 1.9*
TJ = 25°C 1.4 1.8 2.05
IC = 10 A,
TJ = 150°C 1.4 1.8 2.0
VGE = 4.0 V
TJ = −40°C 1.4 1.8 2.1*
TJ = 25°C 1.8 2.2 2.5
IC = 15 A,
TJ = 150°C 2.0 2.4 2.6*
VGE = 4.0 V
TJ = −40°C 1.7 2.1 2.5
TJ = 25°C 1.3 1.8 2.0*
IC = 10 A,
TJ = 150°C 1.3 1.75 2.0*
VGE = 4.5 V
TJ = −40°C 1.4 1.8 2.0*
Forward Transconductance gfs VCE = 5.0 V, IC = 6.0 A TJ = −40°C to 8.0 14 25 Mhos
150°C
DYNAMIC CHARACTERISTICS
Input Capacitance CISS 400 800 1000 pF
VCC = 25 V, VGE = 0 V TJ = −40°C
40°C to
Output Capacitance COSS 50 75 100
f = 1.0 MHz 150°C
Transfer Capacitance CRSS 4.0 7.0 10
SWITCHING CHARACTERISTICS
Turn−Off Delay Time (Resistive) td(off) VCC = 300 V, IC = 6.5 A TJ = 25°C − 4.0 10 µSec
RG = 1.0 kΩ, RL = 46 Ω,
Fall Time (Resistive) tf VCC = 300 V, IC = 6.5 A TJ = 25°C − 9.0 15
RG = 1.0 kΩ, RL = 46 Ω,
Turn−On Delay Time td(on) VCC = 10 V, IC = 6.5 A TJ = 25°C − 0.7 4.0 µSec
RG = 1.0 kΩ, RL = 1.5 Ω
Rise Time tr VCC = 10 V, IC = 6.5 A TJ = 25°C − 4.5 7.0
RG = 1.0 kΩ, RL = 1.5 Ω
3. Pulse Test: Pulse Width  300 µS, Duty Cycle  2%.
*Maximum Value of Characteristic across Temperature Range.

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 NGD18N40CLBT4

TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)

60 60
VGE = 10 V
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

VGE = 10 V 5V
50 50
5V
4.5 V
40 4.5 V 40
TJ = −40°C 4V
4V
30 TJ = 25°C 30
3.5 V
3.5 V
20 20
3V 3V
10 10
2.5 V 2.5 V
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics Figure 2. Output Characteristics

60 60

IC, COLLECTOR CURRENT (AMPS)

VGE = 10 V
IC, COLLECTOR CURRENT (AMPS)

55 VCE = 10 V
50 50
5V 45 TJ = −40°C TJ = 150°C
40 40
TJ = 150°C 4.5 V 35
30 30 TJ = 25°C
4V 25
20 3.5 V 20
15
3V
10 10
2.5 V
5
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VGE, GATE TO EMITTER VOLTAGE (VOLTS)

Figure 3. Output Characteristics Figure 4. Transfer Characteristics

VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

COLLECTOR TO EMITTER VOLTAGE (VOLTS)

4.0 3
TJ = 25°C
3.5 VGE = 5 V
2.5
IC = 25 A
3.0 IC = 15 A
IC = 20 A 2
2.5 IC = 10 A
IC = 15 A
2.0 1.5 IC = 5 A
IC = 10 A
1.5
IC = 5 A 1
1.0
0.5
0.5

0.0 0
−50 −25 0 25 50 75 100 125 150 3 4 5 6 7 8 9 10
TJ, JUNCTION TEMPERATURE (°C) GATE−TO−EMITTER VOLTAGE (VOLTS)

Figure 5. Collector−to−Emitter Saturation Figure 6. Collector−to−Emitter Voltage versus

Voltage versus Junction Temperature Gate−to−Emitter Voltage

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 NGD18N40CLBT4

COLLECTOR TO EMITTER VOLTAGE (VOLTS) 3 10000

2.5 IC = 15 A TJ = 150°C 1000 Ciss

C, CAPACITANCE (pF)
2
IC = 10 A 100 Coss
1.5
IC = 5 A
10 Crss
1

1
0.5

0 0
3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200
GATE TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 7. Collector−to−Emitter Voltage versus Figure 8. Capacitance Variation

Gate−to−Emitter Voltage

2 30
GATE THRESHOLD VOLTAGE (VOLTS)

1.8 VCC = 50 V
VTH + 4 σ
VTH IL, LATCH CURRENT (AMPS) 25 VGE = 5.0 V
1.6
RG = 1000 Ω
1.4 VTH − 4 σ L = 1.8 mH
20
1.2
1 15
L = 3 mH
0.8
10
0.6 L = 6 mH
0.4
5
0.2
0 0
−50 −30 −10 10 30 50 70 90 110 130 150 −50 −25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 9. Gate Threshold Voltage versus Figure 10. Minimum Open Secondary Latch
Temperature Current versus Temperature

30 12
VCC = 50 V VCC = 300 V
IL, LATCH CURRENT (AMPS)

25 VGE = 5.0 V 10 VGE = 5.0 V

RG = 1000 Ω RG = 1000 Ω
SWITCHING TIME (µs)

L = 1.8 mH tf
20 8 IC = 10 A
L = 3 mH L = 300 µH

15 6
L = 6 mH
td(off)
10 4

5 2

0 0
−50 −25 0 25 50 75 100 125 150 175 −50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Typical Open Secondary Latch Figure 12. Inductive Switching Fall Time
Current versus Temperature versus Temperature

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 NGD18N40CLBT4

100 100

COLLECTOR CURRENT (AMPS)

COLLECTOR CURRENT (AMPS)
DC
10 10 DC

100 µs
1 ms
1 1 100 µs
10 ms
1 ms
100 ms
0.1 0.1 100 ms 10 ms

0.01 0.01
1 10 100 1000 1 10 100 1000
COLLECTOR−EMITTER VOLTAGE (VOLTS) COLLECTOR−EMITTER VOLTAGE (VOLTS)

Figure 13. Single Pulse Safe Operating Area Figure 14. Single Pulse Safe Operating Area
(Mounted on an Infinite Heatsink at TA = 25C) (Mounted on an Infinite Heatsink at TA = 125C)

100 100

COLLECTOR CURRENT (AMPS)

t1 = 1 ms, D = 0.05
COLLECTOR CURRENT (AMPS)

t1 = 1 ms, D = 0.05
t1 = 2 ms, D = 0.10 t1 = 2 ms, D = 0.10
10 10
t1 = 3 ms, D = 0.30
t1 = 3 ms, D = 0.30

1 1

0.1 0.1

0.01 0.01
1 10 100 1000 1 10 100 1000
COLLECTOR−EMITTER VOLTAGE (VOLTS) COLLECTOR−EMITTER VOLTAGE (VOLTS)

Figure 15. Pulse Train Safe Operating Area Figure 16. Pulse Train Safe Operating Area
(Mounted on an Infinite Heatsink at TC = 25C) (Mounted on an Infinite Heatsink at TC = 125C)

VBATT = 16 V

VBATT = 16 V
RL = 0.1

RL = 0.1

L = 10 H

L = 10 H
5.0 V VIN RG = 1 k

5.0 V VIN RG = 1 k

RS = 55 m

Figure 17. Circuit Configuration for Figure 18. Circuit Configuration for
Short Circuit Test #1 Short Circuit Test #2

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 NGD18N40CLBT4

100
Duty Cycle = 0.5
R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt)

0.2
0.1
10
0.05
0.02

1 0.01

0.1

0.01
D CURVES APPLY FOR POWER
P(pk)
PULSE TRAIN SHOWN
Single Pulse READ TIME AT t1
t1
0.001
t2 TJ(pk) − TA = P(pk) RJA(t)
RJC
R(t) for t ≤ 0.2 s
DUTY CYCLE, D = t1/t2

0.0001
0.00001 0.0001 0.001 0.01 0.1 1
t,TIME (S)

Figure 19. Transient Thermal Resistance

(Non−normalized Junction−to−Ambient mounted on
minimum pad area)

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 NGD18N40CLBT4

PACKAGE DIMENSIONS

DPAK
CASE 369C−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING
−T− SEATING
PLANE PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B C
INCHES MILLIMETERS
V R E DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
4
D 0.027 0.035 0.69 0.88
Z
A E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
S
1 2 3 G 0.180 BSC 4.58 BSC
U H 0.034 0.040 0.87 1.01
K J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
F J R 0.180 0.215 4.57 5.45
S 0.025 0.040 0.63 1.01
L H U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
D 2 PL Z 0.155 −−− 3.93 −−−
STYLE 7:
G 0.13 (0.005) M T PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR

Thermal Clad is a registered trademark of the Bergquist Company.

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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8