Review on Modular approach for customised UART.

Introduction.
Authors in this a paper proposes UART (Universal a Asynchronous technique
receiver for implementing transmitter) with a new architecture such that the
whole core can be modified for the desired specifications and can be
integrated in a bigger design, wherever UART is necessary. The given paper is
implementing the design through Verilog HDL using Xilinx 14.2 design suite and
it is tested on Spartan-6 FPGA .

Earlier version of UART.

UART(Universal Asynchronous Receiver Transmitter) is used fro transmission
between devices. It converts parallel data into a serial and transmits through
the wire. With the ever increasing demand of the high speed data exchanges
are being hindered by the increasing dynamic power consumption. We need to
change the architecture and methods of transmission to meet the higher
demand of power consumption and high speed.

Customised UART.
Authors designed an architecture, which allows us to modify and customize the
specifications and directly use it to fit the whole core into a bigger design. The
modifiable parameters include

 System clock frequency (default-50MHz).

 Baud rate.
 Number of parity bits (default 1).
 Number of stop bits (1/1.5/2).
 Oversampling factor (8/16).
 The FIFO buffer parameters.

As per the requirements we can make changes in the core of UART to suit our
purpose of speed and power consumption. Complete UART core containing the
baud rate generator, transmitter module, the receiver module and the FIFO
buffers.
With the oscillator clock frequency and baud rate it is possible to calculate
baud rate frequency which can be operated as divider factor. In this, obtained
frequency clock is 16 times baud rate clock instead of equal clock frequency. So
that it is possible to sample precisely asynchronous serial data at receiver.
Expression for baud rate is given by, where M is frequency coefficient.

Frequency Coefficient = Clock Frequency÷ [(Sampling Rate) × (Baud rate)]

M = (32MHz)÷ (16×9600Hz) =208.

By changing the baud rate we can change the frequency coefficient. Which acts
as a dividing factor to increase or decrease the speed of transmission as per
the choice.

Conclusion
The author has created a UART with modified core with the availability of
changing the baud rate and sampling rate. This has enabled the handling of
different speeds of data rate and power consumption efficiently as per the
requirement.