International Journal of VLSI Design and Technology

Vol. 3: Issue 2
www.journalspub.com

Comparision of Adders for High Speed ALU

Rohit Kumar Bairwa*, Chanchal Soni, Roopendra Kumar, Deepak Kumar, Arun Dev Dhar
Dwivedi*
Department of Electrical and Electronic Engineering, Poornima University, Rajasthan, India

ABSTRACT
In this paper, logic optimized multiplexer based adders are incorporated in selected existing
adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder,
and carry save adder and its performance is analyzed in terms of area (slices used) and
maximum combinational path delay as a function of size. Here, different adder architectures
are simulated and analyzed based on power dissipation, area and speed by using Xilinx 14.4
ISE simulator and Verilog HDL. Hence, with the fast developments in the VLSI technology
and design, it is extremely important to include the interconnect sub circuitry during the
simulation process as efficiently as possible.

Keywords: carry look-ahead adder, carry skip adder, FPGA, full adder, half adder

*Corresponding Author
E-mail: adddwivedi@gmail.com, rohit.rohitb.bairwa11@gmail.com

INTRODUCTION
A fast and accurate operation of digital
system is greatly influenced by the
performance of resident adders. The most
important for measuring the quality of
adder designs are computation time and
area. Adders are used not only in the
ALU(s), but also in other parts of the
processor.
The basic principle in designing digital
adder circuit hovers around reducing the
required hardware thus reducing the cost
too. To achieve this, logical optimization
helps to obtaining minimum number of
literals to minimizing the transistor count
and the power consumption and increasing
the speed of operation. It reduces circuit
complexibility, so more flexible Circuit
constructed in processors. VLSI circuits
are available now in your computer, your
car, your brand new state-of-the-art digital
camera, the cell-phones, and what have
you. This technique helps in reducing the
propagation delay and the power
consumption while maintaining low
complexity of logic design.
Adder
In digital electronics adder is a digital
circuit that performs addition of numbers,
these can be classified into 1 bit adders
and multi bit adders. Basic components
for an ALU are Adders in VlSI. There are
N number of adders each with their own
advantages and disadvantages. When two
numbers are to be added and if each of
them is of N bits than we can add them in
two different ways:
(a) Serial adders
(b) Parallel adders
Serial Adders
In serial addition the LSB's are added first
than the carry created are propagated to
the next higher bits. Serial adder is a
digital device capable of adding two
digital n-bit binary numbers, where n
depends on the circuit implementation.
There are two types of adders which are
as follow:
(a) Half adder
(b) Full adder

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Adders for High Speed ALU
Half Adder
A half adder is one of the most basic
combinational logic circuits in computing.
The half adder produces two numbers as
output: the carry and the sum. The sum is
the first digit of the answer, while the carry
is any additional digit. It is called the carry
because it carries over. Half adders only
work with single digit inputs. When
numbers containing more than one digit
are to be combined together, a full adder is
used.
Boolean expression of sum and carry
output of half adder are:
Sum = a XOR b
Carryout = a AND b
Full Adder
The first two inputs are A and B and the
third input is an input carry selected as C
IN. By implementing the full-adder we
would be able to string up eight of them
composed to create a byte-wide adder and
cascade the carry bit from one adder to the
next. The output carry is designated as
Cout and the normal output is designated
as S.
In this truth table, we can see that the
output S is an EXOR between the input A
and the SUM of half-adder output with B
Fig. 1. Half adder.
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Bairwa et al.
and C IN inputs. We must also note that
the C OUT will only be true if any of the
two inputs out of the three are HIGH.
Boolean expression of sum and carry
output of full adder are,
Sum = a XOR b
Carry out = a AND b + b AND c + a AND c
Equation for schematic full adder, are
O = ((I0 * I2) + (I1 * I2) + (I0 * I1));
Parallel Adder
Parallel addition every it added in parallel
without waiting for carry and different
algorithms are used to compensate for the
carry. There are different types of parallel
adders and these are:
(a) Ripple carry adder
(b) Carry look-ahead adder
(c) Carry skip adder
(d) Carry select adder
(e) Carry save adder
Ripple Carry Adder
A ripple carry adder is a logic circuit in
which the carry-out of each full adder is
the carry in of the succeeding next most
significant full adder. It is called a ripple
carry adder because each carry bit gets
rippled into the next stage. In a ripple carry
adder the sum and carry out bits of any of
the half adder stage is not valid until the
carry occurs is of that stage.
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 International Journal of VLSI Design and Technology
Vol. 3: Issue 2
www.journalspub.com

Fig. 2. Full adder gate level block.

Fig. 3. RCA block.

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Adders for High Speed ALU
Fig. 4. RCA concept.
In simple words, the final result of the
ripple carry adder is valid only after the
joint propagation delays of all full adder
circuits inside it.
Carry Look-Ahead Adder
As discussed in ripple carry adder, the
significant delay produced due to ripple
operation is a trade off. This can be
Fig. 5. CLA.
IJVDT (2017) 1–9 © JournalsPub 2017. All Rights Reserved
Bairwa et al.
minimized when carry in to all stages are
computed initially itself, as it will
minimize the wait for carry at every stage
in a n bit adder, hence sum and carryout
expression can be re written as
Sum=(a)XOR(b)XOR(Cin)
Carry out=(Gi)+(Pi).(Cin),
Where, Pi=(a)XOR(b) and Gi=(a).(b).
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 International Journal of VLSI Design and Technology
Carry Skip Adder
A carry-skip adder (also known as a carry-
bypass adder) is an adder implementation
that better on the delay of a ripple-carry
adder with less effort compared to other
adders. The improvement in the worst-case
delay is achieved by using different carry-
skip adders to form a block-carry-skip
adder. In binary system, carry either can be
0 or 1. Only two possibility of value
provides feasibility for choosing between
two. So, if there is a mechanism to select
carry, or better say, skipping carry through
several stages, then delay minimization
can be better obtained.
Carry-skip-adders are chained (see block-
carry-skip-adders) to reduce the overall
critical path.
Carry Select Adder
The carry-select adder basically consists of
two ripple carry adders and a multiplexer.
Fig. 6. Carry skip logic block.
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Vol. 3: Issue 2
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For adding of two n-bit numbers with a
carry-select adder is completed with two
adders (two ripple carry adders) in order to
perform the calculation twice, one time
with the assumption of the carry-in being
zero and the other assuming it would be
one. After calculating both results, the
correct sum, and the correct carry-out, is
then selected with the multiplexer once the
correct carry-in is known.
The general idea of the carry-select adder
is to use blocks of two ripple-carry adders,
one of which is fed with a constant 0
carry-in while the other is fed with a
constant 1 carry-in. Therefore, both blocks
can calculate in parallel.
Carry Save Adder
A carry-save adder is a type of digital
adder, used in computer micro architecture
to compute the sum of three or more n-bit
numbers in binary.
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Adders for High Speed ALU Bairwa et al.

Fig. 7. Carry select adder.

Fig. 8. Basic block carry save adder.

RESULT ANALYSIS verify and a synthesis report gives speed

The design of high speed ALU is
necessary to increase the computation
speed. The VLSI implementation of these
high speed adders are done using RTL
Codes(Verilog HDL) and simulation
process done using Xilinx ISE simulator
14.4. The simulation process helps to
and area of designed circuit. Hence, in this
paper, the analysis of high speed adders
physical and functional parameters like
speed, delay, memory usage, number of
logic gates are measured. The results are
shown below.

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 International Journal of VLSI Design and Technology
Vol. 3: Issue 2
www.journalspub.com

Comparison of Adders
4-bit adders
Table 1. Synthesis report of 4-bit adders.
S. no Parameters Ripple carry Carry look-ahead Carry skip Carry select
1 XOR 1 bit 4 8 8 8
2 NO. of Slices 4/960 4/960 8/4656 9/960
3 Levels of Logic 6 6 6 10
4 CPU Processing Time 17.33 sec 12.42 sec 15.87 sec 15.86 sec
5 Memory usage 250988 kb 251052 kb 250604 kb 251116 kb
6 Logic delay 6.723 ns 7.306 ns 7.306 ns 9.171 ns
7 Route delay 2.236 ns 2.576 ns 2.738 ns 4.032 ns
8 Total delay 8.959 ns 9.882 ns 10.044 ns 13.203 ns

8-bit adders
Table 2. Synthesis report of 8-bit adders.
S.no Parameters Ripple carry Carry look-ahead Carry skip Carry select
1 XOR 1 bit 8 16 16 24
2 NO. of slices 9/960 15/960 10/4656 18/960
3 Levels of logic 10 7 6 13
4 CPU Processing Time 17.85 sec 13.98 sec 9.09 sec 15.46 sec
5 Memory usage 251116 kb 251628 kb 251948 kb 252908 kb
6 Logic delay 9.171 ns 8.010 ns 9.923 ns 10.731 ns
7 Route delay 4.032 ns 3.305 ns 2.431 ns 5.163 ns
8 Total delay 13.203 ns 11.315 ns 9.356 ns 15.894 ns

16-bit adders
Table 3. Synthesis report of 16-bit adders.
S.no Parameters Ripple carry Carry look-ahead Carry skip Carry select
1 XOR 1 bit 16 32 32 24
2 NO. of Slices 18/960 32/960 16/4656 18/960
3 Levels of Logic 18 9 8 13
4 CPU Processing Time 16.20 sec 14.09 sec 9.46 sec 10.23 sec
5 Memory usage 252332 kb 253036 kb 252204 kb 252268 kb
6 Logic delay 14.067 ns 9.418 ns 8.331 ns 10.731 ns
7 Route delay 7.623 ns 4.781 ns 4.047 ns 5.163 ns
8 Total delay 21.690 ns 14.199 ns 12.378 ns 15.894 ns

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Adders for High Speed ALU
CONCLUSION
In this paper, different type of adders like
ripple carry, carry select, carry skip, carry
look-ahead are simulated and synthesized
on the platform Xilinx ISE simulator 14.4
and the parameters of these adders are
captured in synthesized report. Finally, the
parameters like memory usage, levels of
logic, delay are compared for 4-bit, 8-bit
and 16-bit adders.
From Table 3, this review paper concludes
that the carry-skip adder is the efficient
adder in comparision of these parameters,
rather as we know that carry save adder is
most efficient than other adders but carry
skip adder also have high efficient as
compared to ripple carry, carry select
adder, and carry look-ahead adder.
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