Question Bank in VLSI Design and Embedded Systems ---- (Elective- 2) B.E 4/4 (ECE) 1st Sem.

Chapter I. Review of Microelectronics and an Introduction to MOS technology

1) Explain the NMOS fabrication steps with neat diagrams. (P10)
2) Explain the P- well process for a CMOS inverter with neat diagrams. (15)
3) Describe n-well BiCMOS fabrication process steps by giving arrangement of BiCMOS NPN transistor. (23, 25)
4) Compare CMOS , BiCMOS and Bipolar technologies. (22)
5) Discuss alternate forms of Pull-up Configurations and derive the relation between pull –up tp pull-down ratio
for nMOS inverter (41,39)
6) Derive the relation between Ids versus Vds and draw the transfer characteristics between them(27)
Chapter II.MOS and BiCMOS circuit design processes.
1) Draw the stick diagrams and layouts for (a) nMOS inverter (69) (66) (b) CMOS inverter (66) (c) CMOS
dynamic Memory cell (71) (d) 3 Input NAND and NOR gates (See Color plates) (e) Multiplexer (f) Shift Register
2) Sketch λ-based design rules for wires, transistors and contacts. (73)
3) Define Buried contact, Butting contact and Via contact. (75)
4) Sketch 2μm design rules. (83)(Note: Avoid complicated design rules)
5) Sketch 1.2μm design rules. (475) (Note: Avoid complicated design rules)
(Note: Practice all stick diagrams and layouts given in this chapter)
Chapter III. Basic Circuit Concepts
1) Define sheet resistance. (95)
2) Define standard unit of Capacitance and Time delay. (100)
3) Explain about wiring capacitances. (116)
4) Explain various choices of layers. (118)
(Note: Practice all worked out problems on Calculation of Resistance, Capacitance and Inverter delays in
this chapter.)
Chapter IV. Scaling of MOS circuits
1)Draw scaled NMOS transistor and derive all scaling factors for device parameters. Consider Combined V and D
scaling model (125)
2) Explain limitations of scaling. (129)
Chapter V. Subsystem Design and Layout
1) Give the guide lines for a VLSI system design. (147)
2) Explain switch logic and gate logic (restoring logic). (148)
3) Give some switch logic arrangements. (148)
4) Describe the structured design approach of the following combinational logic circuits. (165 onwards).
a) Parity generator b) Bus arbitration logic for n-line bus, c)Multiplexers, d)General logic function block,
e) 4 line gray to binary code converter, f) PLA
Chapter VI. Subsystem Design process
1) Describe the design of an ALU subsystem along with stick diagram and floor plan for a CMOS adder element.
(213)
2) Describe the following memory elements. (259)
a) 3 - Transistor dynamic RAM cell, b) One transistor dynamic memory cell, c) Pseudo-static RAM cell.
3) What are the aspects of design tools? Explain (324)
4) Explain Design for testability. (334)
5) Discuss practical design for test guide lines. (341)
6) Explain about Built in self test (BIST). (353)
7) Describe the design of a) Incrementer / Decrementer. (372), b) A comparator for two N bit numbers. (414)
8) Describe (a).Depletion mode MESFET and (b). Enhancement mode MESFET working. (419)
9) Give MESFET based design methodology by giving an example. (455)

NOTE:
i). Refer old question papers also.
ii). The page numbers given with reference to old addition of Pucknell text book.