DIGITAL LOGIC FAMILIES

Walter Joseph,
Asst. Professor,
DEC, RSET.
DIGITAL IC SPECIFICATIONS

Threshold Voltage

Propagation Delay

Power Dissipation

Fan-in

Fan-out (loading factor)

Voltage & Current parameters

Noise Margin

Operating Temperature

Speed Power Product
• Propagation Delay:- time required for a pulse to propagate from
input to output.
• Fan in:- no: of inputs that the gate is designed to handle
• Fan out:- no; of std. loads that the output of a gate can drive
without impairing its normal operation.
• Noise margin:- Noise immunity is the ability of a ckt to tolerate
noise voltages at its inputs. Quantitative measure of noise
immunity is Noise margin.
• Speed Power Product:- for measuring the overall performance of
an IC family. (propagation delay * gate power dissipation)(figure
of merit of an IC family)
Propagation delay

where
tpLH = signal delay time when o/p goes from logic 0
to logic 1
tpHL = signal delay time when o/p goes from logic 1
to logic 0.
 Power Dissipation

where,

I cc ( avg ) VCC = gate supply voltage

PD = Vcc * ICC(avg) = avg ct. drawn from supply by the
n n
entire IC
= no: of gates in IC
ICCH = ct. drawn by the IC when all the
I CCH + I CCL gates are in HIGH state
I cc ( avg ) = ICCL = ct. drawn by the IC when all the
gates are in LOW state
2
 Fan out (loading factor)
Figure 1: Current sourcing in HIGH state
IOH(max)
High state fan out =
IIH

Figure 1

Figure 2: Current sinking in LOW state

IOL(max) Figure 2
LOW state fan out =
IIL
Voltage & current parameters
• VIH(min) : min vge level required at i/p of a gate for that i/p to be
treated as logic 1.
• VOH(min) :
• VIL(max) : max vge level that can be treated as logic 0 at the i/p of a
gate.
• VOL(max) :
• IIH : ct. that flows into an i/p when a specified HIGH level vge is
applied to that input.
• IIL :
• IOH : ct. that flows from an o/p in a logic 1 state under speified
load conditions.
• IOL :
Noise Margin (VN)

VNH= VOH(min) – VIH(min)

VNL= VIL(max) – VOL(max)
 LOGIC FAMILIES
• RTL (Resistor-Transistor logic)

• DCTL (Direct Coupled Transistor logic)

Obsolete
• DTL (Diode-Transistor logic)

• HTL (High Threshold logic)

• TTL - suitable for SSI & MSI. (Transistor-Transistor logic)

• ECL - used in superfast computers. (Emitter Coupled logic)

• IIL - suitable for VLSI & ULSI. (Integrated Injection logic)

• MOS - suitable for LSI.

• CMOS - suitable for SSI, MSI & LSI.
 Bipolar Logic families

• Saturated Logic - RTL,DCTL,DTL,HTL,TTL,IIL

• Non saturated Logic - Schottky TTL,ECL

MOS families
• PMOS- P channel MOSFETs
• NMOS- N channel MOSFETs
• CMOS- Complementary MOSFETs
 Comparison of Logic families

Power
Propagation Noise
Logic dissipation
delay time margin Fan-in Fan-out Cost
Family per gate
(ns) (V)
(mW)
TTL 9 10 0.4 8 10 Low
ECL 1 50 0.25 5 10 High
MOS 50 0.1 1.5 - 10 Low
CMOS < 50 0.01 5 10 50 Low
IIL 1 0.1 0.35 5 8 Very Low
 TTL
 Uses transistors in saturation mode.
 Widely used bipolar family.
 Fastest of the saturated logic families.
 Basic TTL logic ckt is NAND gate.

Sub-families •TTL with passive pull-up

•TTL with totempole output
 Standard TTL
•TTL with open collector
 High Speed TTL • Tristate TTL
 Low Power TTL
 Schottky TTL
 Advanced Schottky TTL
 Low Power Schottky TTL
 Advanced Low Power Schottky TTL
 Fast TTL.
 The Ideal Switching Action of the BJT
• Consider a bipolar transistor in logic circuits .

It is operated in either two states

produces the two logic levels
 Fully conducting state - saturated/turned on (or)
 Fully non-conducting state - cut-off state
Part Numbers
 Two input TTL NAND gate
Totempole
arrangement

Diode : Ensures TC
and TD do not conduct
simultaneously.

Phase Splitter Output Stage

Input Stage
Stage

Figure 1: A 2-
2-input TTL NAND Gate with a Totem Pole Output Stage
NAND Gate Circuit Redrawn with at least One Input LOW
 Operation of TTL NAND gate
Inputs Transistor TA
Transistors Transistor
Emitter Emitter Output
1 2 TB & TD TC
junction 1 junction 2

Forward Forward
Logic 0 Logic 0 Cut off Saturation Logic 1
Biased Biased

Forward Reverse
Logic 0 Logic 1 Cut off Saturation Logic 1
Biased Biased

Reverse Forward
Logic 1 Logic 0 Cut off Saturation Logic 1
Biased Biased

Reverse Reverse
Logic 1 Logic 1 Saturation Cut off Logic 0
Biased Biased
Advantages of Totempole
• Inclusion of TC and D keeps the circuit power dissipation
low.
• In the o/p HIGH state, TC acts as emitter follower with its
associated low impedence. Small time constant for
charging up any capacitive load on the o/p. This action is
called active pull-up & provides very fast rise time
waveforms at the o/p.
Disadvantages of Totempole
• During 0 to 1 transition at o/p, TD turns OFF more slowly
than TC turns ON and relatively large currents will be drawn
from the supply.(as both are on for a few ns). So TTL ckts
suffer from current transients/spikes because of totempole
connection.
• Totempole o/ps cannot be wired ANDed.
Wired AND concept
The Destruction Effect if Totem Pole Outputs
are Tied Together(Wired-AND)

Totem pole outputs tied

together can produce
harmful current through
ON OFF TC1 and TD2

OFF ON
TTL with open collector
 TTL with open collector (cont.)
An open-collector output can present a logic LOW output.
Since there is no internal path from the output Y to the supply
voltage VCC , the circuit cannot present a logic HIGH on its own.
 To function properly an external pull-up resistor, R is being
used as shown.

Use this symbol to

Indicates open
collector output

Symbol : Underlined diamond

Open collector NAND with external resistor.
Advantages of Open Collector Outputs

1. Wired-ANDing - Open-collector outputs can be tied directly

together which results in the logical ANDing of the outputs. Thus
the equivalent of an AND gate can be formed by simply
connecting the outputs.
Advantages of Open Collector Outputs (cont.)

2. Increased current levels - Standard TTL gates with totem-pole outputs

can only provide a HIGH current output of 0.4 mA and a LOW current
of 1.6 mA. Many open-collector gates have increased current ratings
3. Different voltage levels - A wide variety of output HIGH voltages can
be achieved using open-collector gates. This is useful in interfacing
different logic families that have different voltage and current level
requirements

 The big disadvantage of open-collector gates is their slow switching

speed. This is because the value of pull-up resistor is in kΩ, which
results in a relatively long time constants.
Comparison of Totem Pole and Open Collector
Output

The major advantage of using a totem-pole connection is that it

offers low-output impedance in both the HIGH and LOW output
states.
 Tri-state TTL
 combines the advantages of the totem-pole and
open collector circuits
 Three output states are HIGH, LOW, and high
impedance (Hi-Z).
 IN-data input ; EN- enable input for control.
 For EN = 0, regardless of the value on IN (denoted
by X), the output value is Hi-Z.
 For EN = 1, the output value follows the input value

Variations:
Data input, IN, can be inverted
Control input, EN, can be inverted by addition of "bubbles" to signals.
 Hi-Impedance Outputs
 Tristate gate utilize the high-speed
operation of the totem-pole arrangement
when input enabled.
 Permit outputs to be connected together.
 What is a Hi-Z value?
 Both transistor are turned off in the totempole
arrangement.
 This means that, looking back into the
circuit, the output appears to be disconnected
(open circuit).

An equivalent circuit for the

tristate output in the high-Z state
Tri-state Inverter
 Standard TTL Transistor Switching
Problem
• Transistors are driven into deep saturation to fully conduct, or cut
off to switch off.
• The result of deep saturation is that the two junctions are now
forward biased.
• The forward biasing of the BC junction forces a large number of
minority carriers to the collector region.
• When the transistor switches off, these minority carriers needs to
be removed. This takes a finite amount of time called the storage
time (major component of the propagation delay) and thus
increases the switch off time.

31
Solution
• Prevent the transistor from going deep in saturation. This
accomplished by preventing the BC junction from becoming
forward biased.
• The Schottky diode is used to do the above by placing it across
the BC junction. Because of its lower barrier potential, it will
conduct current from the base directly to the collector before the
BC is forward biased. Thus less carriers are stored in the
collector area and the switching becomes much faster.

32
Normal Transistor in saturation Transistor with Schottky diode in saturation

33
 Schottky TTL (74 series)
• Transistors never go to full saturation and thus
increases speed.
• Operates in active or cut off region alone.
• Accomplished by using Schottky barrier Diode(SBD)
b/w base and collector.
• So the collector junction cannot get forward biased.
• Forward voltage : 0.25V
• 54S/74S series have the highest speed among TTL
gates.
Darlington pair
 ECL
• Current-Mode Logic (CML)/ Current-Steering Logic(CSL)
• Operates on the principle of current switching.
• Fastest of all logic families. (tp=1ns)
– Non saturated digital logic family
– Eliminates turn off delay of saturated transistors by operating in active
mode.
– Currents are kept high, o/p impedence is low. So ckt and stray
capacitances can be quickly charged and discharged.
– Has limited voltage swing.
• Consists of difference amplifiers and emitter followers.
• Emitter terminals of 2 transistors are tied together & hence
called ECL.
• Logic LOW : -1.7V ; Logic HIGH : -0.9V
 ECL Inverter
Differential
Amplifier
ECL OR/NOR
Drawbacks of ECL
• High cost
• Low noise margin
• High power dissipation
• Its –ive supply vge and logic levels are not compatible with other
logic families.
• Problem of cooling

Imp. characteristics of ECL

• Transistor never saturate. So high speed
• Logic levels are –ive
• Noise margin is less
• Used as inverter/buffer
• Large fan out (25)
• Large power dissipation
• Total current flow is constant. So no noise spikes will be internally
generated.
MOS Families vs Bipolar Families
• Simpler and inexpensive to fabricate
• Require much less power (PD=0.1mW)
• Better noise margin (1.5V for +5V supply)
• Greater supply voltage range
• Higher fan out (50 for freq > 100Hz & unlimited for low freq)
• Require much less chip area
• Higher reliability
• Slower in operating speed (tp=50ns)
• Susceptible to static charge discharge damage
Deletion Type  NMOS

MOSFET
Enhancement Type PMOS
EQUIVALENTS OF PMOS & NMOS
 NMOS INVERTER
Q1 : Load MOSFET (resistor) (Enhancement/Depletion)
Q2 : Switching MOSFET (Enhancement type only)
NMOS NAND
NMOS NOR
 CMOS
• p channel and n channel MOS devices are fabricated on the same
chip.
• Faster
• Consumes less power (suited for battery operated systems)
• Operated at higher voltages(better noise immunity)
• Very high i/p &(o/p) resistance. so draws almost zero ct. from the
driving gate.
• Very high fan-out
• Noise margin is same for both states. (30% of VDD)
• Increase in VDD results in increase in PD.
• Increased complexity
• Lower packing density
CMOS INVERTER
CMOS NAND
CMOS NOR
Self study
• Subfamilies of TTL & CMOS

References
• Fundamentals of Digital Circuits– Anand
Kumar
• Digital Electronics- G K Kharate