Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
LAB # 3:
Design the combinational circuit using library building technique of VHDL programming
Objective
Frequently used pieces of VHDL code are usually written in the form of
COMPONENTS, FUNCTIONS, or PROCEDURES. Such codes are then placed inside
a PACKAGE and compiled into the destination LIBRARY. The importance of this
technique is that it allows code partitioning, code sharing, and code reuse.
We start by describing the structure of a PACKAGE. Besides COMPONENTS,
FUNCTIONS, and PROCEDURES, it can also contain TYPE and CONSTANT
definitions, among others. Its syntax is presented below
PACKAGE package_name IS
(declarations)
END package_name;
[ PACKAGE BODY package_name IS
(FUNCTION and PROCEDURE descriptions)
END package_name; ]
The syntax is composed of two parts: PACKAGE and PACKAGE BODY. The first part
is mandatory and contains all declarations, while the second part is necessary only when
one or more subprograms (FUNCTION or PROCEDURE) are declared in the upper
part, in which case it must contain the descriptions (bodies) of the subprograms.
PACKAGE and PACKAGE BODY must have the same name.
The declaration list can contain the following COMPONENT, FUNCTION,
PROCEDURE, TYPE, CONSTANT etc.
EXAMPLE:
The example below shows a how to use PACKAGE called my_components. It contains
three components inverter, nand_2 and nand_3 in it.
package my_components is
component myinverter is
port( inv_in: in std_logic; inv_out: out std_logic);
end component;
component nand_2 is
port ( nand2_in1: in std_logic;
nand2_in2: in std_logic;
nand2_out: out std_logic
);
end component;
component nand_3 is
port(
nand3_in1: in std_logic;
nand3_in2: in std_logic;
nand3_in3: in std_logic;
nand3_out: out std_logic
library ieee;
use ieee.std_logic_1164.all;
use work.my_components.all;
entity my_package is
port( a,b,c,d : in std_logic;
x,y: out std_logic);
end my_package;
a b c d x y
PIN_AD27 PIN_AC27 PIN_AC28 PIN_AB28 PIN_G19 PIN_F19
Lab Tasks
Using the techniques, you learned from Part 1, implement a single bit ALU shown below
using VHDL codes and components in your library.
Implement the given ALU by writing VHDL modules and storing in the library. Connect the inputs
in1, in2, C_in, and Selector to switches and the outputs, result and C_out, to LEDs as
Lab Assessment
Pre-Lab /1
Performance /3
/10
Results /2
Viva /2
Lab Report /2
LAB # 4:
Design the sequential circuit using VHDL programming techniques
Objective
Introduction:
Combinational circuits and systems produce an output based on input variables only. Sequential
circuits use current input variables and previous input variables by storing the information and
putting back into the circuit on the next clock (activation) cycle.
Asynchronous Circuit:
Asynchronous sequential circuits do not use a clock signal as synchronous circuits do. Instead the
circuit is driven by the pulses of the inputs. You will not need to know any more about
asynchronous circuits for this course.
D Latch:
Latch is an electronic device that can be used to store one bit of information. The D latch is used to
capture, or 'latch' the logic level which is present on the Data line when the clock input is high. If
the data on the D line changes state while the clock pulse is high, then the output, Q, follows the
input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held in
the latch.
D Flip Flop:
The working of D flip flop is similar to the D latch except that the output of D Flip Flop takes the
state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock
input is active low) and delays it by one clock cycle.
The clock provided by the board is 50MHz, which is too fast for seeing the sequential circuit
output through LEDs for verification. Therefore, we need to divide this clock into a slow clock.
For this, we define two temporary signals.
The slow clock, sclk, is generated through a process and a current statement as shown below:
Note that the 24-bit signal called “clkdiv” is incremented by one per every mclk clock cycle. The
slow clock, sclk, is generated by only copying the 24-th bit of the signal clkdiv. Write a code to
use “sclk” to run the arbitrary sequential circuit. This would allow you to see the changes of
sequential circuit through LEDs.
When you run “Implement Design”, it will give a warning message “… have excessive skew” for
the clock division. Ignore this warning message and generate the bit file. When this bit file is
downloaded to the FPGA, you should see the sequential circuit bit patterns on assigned LEDs.
Don’t forget to test the reset button of this circuit
Lab Tasks
Task 1: The complete code for D- Flip Flop (asynchronous) is given below- test it
Task 2: Write the code for D- Flip Flop (Synchronous) in the space given below.
One of the interesting aspects of using VHDL for implementing a state diagram on a FPGA is
that it does not require the knowledge of flip-flops and the complicated minimization procedures.
The state diagram can be directly implemented using if-then-else (or case-when) constructs,
based on a finite state machine (FSM). For this lab, a counter and a simple sequence detector are
implemented.
A sequence “1101” detector can be designed using the following state diagram.
Important Note:
Notice that you are using a push button switch to generate a slow clock. It is normally zero and
becomes one when pushed. Since the button switch is a mechanical device, it creates oscillation
of signals, called key bouncing, when it is pushed and released. A bouncing waveform is showing
below. The oscillation period is typically less than 20ms.
The routine that filters the bouncing waveform is called a debouncing routine. If you do not
debounce the button signal, a single push of a button sometimes will cause to go through multiple
states, equivalent to multiple pushes. Implement the button debouncing by adding the debounce
routine provided in the link to your library and then calling it. An example of debouncing that
rotates LED lights per each push of a button is shown below’.
In the future, use this debouncing routine whenever a mechanical switch is used.
Write your VHDL Code for to detect 1101 sequence in Figure 4.6:
Lab Assessment
Pre-Lab /1
Performance /3
/10
Results /2
Viva /2
Lab Report /2