UVMF One Bite at a Time

Code Generation Guidelines

Verification Academy Course
Bob Oden
UVM Field Specialist
Objectives & Results

Objectives
 Overview of Code Generation Flow
— Interface, environment, bench
 Provide best practices guidelines
 Provide overview of ALU tutorial

Results
 Increased understanding of generation flow
 Avoid common mistakes
 Faster generation of verification code

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Source Documents

 The information in this presentation is

provided in more detail in the following
documents:
— UVM_Framework_Users_Guide
— UVMF_Code_Generator_YAML_Reference
— ALU_UVMF_Step_By_Step_Guide
 Documents provided in UVMF installation in
the docs directory

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Reference Design
 The same design used in: ALU_UVMF_Step_By_Step_Guide
— Located in $UVMF_HOME/docs/generator_tutorial/ALU_UVMF_Step_By_Step_Guide.pdf

Bench Module

test

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent

ALU

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Flow Overview – The YAML 5-step

1. Design the verification block to be generated

2. Translate the design into YAML

3. Generate the verification block

4. Simulate the generated code

5. Add custom code to generated code

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Steps for Generating an Interface
1. Design the interface to be generated by identifying:
a. Protocol signals
b. Parameters for signals and variables
c. Configuration variables: knobs for controlling protocol behavior
d. Constraints for configuration variables
e. Transaction variables: variables that reflect data transfers
f. Constraints for transaction variables
g. Typedefs
h. Any C code to be used for stimulus generation, etc.
alu_in_agent

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Steps for Generating an Interface
2. Translate the interface design into YAML
— Copy new_interface.yaml as a starting point
Located in $UVMF_HOME/templates/python/examples/yaml_files
— YAML labels and used defined in UVMF_Code_Generator_YAML_Reference
document
Located in $UVMF_HOME/docs

alu_in_agent

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Steps for Generating an Interface
3. Generate the interface
a. yaml2uvmf.py alu_in_interface.yaml
Generated Directories

4. Simulate the interface

a. Interfaces must be simulated within environment alu_in_agent
We’ll talk about creating environments next.

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Steps for Generating an Interface

5. Add custom code to interface

a. src/alu_in_driver_bfm.sv: Add code to implement protocol driving
1. To implement initiator functionality, add signaling code to the
initiate_and_get_response() task.
2. To implement responder functionality, add signaling code to the
respond_and_wait_for_next_transfer() task.
b. src/alu_in_monitor_bfm.sv: Implement protocol monitoring in the
provided do_monitor task.
c. src/alu_in_responder_sequence.svh: If the interface has responder
functionality, complete the body of this sequence

alu_in_agent
Look for UVMF_CHANGE_ME
in genrated source

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Steps for Generating an Interface
5. Add custom code to interface
d. src/alu_in_transaction_coverage.svh : If functional coverage from the
agent is desired, add bins, crosses, etc., to the generated covergroup.
e. src/alu_in2reg_adapter.svh: If the interface will be used with a UVM
register model, fill in the bus2reg() and reg2bus() functions.
f. Add new sequence items based on protocol needs.
1. All new sequence items should be extended from alu_in_transaction.sh
g. Add new sequences based on protocol needs.
1. All new sequences should be extended from alu_in_sequence_base.

alu_in_agent
Look for UVMF_CHANGE_ME
in genrated source

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 Steps for Generating an Environment
1. Design the environment to be generated
a) Identify any environment parameters
b) Create architectural block diagram of
environment
1. Include agents, predictors, scoreboards, coverage
components, etc.
2. Label each component type and instance name
3. Identify agents as initiators or responders
c) Show TLM connections between components alu_environment
1. Label each port and export by instance name and alu_predictor alu_scoreboard
transaction type sent through the connection
2. Numbering each port to help avoid mistakes when
alu_in_agent alu_out_agent
creating YAML

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Steps for Generating an Environment
2. Translate the environment design into YAML
a. Copy new_environment.yaml as a starting point
1. Assume new environment name is alu_in_proj
2. cp new_environment.yaml alu_in_proj_environment.yaml
b. YAML labels and used defined in
UVMF_Code_Generator_YAML_Reference document

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent

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Steps for Generating an Environment
3. Generate the environment
a. yaml2uvmf.py alu_in_proj_environment.yaml alu_in_interface.yaml
Note that YAML must be provided for all contained components
Generated Directories

alu_environment

alu_predictor alu_scoreboard

4. Simulate the environment alu_in_agent alu_out_agent

a. Environments must be simulated in a bench
We’ll talk about creating benches next.
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Steps for Generating an Environment
5. Add custom code to environment
a. src/alu_in_prj_env_configuration.svh: Configure agents as required by
the DUT.
b. Implement the prediction model in the write…ap function within the
predictor class created using the util_components YAML label.
c. Implement the coverage model in the write…ap function within the
coverage class created using the util_components YAML label.

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent

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Steps for Generating an Environment
5. Add custom code to environment
d. Implement any custom scoreboards in the write…ap function within the
scoreboard class created using the defineAnalysisComponent API or
util_components YAML label.
e. Add new sequences as needed in the src directory. All new sequences
should be extended from src/alu_in_prj_sequence_base.svh. Be sure to
add new sequences to the environment package: alu_in_prj_env_pkg.sv

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent
Look for UVMF_CHANGE_ME
in genrated source

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Steps for Generating a Bench

1. Design the bench to be generated by identifying

a. Top level environment
b. Bench parameters and any environment parameter overrides
c. Clock half period and offset
d. Reset duration and assertion level
e. BFM parameters to match agent parameters
f. Which agents are passive Bench Module

test

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent

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Steps for Generating a Bench
2. Translate the bench design into YAML
a. Copy new_bench.yaml as a starting point
1. Assume new bench name is alu
2. Cp new_bench.yaml alu_in_bench.yaml
b. YAML labels and used defined in
UVMF_Code_Generator_YAML_Reference document
Bench Module

test

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent

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Steps for Generating a Bench
3. Generate the bench
a. Yaml2uvmf.py alu_in_bench.yaml alu_in_proj_environment.yaml
alu_in_interface.yaml
Generated Directories

Bench Module

test

alu_environment

alu_predictor alu_scoreboard

4. Simulate the bench alu_in_agent alu_out_agent

a. cd into alu/sim directory

b. Execute: make debug Restricted © 2019 Mentor Graphics Corporation
Steps for Generating a Bench
5. Add custom code to bench
a. Alu/tb/test bench/hdl_top.sv: Instantiate the DUT and connect ports to
the signals in the interface busses, _bus.
b. Sim/Makefile: Update the <benchName>_VERILOG_DUT make variable
with a list of DUT verilog files to compile. Update the
<benchName>_VHDL_DUT make variable with a list of DUT vhdl files to
compile. Bench Module

test ALU

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent
Look for UVMF_CHANGE_ME
in genrated source

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Steps for Generating a Bench
c. Tb/sequences/src/alu_in_bench_sequence_base.svh: Modify the body()
task to reflect the typical test flow.
d. Add new sequences as needed in the alu/tb/sequences/src directory
– All new sequences should be extended from alu_in_bench_sequence_base.
– Be sure to add new sequences to the environment package:
tb/sequences/alu_in_sequence_pkg.sv

Bench Module

test ALU

alu_environment

alu_predictor alu_scoreboard

alu_in_agent alu_out_agent
Look for UVMF_CHANGE_ME
in genrated source

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Generation Tips and Techniques
1. Do the design work up front
2. Start with new_<interface|environment|bench>.yaml
3. Spend a little time checking the YAML before generation
4. Verify the interfaces YAML fields are valid SystemVerilog syntax
5. Verify the environments YAML fields are valid SystemVerilog syntax
6. Verify the util_components YAML fields are valid SystemVerilog syntax
7. Verify the benches YAML fields are valid SystemVerilog syntax
8. Ensure emulation readiness
9. Always simulate generated code before making hand edits
10. After the generated code simulates, add custom code incrementally
11. After the generated code simulates, add custom code from the DUT pins out
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Generation Tips and Techniques #1
 Do the Design work up front
— Design the interface, environment, bench first
— Translate the design into YAML second
— Increased detail in the design work simplifies creation of YAML
— Increased detail in the design work decreases regeneration iterations

Engineering Analysis is still Required!

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Generation Tips and Techniques #2
 Start with new_<interface|environment|bench>.yaml
— All relevant YAML constructs included as comments
— Uncomment constructs as needed
— Prevents construct misspelling
— Provides required construct sub-fields and formatting
— Helps avoid indentation errors

Remember, YAML is indentation sensitive

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Generation Tips and Techniques #3
 Spend a little time checking the YAML before generation
— Make sure types are correct
– Component type names should match YAML that defines the component
– Agent type should match an interface type, sub-environment type should match
an environment type, predictors/coverage type should match a util_component
type, scoreboards should match a uvmf scoreboard type
— Make sure instance names are consistent
– Search for occurrences of component instances to verify component connections
— Make sure analysis_port and analysis_export names are consistent
– Search for occurrences of port/export names to verify component connections

Misspelled names, typo’s, extra underscores, etc.,

will create code that generates errors

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Generation Tips and Techniques #4
 Verify the following interfaces YAML fields are valid SystemVerilog
syntax
— parameters type and value
— hvl_pkg_parameters type and value
— hdl_pkg_parameters type and value
— hdl_typedefs type
— hvl_typedefs type
— port reset_value
— transaction_vars type
— transaction_constraints value
— configuration_vars type
— configuration_constraints value
— dpi_define c_return_type and sv_return_type
— dpi_define c_args
— dpi_define sv_args type and dir
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Generation Tips and Techniques #5
 Verify the following environments YAML fields are valid
SystemVerilog syntax
— parameters type and value
— hvl_pkg_parameters type and value
— typedefs type
— configuration_vars type
— configuration_constraints value
— agents parameters value
— subenvs parameters value
— scoreboards parameters value
— scoreboards trans_type
— analysis_ports trans_type
— analysis_exports trans_type
— dpi_define c_return_type and sv_return_type
— dpi_define c_args
— dpi_define sv_args type and dir
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Generation Tips and Techniques #6
 Verify the following util_components YAML fields are valid
SystemVerilog syntax
— parameters type and value
— analysis_exports type
— analysis_ports type

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Generation Tips and Techniques #7
 Verify the following benches YAML fields are valid SystemVerilog
syntax
— parameters type and value

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Generation Tips and Techniques #8
 To ensure Veloce/Strato readiness
— Interface YAML
– veloce_ready flag set to True
– Configuration variables and transaction variables should not have unpacked
dimensions
— Code added to interface driver and monitor BFM’s must be
synthesizable
– Veloce/Strato supports synthesis of subset of behavioral constructs
– See documentation on XRTL
— Bench YAML
– veloce_ready flag set to True
– Use_coemu_clk_rst_gen set to True to use co-emulation clock and reset generator
— Code added to bench hdl_top.sv must be synthesizable

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Generation Tips and Techniques #9
 Always simulate generated code before making hand edits
— Generated code should compile, optimize, load, and run. If not,
there is a mistake in the YAML

Use the simulation error messages to find errors in the YAML

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Generation Tips and Techniques #10
 After the generated code simulates, add custom code
incrementally
— The code requiring debug is proportional to the code modified
between simulation runs

Start with baby steps

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Generation Tips and Techniques #11
 After the generated code simulates, add custom code in the
following order
1. Interface(s)
1. Driver BFM
2. Monitor BFM
3. Add protocol specific sequences
4. Complete covergroup in coverage component
2. Environment(s):
1. Complete covergroup(s) in coverage component(s)
2. Implement prediction model in analysis_export write functions
3. Create environment, reusable, sequences
3. Bench
1. Instantiate the DUT
2. Create test level sequences
3. Create tests that use bench, environment, and interface sequences
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Common Generation Errors
 Not providing all YAML files needed by the generator.
 Typo in YAML.
 Indentation error in YAML.
 Invalid syntax in fields requiring valid SV syntax.
 Inconsistent transaction type or parameterizations between driver and receiver of
tlm_connections or qvip_connections.
 Forgetting the fact that an agent instance with parameter overrides broadcasts
transactions with the same parameter overrides, which is important for
tlm_connections.

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Common Generation Errors – Cont’d
 Missing environment hierarchical reference when specifying driver in
qvip_connections.
 Missing environment hierarchical reference when specifying bfm_name within
active_passive label in bench YAML.
 Missing environment hierarchical reference when specifying bfm_name within
interface_params label in bench YAML.

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Summary

1. Design
The verification block to be generated
2. Translate
The design into YAML
3. Generate
The verification block
4. Simulate
The generated code
5. Add
Custom code to generated code
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