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Introduction to software :
This lab gives basic idea about working on Xilinx FPGAs. The given figures explain all the steps
involved in designing a circuit on FPGA.
Section 1 is the physical implementation of the design into target device i.e. FPGA.
Objectives:
3. Now click on next button and set the properties according to the FPGA board connected.
7. Now name the file and finish the setup to create test file.
11. Now click on next button and set the properties according to the FPGA board connected.
15. Now name the file and finish the setup to create test file.
Some figures shows the procedure and steps to run software, are following.
Spartan-6 FPGA Board:
Spartan-6 LX FPGAs are optimized for applications that require the absolute lowest cost. They support up to 147K
logic cell density, 4.8Mb memory, integrated memory controllers, DSP slices, and high-performance integrated IP
with support for industry standards.
The Spartan®-6 FPGA family comprises two domain-optimized subfamilies with a mix of features matched to
stringent market requirements for price-sensitive, high-volume applications
Key Cabalities:
Comprehensive Connectivity • Connect to more with support for major single and double differential I/O standards
• Connect faster with 1Gb/s differential I/O, multiple 3.2Gb/s integrated serial transceivers, and 12.8Gb/s memory
bandwidth access
• Connect at lower cost with integrated SDRAM memory controller and PCI Express® interfaces
Lowest Cost ; 45nm process technology optimized for low-cost, cost-optimized, wire-bond packaging and
dedicated IP blocks reduce size to help you drive down system costs
High Performance
• Abundant logic resources with increased logic capacity of up to 147K logic cells enables high-performance
systems
• Efficient, second-generation DSP48A1 architectural blocks for high-performance digital signal processing systems
for video, wireless, and many other applications
• Integrated memory controller blocks with streamlined access to external DDR3 memory for video and data
storage applications
Advantages :
Spartan®-6 devices are the most cost-optimized FPGAs, offering industry leading connectivity features such as high
logic-to-pin ratios, small form-factor packaging, and a diverse number of supported I/O protocols. Built on 45nm
technology, the devices are ideally suited for a range of advanced bridging applications found in automotive
infotainment, consumer, and industrial automation.
Disadvantages:
When the syntax is verified , Go to User Constraints and select the I/O pin planning.
By selecting the I/O pin planning , a navigator will be On and select the Yes button.
By hitting the Yes button , a New Planhead Wizard will be opend.Just Close after read.
Planhead wizard shows area of selection of Spartan-6 board for pin constrains. Go to scalar
ports and minimize into port for allocations.
Go to user Hardware User guide for pin assignments and their respective keywords.
Now Enter the Pin assignment keywords as per given in User Guide
i.e. a input E4 , b input F6, c output E13
After pin assignment in user constraints, Go to implement design. And let get it verified.
When design in implemented. Select the Generate programming file.
After generating programming file , enter on the congfigure target device and select the
boundary scan. Add the target device from system.
Open dialogue box will be open. Now give path of .bit file as per created project name.
Configuration operation status will show. By clicking on burn the program option following
will be shown.
Results will be shown on FPGA board
output c;
input a, b;
or(c, a, b);
endmodule
Test Bench:
initial begin
// Initialize Inputs
a=0;
b=0;
#100;
a=1; b=0;
#100;
a=0;b=1;
#100
a=1;b=1;
ISim Simulation:
Implementation of Or-gate:
2.XorGate:
output c;
input a, b;
xor(c, a, b);
endmodule
initial begin
// Initialize Inputs
a=0;
b=0;
#100;
a=1; b=0;
#100;
a=0;b=1;
#100
a=1;b=1;
ISim Simulation:
And gate :
RTL simulation:
Code :
output c;
input a, b;
and(c, a, b);
endmodule
Test bench :
initial begin
// Initialize Inputs
a=0;
b=0;
a=1; b=0;
#100;
a=0;b=1;
#100
a=1;b=1
Results:
2. Nand Gate:
RTL simulation
Code:
output c;
input a, b;
and(c, a, b);
endmodule
Test Bench:
initial begin
// Initialize Inputs
a=0;
b=0;
#100;
a=1; b=0;
#100;
a=0;b=1;
#100
a=1;b=1
ISim Simulation:
5. NOT GATE :
RTL simulations:
Code :
output c;
input a;
not(c, a);
endmodule
Test Bench :
ISim Simulation:
6. XNOR GATE :
Code:
output c;
input a, b;
xnor(c, a, b);
endmodule
initial begin
// Initialize Inputs
a=0;
b=0;
#100;
a=1; b=0;
#100;
a=0;b=1;
#100
a=1;b=1;
ISim Simulations:
7. NOR GATE :
Code:
output c;
input a, b;
nor(c, a, b);
endmodule
Test Bench:
initial begin
// Initialize Inputs
a=0;
b=0;
#100;
a=1; b=0;
#100;
a=0;b=1;
#100
a=1;b=1;
CONCLUSION :
In this lab we have learnt about Verilog language and its designing to make a program for all logic
gates .