Basic Fabrication Steps

and Layout

Somayyeh Koohi
Department of Computer Engineering
Sharif University of Technology
Adapted with modifications from lecture notes prepared by
author
Outline

Fabrication steps
Transistor structures
Transistor behavior
NMOS
PMOS
Latch up

Sharif University of Technology Modern VLSI Design: Chap2 2 of 35

Foundry & Fab

Foundry : fabrication line for hire

Foundries are major sources of fab capacity today
Fab : Design and fabricate

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Silicon Lattice
Semiconductor
Conductivity changed by adding
impurities Si Si Si
Impurities, called dopants, create
either n
n-type
type or pp-type
type regions Si Si Si
Transistors are built on a
Si Si Si
silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds
to four neighbors

Sharif University of Technology Modern VLSI Design: Chap2 4 of 35

Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Groupp V (Arsenic,
Gro (A ): extra
i Phosphorus)
Ph h e tra electron (n-type)
(n t pe)
Group III (Boron): missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

Sharif University of Technology Modern VLSI Design: Chap2 5 of 35

p-n Junctions

A junction between p-type and n-type

semiconductor forms a diode
Current flows only in one direction

N-Diff P-Diff

cathode anode
Sharif University of Technology Modern VLSI Design: Chap2 6 of 35
Fabrication processes
IC built on silicon substrate:
some structures diffused into substrate
other structures built on top of substrate
Substrate regions are doped with n-type and p-type
impurities
(n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple
layers of aluminum (metal)
Silicon dioxide (SiO2) is insulator
Sharif University of Technology Modern VLSI Design: Chap2 7 of 35
 Simple cross section
SiO2 metal3

metal2

transistor metal1
via

poly
n+ n+
p+
substrate
substrate

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Photolithography

Mask patterns are put on wafer using photo-

sensitive material:

Sharif University of Technology Modern VLSI Design: Chap2 9 of 35

Process steps
First place tubs to provide properly-doped substrate for
n-type, p-type transistors:
p-tub n-tub

substrate

Pattern polysilicon before diffusion regions:

poly gate oxide poly

p-tub n-tub

Sharif University of Technology Modern VLSI Design: Chap2 10 of 35

Process steps, cont’d

Add diffusions, performing self-masking:

poly poly

n+ p-tub n+ p+ n-tub p+

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Process steps, cont’d

Start adding metal layers:

metal 1 metal 1

poly vias poly

n+ p-tub n+ p+ n-tub p+

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Outline

Fabrication steps
Transistor structures
Transistor behavior
NMOS
PMOS
Latch up

Sharif University of Technology Modern VLSI Design: Chap2 13 of 35

Transistor structure

n-type transistor:

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 0.25 micron transistor (Bell Labs)
gate oxide

silicide

source/drain

poly

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Transistor layout

n-type (tubs may vary):

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Basic transistor parasitics

Gate to substrate, also gate to source/drain

Source/drain capacitance, resistance

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Basic transistor parasitics (Cont’d)

Gate capacitance Cg
Determined by active area
Source/drain overlap capacitances Cgs, Cgdd
Determined by source/gate and drain/gate overlaps
Independent of transistor L
Cgs = Col W
Drain/bulk & source/bulk capacitance

Sharif University of Technology Modern VLSI Design: Chap2 18 of 35

Outline

Fabrication steps
Transistor structures
Transistor behavior
NMOS
PMOS
Latch up

Sharif University of Technology Modern VLSI Design: Chap2 19 of 35

NMOS Transistor
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 ((oxide)) is a veryy ggood insulator
Called metal – oxide – semiconductor (MOS) capacitor
Even though gate is Source Gate Drain
no longer made of metal Polysilicon
SiO2

n+ n+

p bulk Si

Sharif University of Technology Modern VLSI Design: Chap2 20 of 35

NMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage
P-type body is at low voltage
Source-bodyy and drain-bodyy diodes are OFF
No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Sharif University of Technology Modern VLSI Design: Chap2 21 of 35

NMOS Operation (Cont’d)
When the gate is at a high voltage
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through nn-type
type silicon from source through
channel to drain, transistor is ON
This induced channel forms a resistor (more carriers in the channel,
lower the resistance)
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

Sharif University of Technology Modern VLSI Design: Chap2 22 of 35

NMOS Operation (Cont’d)

Poly-oxide-silicon sandwich under the gate is a

capacitor
To increase voltage, need to add positive charge to
poly
l andd negative
i charge
h to silicon
ili
Initially, negative charge comes from pushing
away holes
After threshold voltage is reached, channel of
mobile electrons formed

Sharif University of Technology Modern VLSI Design: Chap2 23 of 35

PMOS Transistor
Channel carriers have positive charge
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Attracts holes to form a thin p-region allows holes to flow from p+ to p+
G t high:
Gate hi h transistor
t i t OFF
When channel not formed, p+ regions are isolated by back-to-back diodes
Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

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Drain current characteristics

Sharif University of Technology Modern VLSI Design: Chap2 25 of 35

Drain current

Linear region (Vds < Vgs - Vt)

Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds2]
Saturation region (Vds EVgs - Vt)
Id = 0.5k’ (W/L)(Vgs - Vt) 2

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Power Supply Voltage

GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

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0.5 µm transconductances

From a MOSIS process:

n-type:
kn’ = 73 µA/V2
Vtn = 0.7 V
p-type:
kp’ = 21 µA/V2
Vtp = -0.8 V

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Current through a transistor
0.5 µm parameters
W/L = 3/2
Measure at boundary
y between linear and saturation
regions:
Vgs = 2V
Id = 0.5k’(W/L)(Vgs-Vt)2= 93 µA
Vgs = 5V
Id = 1 mA

Sharif University of Technology Modern VLSI Design: Chap2 29 of 35

Outline

Fabrication steps
Transistor structures
Transistor behavior
NMOS
PMOS
Latch up

Sharif University of Technology Modern VLSI Design: Chap2 30 of 35

Latch-up
CMOS ICs have parastic silicon-controlled rectifiers
(SCRs)
When powered up
SCRs can turn on
Creating low-resistance path from power to ground
Current can destroy chip
Early CMOS problem
Can be solved with proper circuit/layout structures

Sharif University of Technology Modern VLSI Design: Chap2 31 of 35

Parasitic SCR structure
Parasitic bipolar transistors (pnp and npn) in a CMOS structure
The well and substrate have resistances RW and RS, respectively
Not completely isolated tubs

Twin tub

n tub

A
Rwell Vwell GND VDD
Y

p+ n+ n+ p+ p+ n+

Vsub Rsub p substrate n well Rwell

Rsub Vwell

substrate tap Vsub

well tap

Sharif University of Technology Modern VLSI Design: Chap2 32 of 35

Parasitic SCR
Two modes of operation:
Both BJTs off
Both BJTs saturated short circuit power supply

circuit I-V behavior

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Solution to latch-up
Use tub ties with small resistance to connect tub to
power rail
n+ (heavily doped): low resistance
Use enough to create low
low-voltage
voltage connection

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Tub tie layout

p+

metal (VDD)

p-tub

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