TetraMAX2 - DSM - 2010 03 - LG PDF

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TetraMAX 2 DSM Test ATPG

Workshop
Lab Guide
30-I-022-SLG-004 2010.03
Synopsys Customer Education Services

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TetraMAX 2 DSM Test ATPG Lab Guide
Synopsys Customer Education Services

1 Modifying the SPF
Learning Objectives
In this lab, you will modify the default STIL file writen
from DFT Compiler to suit your Transition fault model
ATPG requirement.
After completing this lab, you should be able to:
• List the procedure and there WFT used during ATPG
• Adjust the clock timing for Last Shift launch Transition
ATPG
• Adjust the clock timing for System Clock launch
Transition ATPG
Lab Duration:
45 minutes
Modifying the SPF Lab 1-1

Synopsys 30-I-022-SLG-004
Lab 1
Introduction
Objective:
In this lab, you will take the default SPF file written out from DFT Compiler and
edit the same for Transition fault model ATPG.
Answers & Solutions

Each lab contains answers to all questions and results or solutions.
You are encouraged to verify your results by checking the Answers/Solutions

section at the end of each lab.
Lab 1-2 Modifying the SPF
Synopsys TetraMAX 2: DSM Test ATPG Workshop

Lab 1
File Locations
Directory Structure
Reference Directory: ./ref

./ref/lib : Contains library files used in the labs
./ref/netlist : Contains netlist used in the labs
./ref/input : Contains default SPF written out by DFT Compiler
Working Directories:
./lab1_stil_req
./lab2_timing_exp
./lab3_transition_atpg
./lab_SDD_atpg
./lab5_pll_flow
./lab6_path_delay_atpg
Relevant Files for Lab1:

./lab1_stil_req/orca_comp_mode.spf
Working Directory for Lab1:

./lab1_stil_req

Lab 1
Instructions
Your goal is to take the provided SPF file and then create a new SPF file that can be
used for both the last shift launch and system clock launch transition ATPG.
Follow the instructions in the tasks to accomplish this goal.
Task 1. Exploring the default SPF file
In this Task, you will open a default SPF file written out by DFT Compiler.
The design has the following three clocks
Name Period Clock Start Pin
ate_pclk 16.00 ns ate_pclk
ate_sysclk 10.00 ns ate_sysclk
ate_sdrclk 8.00 ns ate_sdrclk
1. Examine the initial .spf file:

Open file orca_scan.spf file present in the working directory. This has
been created by DFT Compiler.
Question 1. List all the Waveform Tables present?
...................................................................................................
Question 2. Do they have the same timing?
...................................................................................................
Question 3. How may capture procedures are there in the “Procedures

ScanCompression_mode_occ_bypass” section?
...................................................................................................
Question 4. How many Tester Cycles does the multiclock_capture

procedure take?
...................................................................................................

Lab 1
Task 2. Modify WFT’s clock timings for Last Shift

Launch
In this Task, you are going to modify the timing of the _default_WFT and
_multiclock_capture_WFT, which are used for last shift launch
Transition ATPG.
1. Copy the file orca_comp_mode.spf to

orca_comp_mode_occ_bypass_at_speed.spf and open it for editing.
2. Decide what changes to make to the waveform table.
In the last shift mode, immediately after the last-shift you will have the
capture of the fault. The time difference between the active edge of ate_pclk
in the last shift and the active edge of ate_pclk in the capture procedure must
be equal to 16ns.
Question 5. What procedure and WFT is used for shifting?
...................................................................................................
Question 6. What procedure and WFT is used during capture for Last
Shift Launch Transition ATPG?
...................................................................................................
The period of _default_WFT_ is 100ns. To get the at-speed behavior you can
have the ate_pclk waveform as { 96 99} in _default_WFT_ and {12 15} in
_multiclock_capture_WFT_. This way the time difference between the two
edges of PCLK is 16ns
"ate_pclk" {P{ '0ns' D; '96ns' U; '99ns' D; } } Æ _default_WFT_
"ate_pclk" {P{ '0ns' D; '12ns' U; '15ns' D; } } Æ _multiclock_capture_WFT_
In a similar way calculate the timing for other clocks
Question 7. What will be the waveform for ate_sysclk in
_multiclock_capture_WFT_ if it is { 96 99 } in the
_default_WFT_?
...................................................................................................
Question 8. What will be the waveform for ate_sdrclk in _default_WFT_

if it is { 4 7 } in the _multiclock_capture_WFT_ ?
...................................................................................................

Lab 1
Question 9. Since you have to do the pre-clock measure, what is the range
for the output strobe for multiclock_capture?
...................................................................................................
Question 10. Is there any need to change the default input delay of 0?
...................................................................................................
3. Correct the timing for the reset pin.

Note: The reset pin would not be used for the transition ATPG but
still we have to make sure that the clock edges are within
the period of the waveform timing and also that it is still a
preclock measure.
Task 3. Modify WFT’s clock timing for System Clock

Launch
In this task, you will modify the clocks for the WFTs used in System Clock Launch
Transition ATPG.
Question 11. What procedure and WFT is used during the launch of the
fault in System Clock Launch Transition ATPG?
...................................................................................................
Question 12. What procedure and WFT is used during the capture of the
...................................................................................................
Adjust the timing of the clocks in the “_allclock_launch_WFT_” and

“_allclock_capture_WFT_” to get the At-Speed pulses. Also, adjust the strobe such
that all the WFTs have a pre-clock strobe.

Answers / Solutions Lab 1
Answers / Solutions
Task 1. Exploring the default SPF file
Question 1. List all the Waveform Tables present?
There are 5 Waveform Tables

WaveformTable "_default_WFT_"
WaveformTable "_multiclock_capture_WFT_"
WaveformTable "_allclock_capture_WFT_"
WaveformTable "_allclock_launch_WFT_"
WaveformTable "_allclock_launch_capture_WFT_"
Question 2. Do they have the same timing?
Yes all have the same timing.

Question 3. How may capture procedures are there in “Procedures
ScanCompression_mode_occ_bypass” section?
There are 4 Capture Procedures
“multiclock_capture”
“allclock_capture”
“allclock_launch”
“allclock_launch_capture”
Question 4. How many Tester Cycles does the multiclock_capture
procedure takes?
It is a single cycle capture procedure.


Lab 1 Answers / Solutions
Task 2. Modify WFT’s clock timings for Last Shift

Launch
Question 5. What procedure and WFT is used for shifting?
The “shift” procedure with “_default_WFT_” WFT.
Question 6. What procedure and WFT is used during capture for Last
Shift Launch Transition ATPG?
The “multiclock_capture” procedure with

“_multiclock_capture_WFT_” WFT.
Question 7. What will be the waveform for ate_sysclk in

_multiclock_capture_WFT_ if it is { 96 99 } in the
_default_WFT_?
"ate_sysclk" { P { '0ns' D; '6ns' U; '9ns' D; } }
Question 8. What will be the waveform for ate_sdrclk in

_default_WFT_ if it is { 4 7 } in the
_multiclock_capture_WFT_ ?
"ate_sdrclk"{P{'0ns'D;'96ns'U;'99ns'D;}}
Question 9. Since you have to do a pre-clock measure, what is the range

for the output strobe for multiclock_capture?
It can be anywhere between 1 to 3 ns. If the strobe is at 4ns

then this is concurrent with the clock. With at ps resolution
the strobe can be till 3999ps
Question 10. Is there any need to change the default input delay of 0?
NO


Task 3. Modify WFT’s clock timing for System Clock

Launch
Question 11. What procedure and WFT is used during the launch of
thefault in System Clock Launch Transition ATPG?
The “allclock_launch” procedure with

"_allclock_launch_WFT_" WFT.
Question 12. What procedure and WFT is used during the capture of the
The "allclock_capture" procedure with

“_allclock_capture_WFT_" WFT.


This page is left blank intentionally.

2 Generating Timing
Exceptions
Learning Objectives
In this lab, you will invoke PrimeTime and generate the

timing exceptions for TetraMAX.
• Generate the SDC file which can be read in TetraMAX
• Mask the timing violations in the SDC file.

Lab Duration:
45 minutes
Generating Timing Exceptions Lab 2-1
Lab 2
Introduction
Objective:
In this lab, you will take care of the false paths and multi-cycle paths in the design.
As these paths are excluded for the STA, the faults on these paths should not be
given a detection credit.
You will use the pt2tmax.tcl utility to generate the SDC file which includes the user
exceptions as well as exceptions which are there for the paths violated.
Answers & Solutions

Each lab contains answers to all questions and results or solutions. You are
encouraged to verify your results by checking the Answers/Solutions section at the
end of each lab.
Lab 2-2 Generating Timing Exceptions

Lab 2
File Locations
Directory Structure

./ref/input : Contains default SPF written out by DFT
Compiler
./ref/script : Contains script for VCS and PrimeTime
./lab1_stil_req
./lab2_timing_exp
./lab4_SDD_atpg
./lab5_pll_flow

../ref/lib/* : Library Files
../ref/netlist/orca_scan.v : Netlist
./pt_lab2_timing_exp.cmd

./lab2_timing_exp

Lab 2
Instructions
Your goal is to define the false path and multi-cycle paths in PrimeTime and to do a
timing analysis. If there are any violated paths then use the utility pt2tmax.tcl to
generate the exceptions for the violated paths. Once all the exceptions are applied
then generate the SDC file for TetraMAX ATPG.
Task 1. Explore the exceptions for TetraMAX
The design has the following False and Multi-cycle paths:
False Paths :
set_false_path -from
I_ORCA_TOP/I_SDRAM_TOP/I_SDRAM_IF/DQ_in_1_reg_0_ \
-to
I_ORCA_TOP/I_SDRAM_TOP/I_SDRAM_READ_FIFO/reg_array_r
eg_1__16_
I_ORCA_TOP/I_PARSER/out_bus_reg_15_ \
-to
I_ORCA_TOP/I_SDRAM_TOP/I_SDRAM_WRITE_FIFO/SD_FIFO_CT
L/U1/empty_int_reg/D
I_ORCA_TOP/I_PARSER/r_pcmd_reg_0_/CP
set_false_path -through
I_ORCA_TOP/I_PARSER/out_bus_reg_7_/Q
set_false_path -to
I_ORCA_TOP/I_PARSER/pci_w_mux_select_reg_0_/D
Multi-cycle Paths :
set_multicycle_path 5 -from
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/UseData_Imm_Or_RegB
_reg/CP \
-to
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg_0_/D

Lab 2
set_multicycle_path 4 -from
I_ORCA_TOP/I_RISC_CORE/I_CONTROL/UseData_Imm_Or_RegB
_reg/CP \
-to
I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg_0_/D
-hold
Note: * These paths have been picked up arbitrarily.

* Test ports in the design are scan_en and test_mode
* Delay has been added to cells to make PT fail for some
paths.
Task 2. Update the Script
In this task you have to edit the PrimeTime Script that is given. You need to look for
the “LAB STEP” section and udpate/add the commands in the script.
1. Open the script pt_lab2_timing_exp.cmd

2. Constrain the ports to do the STA in test mode for At-Speed ATPG
Question 1. What ports have to be constrained for At-Speed ATPG in test
mode?
……………………………………………………………
Update the script with these constraints.
3. Update the script to source pt2tmax.tcl
Question 2. Where is the pt2tmax.tcl utility available?
……………………………………………………
Update the script
4. Copy the Multi-cycle and False path from top to the script
set_false_path …
set_multicycle_path …
Update the script

5. Update the exceptions with the violations


Lab 2
Question 3. What is the command to update the exceptions to take both

hold and setup timing violations in account?
…………………………………………………………
6. Add the command to write the updated SDC.
Update the script
Task 3. PrimeTime Run
1. Run the script in PrimeTime
pt_shell –f pt_lab2_timing_exp.cmd | tee pt_lab2.log
2. Timing Reports
Open the log file to answer the following questions
Question 4. Is there a timing violation with the user exceptions?
……………………………………………………….
Question 5. Is there a timing violation after the exceptions are updated?
………………………………………………………
3. There will be 2 SDC files generated at the end of the PrimeTime run. One
with the violations changed to exceptions and other only with the user
exceptions.
a. orca_scan_user_exception_update.sdc (User Exceptions
Only)
b. orca_scan_user_violation_exceptions.sdc (Both the user
and violation exceptions)
Task 4. SDC generated
1. Compare the SDC generated

Question 6. Is there a difference between the two SDC generated?
………………………………………………………

Answers / Solutions
Task 2. Update the Script

Question 1. What ports have to be constrained for At-Speed ATPG in
test mode?
Ports to be constrained are

Testmode =1, Scan Enable= 0, Resets =1
Question 2. Where is the pt2tmax.tcl utility available?
$env(SYNOPSYS)/auxx/syn/tmax/pt2tmax.tcl
Note: On some machine you may have to use

SYNOPSYS_TMAX variable.
Question 3. What is the command to update the exceptions to take both

hold and setup timing violations in account?
write_exceptions_from_violations –
delay_type min_max
Task 3. PrimeTime Run

Question 4. Is there a timing violation with the user exceptions?
Yes there is are 15 setup and 16 hold violations
Question 5. Is there a timing violation after the exceptions are updated?
No there are no violations after update.

Task 4. SDC generated
Question 6. Is there a difference between the two SDC generated?
Yes there is a difference in SDCs generated.



Transition ATPG and
3 pattern simulation
Learning Objectives
In this lab, you will run TetraMAX to perform ATPG for

the Transition fault model. Also, you will simulate the
patterns in VCS to see the at-speed launch and capture
clocks.
• Set the correct SPF and fault model needed for
Transition ATPG.
• Describe the difference in the fault list for stuck-at and
Transition ATPG
• List some extra constraints needed for Transition ATPG.
• Generate and save the patterns for Transition ATPG
using both the Last shift launch and System clock
launch.
• Simulate the patterns in VCS to see the at-speed launch
and capture pulses.

Lab Duration:
50 minutes
Transition ATPG and Pattern Simulation Lab 3-1
Lab 3
Introduction
Objective
In this lab, you will perform Transition ATPG on a given design.
You will not be targeting for high test coverage. You will generate a few patterns
for both the “Last Shift” and “System Clock” launch methods. The intention here is
to see the at-speed clocks when the patterns are simulated in VCS.
In this lab you will be using the external ATE clocks for At-Speed launch/capture.
In lab5_pll_flow, you will use the internal PLL clocks for At-Speed launch/capture.
In this lab, the focus will be more on Transition ATPG and not on the DRC
violations. How to understand and debug the DRC violations is part of
TetraMAX-1.
Answers & Solutions


Lab 3-2 Transition ATPG and Pattern Simulation

Lab 3
File Locations
Directory Structure

./ref/input : Contains default SPF written out by DFT Compiler
./lab1_stil_req
./lab2_timing_exp
./lab4_sdd_atpg
./lab5_pll_flow

./ref/lib/* : Library Files
./ref/netlist/orca_scan.v : Netlist
./lab1_stil_req/
orca_comp_mode_occ_bypass_at_speed.spf (From lab1)
./lab2_timing_exp/orca_scan_user_violation_exception
s.sdc (From lab2)
Working Directory for Lab3 :


Lab 3
Instructions
Your goal is to take the orca_scan.v netlist and generate 10 patterns for both “last
shift launch” and “system clock launch”. After generating these patterns, simulate
them in VCS and see the at-speed launch and capture pulse.
This lab will use the SPF file “orca_comp_mode_occ_bypass_at_speed.spf”

generated in Lab1 and the SDC file “orca_scan_user_violation_exceptions.sdc”
generated in Lab2.
Task 1. Read the netlist in TetraMAX
1. In this Task, you will invoke TetraMAX and read the library and the netlist
files.Invoke TetraMAX and read the library and the netlist file.
read_netlist ../ref/lib/libs.v.gz –library

read_netlist ../ref/lib/rams.v -library
read_netlist ../ref/netlist/orca_scan.v
2. Since the model of CLKMUL , PLL_1 and PLL_2 are missing it is required
to black box them.
Set_build –black_box { CLKMUL PLL_1 PLL_2 }
3. Build the model and move to DRC mode.
run_build_model ORCA

Lab 3
Task 2. Setup DRC
In this task, you will run drc using the SPF file created in lab1.
1. Set drc to the new SPF file created in lab1.
set_drc ../lab1_stil_req/
orca_comp_mode_occ_bypass_at_speed.spf
The timing exceptions generated in Primetime do not set the false path between the
clock domains.
Question 1. What command should be used to constraint the tool to use a

common launch and capture clock ?
...................................................................................................
set_delay ………………
2. Constrain the reset and the scan enable.

Question 2. You will constrain scan enable and reset to what value?
...................................................................................................
add_pi_constraint ……… prst_n

add_pi_constraint ………… scan_en
3. ORCA design requires the following command to prevent parallel pattern

simulation failure
set_drc -nodslave_remodel
-noreclassify_invalid_dslave
4. Read the SDC file “orca_scan_user_violation_exceptions.sdc” generated in

Lab 2.
read_sdc …………………………………
5. Run drc.
run_drc

Lab 3
Question 3. How many nonscan flip flops are there in the design?
...................................................................................................
Question 4. How many scan chains are there and what is the maximum
chain length?
...................................................................................................
Question 5. Are there any capture violations?
...................................................................................................
Note: You should be in TEST mode , once you have given the
“run_drc” command.
Task 3. Run ATPG
1. In this task, you will set up the ATPG for Transition fault model and then
generate 10 patterns of each kind of launch technique.Define Transition fault
model.
Question 6. What is the default fault model ?
...................................................................................................
Question 7. What is the default launch type ?
...................................................................................................
Note: At any point in the flow you can use the command “report
setting” to see the default or the current settings of any
command.
2. Set the fault model to Transition and launch type to last shift launch.
set_fault –model ………………

set_delay –launch_cycle …………………
3. Add the faults.
add_faults –all
Question 8. How many faults have been added?
...................................................................................................

Lab 3
Question 9. Is the fault list of stuck-at and transition fault models the
same?
...................................................................................................
Question 10. Transition fault model by default does not add faults on what
signals?
...................................................................................................
...................................................................................................
4. Constrain ATPG to generate only 10 patterns.
set_atpg –pattern 10
5. Run atpg
run_atpg –auto
Question 11. What warning messages are you getting ?
...................................................................................................
Question 12. What type of patterns have been generated ?
...................................................................................................
Use the command report_pattern to see what clocks have been used to
capture the faults
report_pattern –type –all
Question 13. Are there multiple capture clocks per pattern?
...................................................................................................
Question 14. What flow will you take if you have to generate patterns
using a single clock?
...................................................................................................

Lab 3
6. Generate the system clock launch pattern.
set_delay –launch_cycle system_clock

run_atpg –auto
Question 15. Are there any new patterns generated ? Why ?
...................................................................................................
7. Increase the pattern limit to 20 and then generate the patterns.
run_atpg –auto
Question 16. What type of patterns are generated now ?
...................................................................................................
Question 17. Are there multiple capture clocks in the new patterns
generated?
...................................................................................................
Question 18. Are there any inter-clock domain patterns generated ?
...................................................................................................
report_pattern –type –all

Lab 3
Task 4. Save the patterns
In this task, you will save the patterns generated and validate them by simulating in
VCS. You will be using the Unified STIL Flow (USF) to validate these patterns.
1. Write out the patterns in the pattern directory .
write_patterns ./pattern/trans_pat.stil -internal -

format STIL -unified_stil_flow -replace
2. Write out the verilog testbench to simulate the patterns generated.
write_testbench -input ./pattern/trans_pat.stil

-output ./pattern/trans_pat_parallel_tb -parameter
{-parallel -replace -log trans_pat_parallel_tb.log}
write_testbench -input ./pattern/trans_pat.stil
-output ./pattern/trans_pat_serial_tb -parameter
{-serial -replace -log trans_pat_serial_tb.log}
3. Check if the testbenches have been created.

Question 19. What are the two files created for the parallel testbench?
-----------------------------------------------------------------
Task 5. Simulate patterns in VCS in Parallel mode
1. Change working directory to “pattern”.

Source the file vcs_tran_parallel. After the compilation the DVE will invoke
with the simulation executable loaded.
2. From the top tab click on “Window Æ New Top Level Frame Æ Hierarchy +
Data + Console”

Lab 3
3. On the Hierarchy Frame select the top module. This will load the signals in
the Variable frame. In the variable Frame Select the following signals with
control key pressed

Lab 3
a. cur_pat[31:0]
b. TM_MODE
c. TM_OCC
d. ate_pclk
e. ate_sdrclk
f. ate_sysclk
g. pll_bypass
h. scan_en
i. test_mode
j. Any other signal in which you are interested….
Keeping the mouse over one of the selected signal , take a right click and then “Add
To Waves Æ New Wave View”

Lab 3
Or after selecting the signals you can click on the “Waveform” at the left top.
Add to
4. You should be able to see the signals loaded in the waveform viewer. Now
you have to simulate the patterns. To simulate the patterns click on the
“Downward Arrow” on the tab.
In the waveform window. Click Here to
Start Simulations
5. At the end of the simulation the waveform window will get updated by itself.
Take a look at the simulated waveform to see the at-speed clocks in both the last
shift launch and system clock launch patterns.

Lab 3
Task 6. Simulating Patterns in VCS in Serial mode

(Optional)
1. Source the file vcs_tran_serial. After the compilation the DVE will invoke
2. Follow the steps 210-24 again
3. Exit all the tools

Answers / Solutions
Task 2. Setup DRC

Question 1. What command should be used to constraint the tool to use
a common launch and capture clock?
“set_delay –common_launch_capture_clock”
Question 2. You will constrain scan enable to what value?
add_pi_constrain 0 scan_en
Question 3. How many nonscan flip flops are there in the design?
37
Question 4. How many scan chains are there and what is the maximum
chain length?
96 Chains, Maximum cells 78

Question 5. Are there any capture violations?
Yes, C6, C12, C13, C16, C17 and C21
Task 3. Run ATPG

Question 6. What is the default fault model?
Stuck-at is the default fault model.

Question 7. What is the default launch type?
The default launch clock is “any”.

Question 8. How many faults have been added?
#uncollapsed_faults=130122
Question 9. Is the fault list of stuck-at and transition fault models the
same?
NO


Question 10. Transition fault model by default does not add faults on
what signals?
The transition fault model does not add faults on the clocks
and the scan_en signals.
Question 11. What warning messages are you getting?
M495: Warning: Merging and pattern limits enabled

without basic-scan minimum detections per pattern.
Question 12. What type of patterns has been generated?
Basic Scan patterns. Last shift launch uses the basic scan
ATPG to generate the patterns.
Question 13. Are there multiple capture clocks per pattern?
Yes there are multiple capture clocks in most of the patterns.

Question 14. What flow will you take if you have to generate pattern
using a single clock?
Constrain all the clocks to their off state, except the clock
that is to be used for capture.
Question 15. Are there any new patterns generated? Why?
NO, since the pattern limit is still 10 patterns.

Question 16. What type of patterns are generated now?
Now, fast-sequential patterns have been generated.

Question 17. Are there multiple capture clocks in the new patterns
generated?
Yes, there are multiple capture clocks in most of the

patterns. Use command “report pattern –type –all”.
Question 18. Are there any inter-clock domain patterns generated?
No, Use command “report pattern –type –all” to see the

clocks used. Same clock is used for both launch and capture.


4 Small Delay Defects

Learning Objectives
In the following lab, you will invoke TetraMAX to

perform ATPG targeting Small Delay Defects
.
• Use PrimeTime to generate the Slack Data File used for
ATPG
• Use TetraMAX to perform ATPG for Small Delay
Defects

Lab Duration:
60 minutes
Small Delay Defects Lab 4-1
Lab 4
Introduction
Objective
In this lab, you will do Small Delay Defect ATPG on given design.
You will use PrimeTime to generate the Slack Data File. The slack data will be used
by TetraMAX to target the faults on the paths with least slacks.
In this lab, the focus will be more on ATPG and not on the DRC violations. How to
understand and debug the DRC violation is part of TetraMAX – 1.
Answers & Solutions


Lab 4-2 Small Delay Defects

Lab 4
File Locations
Directory Structure

./ref/lib: Contains library files used in the labs
./ref/netlist: Contains netlist used in the labs
./ref/input: Contains default SPF written out by DFT Compiler
./lab1_stil_req
./lab2_timing_exp
./lab4_SDD_atpg
./lab5_pll_flow

./lab1_stil_req/orca_scan_at_speed.spf (From lab1)
./lab2/_timing_expt/orca_scan_user_violation_excepti
ons.sdc (From lab2)

./lab4_SDD_flows

Lab 4
Instructions
Your goal is to take the orca_scan.v netlist and generate 10 patterns for each “last
shift launch” and “system clock launch”. After generating these patterns, simulate
the same in VCS and see the at-speed launch and capture pulse.
This lab will use the SPF file “orca_scan_trans.spf ” generated in Lab1 and
“orca_scan_user_violation_exceptions.sdc” generated in lab 2.
Task 1. Generate the Slack Data for SDD ATPG
In this Task, you will invoke PrimTime and generate the slack data to be used
during ATPG.
1. Change Directory to ./lab2_timing_exp

2. Copy the pt_lab2_timing_exp_sol.cmd file as pt_lab4_sdd_atpg.cmd
This script is already constrained to be used for At-Speed ATPG. Along with
the SDC file, you will also generate the slack data to be used for ATPG.
3. Generate Slack Data

Question 1. What is the command to report slack data on each pin?
……………………………………………………………
4. Update the script to redirect the output of the above command to file
orca_scan_comp_mode_occ_bypass_sdd.slack ( Let this be last command
before exit)
report_global_slack >
orca_scan_comp_mode_occ_bypass_sdd.slack
5. Run PrimeTime with the new script.
pt_shell –f pt_lab4_sdd_atpg.cmd
6. Exit PrimeTime.

Lab 4
Task 2. Run TetraMAX and go to Test Mode
In this Task, you will run TetraMAX, read the library, netlist files and give the
needed command to reach the TEST mode.
1. Change directory to lab4_sdd_atpg

2. Invoke TetraMAX and go to test mode.
Question 2. Is there any change required in the Transition SPF file for
SDD ATPG?
… ...............................................................................................
read_netlist ../ref/libs/libs.v.gz –library

read_netlist ../ref/lib/rams.v -library
set_build –black { CLKMUL PLL_1 PLL_2}
run_build_model ORCA
add_pi_constraints ……… (Scan Enable/Resets)
set_delay -common_launch_capture
read_sdc ……
set_drc ../lab1_stil_req/orca_scan_at_speed.spf
## To avoid parallel pattern simulation failure
set_drc -nodslave_remode
set_drc -noreclassify_invalid_dslave
run_drc
Note: You should be in TEST mode , once you have run the
“run_drc” command.

Lab 4
Task 3. Run ATPG
In this task, you will set up ATPG for Small Delay Defect faults and then run the
same. You will generate 10 patterns of each kind of launch technique.
1. Define Transition fault model.
set_fault –model ………………

set_delay –launch_cycle …………………
2. Constrain ATPG to generate only 10 patterns.
3. Read the Slack Data

Question 3. If you run ATPG at this step will it do a SDD based ATPG?
...................................................................................................
Question 4. What is the command to read the timing data ?
...................................................................................................
4. Max Tmgn and Delta for ATPG

Question 5. What is the default value of max_tmgn and Delta? How does
it effect the quality and number of patterns?
...................................................................................................
5. Set the max_tmgn to 30% and delta to 0
set_delay –max_tmgn _ _ _
Question 6. Can the faults with tmgn more than max_tmgn have a DS
classification?
… ...............................................................................................
6. Run ATPG
run_atpg –auto

Lab 4
Question 7. What is absolute value of max_tmgn calculated by

TetraMAX ?
--------------------------------------------------------------------------.
7. Generate the system clock launch patterns.
set_delay –launch_cycle system_clock
run_atpg –auto
Task 4. Reports of SDD Run
1. Take a report on the following fault “ Slow to rise :

I_ORCA_TOP/I_PCI_TOP/I_PCI_CORE/mult_43_L01109_C240_I49/U13/A”
report_fault I_ORCA_TOP/I_PCI_TOP/I_PCI_CORE/U965/Z -slow

r
Question 8. What is the tmgn and delta for this fault?
… ...............................................................................................
report_faults –slack delta
Question 9. How many faults have delta between “2.71 - 3.62”?
… ...............................................................................................
2. Take a report on fault “I_ORCA_TOP/I_BLENDER_0/s4_op2_reg_25_/D ”
report_faults
I_ORCA_TOP/I_BLENDER_0/s4_op2_reg_25_/D -slow r
.. .................................................................................................

Lab 4
Question 11. Why does the fault not have any delta value?
.. .................................................................................................
Question 12. Why is the fault not detected?
.. .................................................................................................
Task 5. Save the patterns

2. Generate the verilog testbench to simulate the patterns.
write_testbench -input ./pattern/sdd_pat.stil -

output ./pattern/sdd_pat_parallel_tb -parameter {-
parallel -replace -log sdd_pat_parallel_tb.log}
write_testbench -input ./pattern/sdd_pat.stil -
output ./pattern/sdd_pat_serial_tb -parameter {-
serial -replace -log sdd_pat_serial_tb.log}
Task 6. Simulate Patterns in VCS in Parallel mode

(Optional)
The pattern simulation will be exactly the same as for the standard Transition Fault
model. If time permits simulate the patterns.
2. Source the file vcs_sdd_parallel. After the compilation the DVE will invoke

Lab 4
Data + Console”

Lab 4
control key pressed
a. cur_pat[31:0]
b. TM_MODE
c. TM_OCC
d. ate_pclk
e. ate_sdrclk
f. ate_sysclk
g. pll_bypass
h. scan_en
i. test_mode
j. Any other signal in which you are interested ….

Lab 4
Add to

Lab 4
“Downward Arrow” on the tab. In the waveform window. Click Here to Start
Simulations
7. Take a look at the simulated waveform to see the at-speed clocks in both last
shift launch and system clock launch.
Task 7. Simulate Pattern in Serial Mode (Optional)
1. Source the file vcs_sdd_serial. After the compilation the DVE will invoke

Answers / Solutions
Task 1. Generate the Slack Data for SDD ATPG

Question 1. What is the command to report slack data on each pin?
report_global_slack
Task 2. Run TetraMAX and go to Test Mode
Question 2. Is there any change required in the Transition SPF file for
SDD ATPG?
No, there is no change needed for the SPF file. The same
SPF file can be used which was used for Transition ATPG.
Task 3. Run ATPG
Question 3. If you run ATPG at this step will it do a SDD based ATPG?
NO, as the slack data has not been read yet.

Question 4. What is the command to read the timing data ?
read_timing
Question 5. What is the default value of max_tmgn and Delta? How
does it affect the quality and number of patterns?
The default value for max_tmgn is “infinity”.

Higher the value of max_tmgn, the better is the quality of
the patterns.
As the value of max_tmgn is raised, the number of patterns
generated increases.
The default value for delta is 0.

The higher the value of delta, the lower will be the number
of patterns.
As the value of delta is increased, the quality of the patterns
decreases.


Question 6. Can the faults with tmgn more than max_tmgn have a DS
classification?
No
Question 7. What is the absolute value of max_tmgn calculated by
TetraMAX ?
run_atpg –auto
The max tmgn for small delay defect faults has been set to
6.04
Task 4. Reports of SDD Run

Tmgn = 14.49 Delta = 0.54
Question 9. How many faults have delta between “2.71 to 3.62”?
Number of faults between 2.55 - 3.82: 4728
str NO
I_ORCA_TOP/I_BLENDER_0/s4_op2_reg_25_/D 0.01
Question 11. Why does the fault not have any delta value?
This fault is not detected so it does not have a delta value.
Question 12. Why is the fault not detected?
It has a timing exception set on the D pin.

5
l5
Transition ATPG
using PLL clocks
Learning Objectives
In this lab, you will invoke TetraMAX to perform ATPG

using PLL clocks. In capture mode the fast clocks from the
PLL will be used to launch and capture the faults. Also,
you will simulate the patterns in VCS to see the at-speed
launch and capture clocks.
• Use QuickSTIL to define the clocks in PLL flow.
• Edit SPF file, to suit your OCC requirements.
• List commands needed to control the number of ATE
and Capture clocks during the capture mode.
• Generate and save the patterns for Transition ATPG for
system clock launch.
• Simulate the pattern in VCS to see the at-speed launch
and capture pulses.
Lab Duration:
60 minutes
Transition ATPG using PLL clocks Lab 5-1
Lab 5
Introduction
Objective
In this lab, you will perform Transition ATPG on the given design with PLL and
OCC. At-speed launch and capture of the fault will happen on the fast clock from
the PLL, instead of the top level port as in Lab3.
Answers & Solutions


Lab 5-2 Transition ATPG using PLL clocks

Lab 5
File Locations
Directory Structure

./ref/spf: Contains default SPF written out by DFT Compiler
./lab1_stil_req
./lab2_timing_exp
./lab5_pll_flow

./ref/netlist/orca_scan_pll_flow.v : Netlist

./lab5_pll_flow

Lab 5
Instructions
Your goal is to take the netlist and generate 30 patterns using system clock launch
where the fast clocks come from PLL. After generating these patterns, simulate the
same in VCS and see the at-speed launch and capture pulse.
This lab will use the QuickSTIL commands in TetraMAX to generate the SPF file.
Once the SPF file is generated, you will edit the same to suit the controller
requirements.
Note: DFT Compiler/DFTMAX can generate the SPF which has the necessary
constructs to run ATPG with PLL. This lab uses the flow where you need to
generate the SPF from TetraMAX.
Since this flow is using the QuickSTIL flow to generate the SPF, you cannot use the
design in Scan Compression mode. Extracting the compressor structures is not
supported.

Lab 5
Task 1. Understand the Design Specifications
In this task we will understand the design. Get to know the various clocks, port
constraint , scan chains etc which are needed to create the SPF file.
ORCA
snps_clk_chain
ate_pclk snps_pll_controller
ate_sdrclk
I_CLOCK_GEN/sdr_occ/U4/Z
ate_sysclk
pll_reset
I_CLOCK_GEN/pclk_occ/U4/Z
pll_bypass
TM_OCC I_CLOCK_GEN/sys_occ/U6/Z
I_CLOCK_GEN/
I_CLOCK_GEN/sys_occ/U7/Z
sdr_clk I_PLL_PCI/CLK
I_PLL_SD/CLK
pclk I_CLKMUL/CLK_1X
sys_clk I_CLKMUL/CLK_2X
scan_en
TM_MODE
prst_n
test_mode
ate_pclk, ate_sdrclk, ate_sysclk

Lab 5
Reference Clocks:
Design has 3 reference clocks
• sdr_clk
• sys_clk
• pclk
PLL Clocks:
The PLL clocks are
• I_CLOCK_GEN/I_PLL_PCI/CLK
• I_CLOCK_GEN/I_PLL_SD/CLK
• I_CLOCK_GEN/I_CLKMUL/CLK_1X
• I_CLOCK_GEN/I_CLKMUL/CLK_2X
OCC BLOCK:
It has the following inputs
• ate_pclk, ate_sdrclk, ate_sysclk : Slow ATE clock.

• pll_reset: Reset pin to reset the OCC.
• pll_bypass: Pin to put the pll in bypass mode.
• scan_en: Scan enable pin of the design
• TM_MODE: Test mode pin of the design
• TM_OCC : Pin to put the OCC in testmode

Lab 5
The Internal clocks from the OCC have the following connections with the
PLL clock and conditions in which the clock is allowed to pass to core.
Clock 1 :
Internal Clock I_CLOCK_GEN/pclk_occ/U4/Z
PLL Source I_CLOCK_GEN/I_PLL_PCI/CLK
Cycle 0 Condition I_CLOCK_GEN/snps_clk_chain_0/U_shftreg_0/ff_1/q_reg/Q

set to 1

set to 1
Clock 2:
Internal Clock I_CLOCK_GEN/sdr_occ/U4/Z
PLL Source I_CLOCK_GEN/I_PLL_SD/CLK

set to 1

set to 1
Clock 3:
Internal Clock I_CLOCK_GEN/sys_occ/U6/Z
PLL Source I_CLOCK_GEN/I_CLKMUL/CLK_1X

set to 1

set to 1

Lab 5
Clock 4:
Internal Clock I_CLOCK_GEN/sys_occ/U7/Z
PLL Source I_CLOCK_GEN/I_CLKMUL/CLK_2X

set to 1

set to 1
Pin Constraints: The following pins have to be constrained during ATPG.
• Constrain 0 : pll_bypass, scan_en, pll_reset and TM_MODE

• Constrain 1 : test_mode, prst_n and TM_OCC
Note: Only signals which are needed for DRC are shown here.
Scan Chains :
Chain Scan Input Scan Output
1 pad[1] sd_DQ[1]
2 pad[2] sd_DQ[2]
3 pad[3] sd_DQ[3]
4 pad[4] sd_DQ[4]
5 pad[5] sd_DQ[5]
6 pad[6] sd_DQ[6]
7 pad[7] sd_DQ[7]
8 pad[8] Sd_DQ[8]
Task 2. Update the script to generate SPF using

QuickSTIL
In this task you have to edit the TetraMAX script that is given. You need to look for
the “LAB STEP” and udpate/add the commands in the script
The script will read the library and the netlist files and run build model to go into
DRC-T mode. Once in DRC-T mode you will use QuickSTIL commands to define
all the clocks of the OCC and generate the SPF file. The necessary pin constraints,
scan paths and the clock information is provided in Task 1.

Lab 5
1. Define the ATE clocks

Synopsys OCC requires that the ATE Clock should pulse even when the
scan enable is low.
add_clocks -shift -ref
Question 1. Is it always needed to pulse the ATE clock during capture?
…………………………………………………………
Question 2. How should an ATE clock be defined if it is to be pulsed
during capture as well?
…………………………………………………………
2. Define the Reference clocks
add_clocks -ref_clock -shift ………………………
Question 3. Can reference clocks have a period different from the ATE
clocks?
…………………………………………………….......
Question 4. What is the command to define a Reference clock with a
period other than that of ATE clock?
………………………………………………………….
Question 5. Can the patterns be written in all the formats if the ATE and
Reference clocks are not same?
………………………………………………………….
Question 6. What is the only supported format if the Reference and ATE
clocks have a asynchronous relation?
…………………………………………………………
Note: You need to define the reference clock as both the reference
and the shift clock for DRC to pass.
3. Define the PLL clocks
add_clocks -pll

Lab 5
Question 7. PLL the clock is a free running clock.
• Yes
• No
………………………………………………………….
Question 8. What is the source of the PLL clock in TetraMAX ?
………………………………………………………….
4. Define the number of capture clock pulses and capture cycles allowed in the
capture mode.
Before defining the Internal clocks you need to define the number of PLL
capture cycles during capture. Depending on this, you will have to define the
condition for each PLL capture cycle to reach the core, when defining the
Internal Clocks. The OCC controller in this design is implemented to support
2 PLL clock pulses duringcapture.
set_drc -num_pll_cycle
5. Define the Internal Clocks
add_clock -int_clock ………………
Question 9. Will the DRC fail if there is not a valid path from PLL clock
to internal clock during capture?
...................................................................................................
6. Define Scan Chains
add_scan_path
7. Define Pin Constraints
add_pi_constraints
8. Define Scan enable
add_scan_eanble

Lab 5
Task 3. Delay Settings
9. Set the correct fault model
Set_fault –model transition
10. Set the launch cycle to system clock launch.
Set_delay –launch_cycle ……………
11. Constrain ATPG to use the same clocks for launch and capture.
set_delay ………………………………
12. Define the number of ATE cycles
This can be a two step process. First you generate the patterns with the default
number of ATE clock cycles. Once the patterns are simulated, you can verify
if the launch and capture pulses are coming with scan enable de-asserted. If
these pulses are late and come once the scan enable is asserted, you need to
increase the cycles for which scan enable is de-asserted. Seeing the simulation
waveforms you can calculate the number of ATE cycles.
For this design you need the number of ATE cycles equal to 3.
set_atpg -min_ateclock_cycles
What is the default number of ATE cycles for which scan enable is low ?
..............................................................................................................................
13. Write out the DRC file.
write_drc lab5_PLL_flow.spf

Lab 5
Task 4. Edit the SPF file to suit the OCC
In this task you will edit the SPF file gnerated in Task3 to suit the OCC requirement.
The SPF file generated from TetraMAX can be used in most cases as is. In case if
there is any specific requirement for OCC you need to edit it and then use the same
for DRC checks. In this task, also you will edit the SPF file so as to pass the DRC.
The OCC implemented in this design, requires a vector before the shift starts. All
the ATE and the Reference clocks need to be pulsed in this vector. Also, it is
required that the OCC is reset before it can be used for ATPG. So, for this you will
assert the OCC's reset pin in the test_setup macro for one cycle with ATE and the
Refclocks constrained to their off state.
14. Open the spf file generated in task 3 in an editor.

15. Edit the load_unload procedure to put a vector before the shift procedure
which pulses the ATE and Reference clocks.
16. Edit the test_setup macro in Macrodef section to assert the pll_reset ( PLL
Reset) signal for one cycle with ATE ,reset and refclocks constrained to their
off state.
17. Save the file.
18. Set this file as the SPF to be used for the DRC checks.
set_drc ……………
Question 10. Do you need to alter the timing in the waveform when using
the OCC ?
……………………………………………………....... ............
simulation failure
20. Run the DRC checks
run_drc
Question 11. What additional DRC checks are done if the OCC is present
in the netlist?
……………………………………………………....... ............

Lab 5
Task 5. Run ATPG
In this task, you will set up ATPG for the Transition fault model and then perform
ATPG to generate 30 patterns.
1. Run ATPG
run_atpg -auto
2. Find the internal clocks used for a pattern

Question 12. How can we know which PLL clock has been used for the
fault detection ?
………………………………………………………………
Task 6. Save the patterns and generate testbench
1. Write out the patterns in the pattern directory.

2. Generate testbench to simulate the patterns
write_testbench -input ./pattern/pll_pat.stil

-output ./pattern/pll_pat_parallel_tb -parameter
{-parallel -replace -log pll_pat_parallel_tb.log}
write_testbench -input ./pattern/pll_pat.stil
-output ./pattern/pll_pat_serial_tb -parameter
{-serial -replace -log pll_pat_serial_tb.log}

Lab 5
Task 7. Simulate Patterns in VCS in Parallel mode
2. Source the file vcs_pll_paralllel. After the compilation the DVE will invoke
Data + Console”

Lab 5
control key pressed
a. cur_pat[31:0] v_count[31:0]
b. TM_MODE TM_OCC
c. ate_pclk ate_sdrclk ate_sysclk
d. pll_bypass pll_reset
e. scan_en test_mode
f. I_CLOCK_GEN/pclk_occ/U4
g. I_CLOCK_GEN/sdr_occ/U4 Capture clocks
h. I_CLOCK_GEN/sys_occ/U7

Lab 5
Add to Waves

Lab 5
“Downward Arrow” on the tab. In the waveform window. Click Here to Start
Simulations
7. Take a look at the simulated waveform to see the at-speed clocks.
Task 8. Simulate Pattern in Serial Mode (Optional)
1. Source the file vcs_pll_serial. After the compilation the DVE will invoke with
the simulation executable loaded.

Answers / Solutions
Task 2. Update the script to generate SPF file using

Quick-STIL
Question 1. Is it always needed to pulse the ATE clock during capture?
No, it is dependent on the OCC implementation. Synopsys

OCC requires the ATE clocks are pulsed in the capture
procedure.
Question 2. How should an ATE clock be defined if it is to be pulsed
during capture as well?
If an ATE clock has to be pulsed during capture it should

also be defined as a reference clock.
Question 3. Can reference clocks have a period different from the ATE
clocks?
Yes, reference clocks can have a period different from the

ATE clock, and mostly it is that way.
Question 4. What is the command to define a Reference clock with
period other than that of ATE clock?
add_clocks 0 ref_clk -refclock –shift –ref_timing {60 40

45}
Question 5. Can the patterns be written in all the formats if the ATE and
Reference clocks are not same?
No, not all the formats are supported

Question 6. What is the only supported formats if the Reference and
ATE clocks have an asynchronous relation?
STIL format only.

Question 7. PLL clock is a free running clock. Yes/No.
Yes
Question 8. What is the source of the PLL clock in TetraMAX?
For TetraMAX the source of the PLL clocks is a black box.

Lab 5
Question 9. Will the DRC fail if there is not a valid path from PLL clock
to internal clock in the capture mode?
Yes, C34 violation is reported.
Task 4. Edit the SPF file to suit the OCC

Question 10. Do you need to alter the timing in the waveform when using
the OCC?
During capture the internal clocks are driven by the PLL.

TetraMAX does not support defining PLL clock timing.
There is no WFT which captures this timing.
The ATE and Reference clock pulse as per the

“multiclock_capture” procedure during capture. If you need
to control its timing you can change the WFT which is used
by this procedure.
In designs which have both the Internal PLL clocks as well

as External clock ports used for At-Speed test, it will be
required to change the WFTs used for At-Speed capture
procedures.
Question 11. What additional DRC checks are done if the OCC is present
in the netlist?
Violations like C34, C39
Task 5. Run ATPG

Question 12. How can we know which PLL clock has been used for the
fault detection?
report_pattern <pattern_number> -clock will give this

information

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6 Path Delay ATPG and
Pattern Simulation
Learning Objectives
In this lab, you will run TetraMAX to perform ATPG

targeting the Path Delay fault model. You will first use
PrimeTime to generate the paths file and exceptions and
then perform ATPG on those faults. At the end, you will
simulate the patterns in VCS to see the at-speed launch and
capture clocks.
• Use PrimeTime to generate the Paths on which ATPG
will be performed.
• In TetraMAX set the correct SPF and fault model
needed for Path Delay ATPG.
• List constraints needed for Path Delay ATPG.
• Generate and save the patterns which detect the faults on
Paths generated in PrimeTime.
• Simulate the pattern in VCS to see the at-speed launch
and capture pulses.
Lab Duration:
60 minutes
Path Delay APTG and Pattern Simulation Lab 6-1
Lab 6
Introduction
Objective
In this lab, you will do Path Delay ATPG. You will use PrimeTime to generate the
Paths which will be read by TetraMAX.
You will select paths from all the clock domains in the design and then target both
the rising and falling transitions on these paths.
Answers & Solutions


Lab 6-2 Path Delay ATPG and Pattern Simulation

Lab 6
File Locations
Directory Structure

./ref/spf: Contains default SPF written out by DFT Compiler
./lab1_stil_req
./lab2_timing_exp
./lab4_SDD_atpg
./lab5_pll_flow

./lab1_stil_req/
orca_comp_mode_occ_bypass_at_speed.spf (From lab1)
./lab2_timing_exp/orca_scan_user_violation_exception
s.sdc (From lab2)

Path Delay ATPG and Pattern Simulation Lab 6-3

Lab 6
Instructions
Your goal is to take the orca_scan.v netlist and generate patterns which target the
paths of the design. The paths will be extracted from PrimeTime using the pt2tmax
utility. This lab will use the SPF file “orca_scan_at_speed.spf ” generated in Lab1.
Follow the instructions in the tasks to accomplish this goal. Use the commands in
grey color box to proceed with the labs.
Task 1. Generate Paths and Exceptions Files using

PrimeTime
In this Task, you will invoke PrimTime and generate the paths on which ATPG will
be performed.
1. Change Directory to ./lab2_timing_exp

2. Copy the pt_lab2.cmd file as pt_lab6.cmd
This script is already constrained to be used for At-Speed ATPG. You will
have to write out critical paths, on which Path Delay ATPG has to be run.
3. Write out the 20 paths from each clock domain using the same launch and
capture clock.
write_delay_path -launch ………… -capture ……………

-max_paths 20 path_delay_fault_pcl_to_pcl.txt
4. Exit.

Lab 6
Task 2. Invoke Tetrmax Read design and Run DRC
In this task, you will invoke TetraMAX and read the design and Run DRC .
1. Invoke TetraMAX and read the library and the netlist file.
read_netlist ../ref/libs/libs.v.gz -library

2. Build the model
set_build –black ………..

run_build_model ORCA_TOP
3. Set drc to the SPF file created in lab1.
set_drc ../lab1_stil_req/orca_scan_at_speed.spf
4. Read the SDC file “orca_scan_user_violation_exceptions.sdc” generated in

Lab 2.
read_sdc …………………………………
5. Define Constraints
Question 1. What ports are needed to be constrained during ATPG?
………………………………………………………….
add_pi_constraints 0 <Scan Enables>

add_pi_constraints 1 <Resets>
Question 2. If the primary inputs and outputs cannot transition at speed

then what should be done?
………………………………………………………….
Question 3. What is the command in TetraMAX to constraint the PIs
and mask Pos?
………………………………………………………….
6. Constraint the ATPG to use the same launch and capture clocks.
set_delay -common_lauch_capture_clocks

Lab 6

simulation failure
8. Run DRC checks
run_drc
Task 3. Run ATPG
In this task, you will set up the ATPG for Path Delay fault model and then run
ATPG on the Paths which were generated in Task1.
1. Define Path Delay fault model.
set_fault –model ……………
Question 4. Does the command "set delay –launch_cycle" have any

effect when doing Path Delay ATPG?
………………………………………………………..
Question 5. If we want to generate patterns only with system clock
launch what shall be done?
………………………………………………………..
Question 6. Is scan enable constrained? What command can you use to
confirm that?
………………………………………………………..
2. Read the paths files generated in Task1.
add_delay_paths ……………………
Question 7. Is there any warning message?
……………………………………………………………

Lab 6
Question 8. Refer to TetraMAX Online Help and give the reason why
we get P21 violations?
……………………………………………………………
Question 9. Will the Paths with P21 violations be targeted for ATPG and
what will be their classification before and after ATPG?
……………………………………………………………
3. Add faults
add_fault -all
Question 10. How many faults were added?
……………………………………………………………
Question 11. What command should be used if you want to add faults for
both rising and falling transition?
……………………………………………………………
4. To avoid long runtime with full sequential ATPG engine, constrain the ATPG
to not use the full sequential engine
set_atpg –nofull_seq_atpg
5. Run ATPG
run_atpg –auto

2. Generate verilog testbench to simulate the STILpatterns.
write_testbench -input ./pattern/trans_pat.stil –

output ./pattern/trans_pat_prallel_tb –parallel

Lab 6
write_testbench -input ./pattern/trans_pat.stil –

output ./pattern/trans_pat_serial_tb –serial
3. Check if the testbenches have been created.

-----------------------------------------------------------------
Task 5. Simulate the patterns in VCS (Optional)

2. Source the file vcs_tran_parallel. After the compilation the DVE will invoke
Data + Console”
control key pressed

Lab 6
a. cur_pat[31:0]
b. TM_MODE
c. TM_OCC
d. ate_pclk
e. ate_sdrclk
f. ate_sysclk
g. pll_bypass
h. scan_en
i. test_mode
j. Any other signal in which you are interested….

Lab 6
Add to Waves

Lab 6
“Downward Arrow” on the tab.
In the waveform window. Click Here to
Start Simulations
7. Take a look at the simulated waveform to see the at-speed clocks in both the
launch on shift ( pattern 0 to 10 ) and system clock launch (11-20).
Task 6. Simulating Patterns in VCS in Serial mode

(Optional)
1. Source the file vcs_tran_serial. After the compilation the DVE will invoke

Answers / Solutions
Task 2. Invoke TetraMAX Read design and Run DRC

Question 1. What ports are needed to be constrained during ATPG?
Scan enable and the reset ports.

Question 2. If the primary inputs and outputs cannot transition at speed
then what should be done?
If these ports cannot transit At-Speed then these should not

be allowed to toggle between the launch and capture clocks.
Question 3. What is the command in TetraMAX to constraint the PIs and
mask POs?
The command to constrain the PI change and PO mask is

set_delay -nopi_change
add_po_mask -all
Task 3. Run ATPG

Question 4. Does the command "set delay –launch_cycle" have any effect
when doing Path Delay ATPG?
No, this command does not have any effect for Path Delay
atpg.
Question 5. If we want to generate patterns only with system clock launch
what shall be done?
If only system clock patterns are needed then constrain the

scan enable to 0 in capture mode.
Question 6. Is scan enable constrained? What command you can use to

confirm that?
Yes, you can use the command report_pi_constraint

Question 7. Is there any warning message?
P21 and P22
Path Delay APTG and Pattern Simulation Lab 6-12
Lab 6
Question 8. Refer to TetraMAX Online Help and give the reason why we
get P21 violations?
Delay paths that violate this rule are combinational false

paths.
Question 9. Will the Paths with P21 violation be targeted for ATPG and
what will be theei classification before and after ATPG?
If the delay path definition is not removed, the associated

path delay faults are classified as undetectable redundant
(UR) and will not be targeted for testing.
Question 10. How many faults were added?
59
Question 11. What command should be used if you want to add faults for
both rising and falling transition?
set_delay -relative_edges


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Modifying the SPF Lab 1-1

Answers & Solutions

You are encouraged to verify your results by checking the Answers/Solutions

Lab 1-2 Modifying the SPF

Synopsys TetraMAX 2: DSM Test ATPG Workshop

Reference Directory: ./ref

Relevant Files for Lab1:

Working Directory for Lab1:

Modifying the SPF Lab 1-3

Synopsys TetraMAX 2: DSM Test ATPG Workshop

Follow the instructions in the tasks to accomplish this goal.

Task 1. Exploring the default SPF file

The design has the following three clocks

Name Period Clock Start Pin

ate_pclk 16.00 ns ate_pclk

ate_sysclk 10.00 ns ate_sysclk

ate_sdrclk 8.00 ns ate_sdrclk

1. Examine the initial .spf file:

Question 2. Do they have the same timing?

Question 3. How may capture procedures are there in the “Procedures

Question 4. How many Tester Cycles does the multiclock_capture

Lab 1-4 Modifying the SPF

Synopsys TetraMAX 2: DSM Test ATPG Workshop

Task 2. Modify WFT’s clock timings for Last Shift

1. Copy the file orca_comp_mode.spf to

Question 8. What will be the waveform for ate_sdrclk in _default_WFT_

Modifying the SPF Lab 1-5

Synopsys TetraMAX 2: DSM Test ATPG Workshop

3. Correct the timing for the reset pin.

Task 3. Modify WFT’s clock timing for System Clock

Adjust the timing of the clocks in the “_allclock_launch_WFT_” and

Lab 1-6 Modifying the SPF

Synopsys TetraMAX 2: DSM Test ATPG Workshop

Task 1. Exploring the default SPF file

Question 1. List all the Waveform Tables present?

There are 5 Waveform Tables

Yes all have the same timing.

There are 4 Capture Procedures

It is a single cycle capture procedure.

Modifying the SPF Lab 1-7

Synopsys TetraMAX 2: DSM Test ATPG Workshop

Task 2. Modify WFT’s clock timings for Last Shift

Question 5. What procedure and WFT is used for shifting?

The “shift” procedure with “_default_WFT_” WFT.

The “multiclock_capture” procedure with

Question 7. What will be the waveform for ate_sysclk in

"ate_sysclk" { P { '0ns' D; '6ns' U; '9ns' D; } }

Question 8. What will be the waveform for ate_sdrclk in

Question 9. Since you have to do a pre-clock measure, what is the range

It can be anywhere between 1 to 3 ns. If the strobe is at 4ns

Lab 1-8 Modifying the SPF

Synopsys TetraMAX 2: DSM Test ATPG Workshop

Task 3. Modify WFT’s clock timing for System Clock

The “allclock_launch” procedure with