ISSN 2322-0929

Vol.02,Issue.01,
January-2014,
Pages:0112-0120

ww.semargroup.org
www.ijvdcs.org

An ASIC Implementation of Automated Teller Machine Controller for

Secured Financial Transactions
PONNA. DIVYA1, AMMIREDDY LAVANYA2, TADI. CHANDRA SEKHAR3
1
Research Scholar, Dept of ECE, GIET Engineering College, Rajahmundry, Andhrapradesh, India,
Email:ponna.divya1@gmail.com.
2
Asst Prof, Dept of ECE, GIET Engineering College, Rajahmundry, Andhrapradesh, India,
E-mail:lavanya.ammireddy@gmail.com.
3
Prof, Dept of ECE, GIET Engineering College, Rajahmundry, Andhrapradesh, India, Email: assprof@rediffmail.com.

Abstract: The high growth of the semiconductor industry over the past two decades has put Very Large Scale Integration in
demand all over the world. The basics of digital logic theory and techniques are easily understood by the design based on VLSI
technology. These are the core fundamentals of the fast, high-speed complex digital circuits. The electronic industry has
achieved a phenomenon growth over the last few decades, mainly due to the rapid advance in semiconductor technologies and
increases the demand in VLSI. In the growing technological world, people want their work to be very simple in order to save
their time. As we know some new technology is becoming popular in banking sector, which is referred as ATMs. It makes the
work of people as well as the banking sectors to be easy. ATMs help in providing money to the people nearer to the living area
by saving their time so that it becoming very popular. In this work the development of a Moore machine state diagram of an
ATM controller. The developed design will be modeled using Verilog HDL language which is a Hardware Description
Language (HDL) used to describe a digital system. The verification of developed model will be made by identifying the
suitable test cases in a test bench. The simulation will be carried out using Modelsim tool and the intended functionality can be
verified with the help of its simulation results and also it can be synthesized using the Xilinx tool.

Keywords: ATM, XILINX, VERILOG, ASIC.

I. INTRODUCTION it becomes user friendly now. In this chapter architecture

Automated Teller Machines (ATM) are banking kiosks
available to consumers 24X7. These serve as data
terminals for convenient money transactions. In these
unattended machines, user has to use the ATM card (a card
with the account information) and provide the Personal
Identification Number (PIN) using a keypad. When the
computer verifies the PIN, the customer gets a choice of
transactions. Adhering to the instructions and entering
proper choices, user can dispense cash, deposit cash,
change PIN or just get an information on account balance.
Basically an ATM (Automated Teller Machine) is the
combination of hardware and software. The hardware used
is card swiper, keypad, display, etc.
The software such as operating system controls this
hardware’s. Now a day’s digital system is entered in
replacing the software. After the invention of ATM,
different groups design the different parts of the system.
But in new generation there are different methods and tools
are emerging, which can handle the design of system from
system level specification. Security, flexibility and
reliability of user’s account get increased due to ATM and
of an ATM is designed and the finite state diagram of the
system is drawn. The system level analysis is made with
the help of FSM of the system. An automated teller
machine (ATM) is a computerized electronic device that
helps the customers of a financial institution to access the
financial transactions in a public place without any help
from others. On most modern ATMs, the customer is
identified by inserting a plastic ATM card with a magnetic
stripe or a plastic smartcard with a chip that contains a
unique card number and some security information, such
as an expiration date. Security is provided by the customer
entering a personal identification number (PIN).
In earlier days customers of one bank can able to access
the ATM machines of that bank only, since banks have
formed cooperative, nationwide networks so that a
customer of one bank can use an ATM of another bank for
cash access. Using an ATM, customers can access their
bank accounts in order to make cash withdrawals or check
their account balances. The types of banking transactions a
customer can carryout are determined by capabilities of the
particular banking machine and the programming of the

Copyright @ 2014 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.

 PONNA. DIVYA, AMMIREDDY LAVANYA, TADI. CHANDRA SEKHAR
institution operating the machine. Now a days ATMs are
used for alternative uses like updating pass books, printing
bank documents, paying bills etc.
II. REVIEW ON ATM
ATMs are becoming increasingly popular because they
make banking functions available to all the customers
around the clock, and at variety of locations, in addition to
banks. In olden days ATMs are manufactured mainly by
using microprocessor or microcontroller. Due to heavier
demands and the falling price of computer like
architectures, ATMs have moved away from custom
architectures using microcontroller and / or integrated
circuits to adopting hardware architecture that is very
similar to a personal computer. Although it is a cheaper to
use commercial hardware, it does not mean that ATMs are
free from some sort of problems exhibited by the personal
computers. With the migration to commodity pc hardware,
standard commercial operating systems and programming
environments can be used in ATMs. Typical platforms
used in ATMs include Microsoft operating systems, Sun
Microsystems, Solaris, Java, Linux and UNIX may also be
used in these environments. In the current scenario Linux
is also playing a leading role in the ATM market place.
Most of the companies are trying to use Linux operating in
there ATMs.
Most ATMs are connected to interbank networks,
enabling people to withdraw and deposit money from
machines not belonging to the bank where they have their
account. This is a convenience; especially for people who
are traveling it is possible to make withdrawals in places
where one's bank has no branches, and even to withdraw
local currency in a foreign country. ATMs mainly consists
of a special type of secure cryptoprocessor, which is a
dedicated microprocessor mainly used for extracting the
information from the card used by the customer. The
security of ATM transactions relies mostly on the integrity
of the secure crypto processor. Many ATMs usually print
each transaction in a printout form that is rolled into a roll
of paper stored inside the ATMs, which allows both the
users of the ATMs and the financial institutions to keep
records, in case there is a dispute. In some cases,
transactions are posted directly to an electronic journal to
reduce the need for paper work. The physical security of
the ATMs can be increased by using the techniques such as
dye markers and smoke canisters. In order to give right
person to access the account, and to increase the security
level in the ATMs, security cameras and security guards
are a common feature and the manufactures also deployed
several different techniques on ATMs. The different
techniques include biometric scanning, bar code scanning
etc.
ATM machines are broken down into two different types
of ATM classifications.
International Journal of VLSI System Design and Communication Systems
Volume.02, IssueNo.01, January-2014, Pages:0112-0120
 Armored ATM: Armored ATM’s are used primarily as
outdoor ATM’s. Such as outdoor entertainment
districts, outdoor flea markets, outdoor concert and
events, etc.
 Non-armored ATM's: Non-armored ATM’s are used
primarily for indoor locations that are closed to the
public when employees are not present. Such as indoor
malls, movie theaters, night clubs, restaurants, bars,
etc
A. Survey on ATM Operations
ATM accesses the bank account through telephone
networking, a host processor and a bank computer to verify
the data. All the operations of ATM are in synchronization
in reference to a common clock source. In case of any
misconnection between the process steps, the whole
transaction is rolled back to effect no change in the account
status.
Figure1. Simple ATM Networking
Banks work to enhance the CRM and integrate the same
at ATMs. It takes care that no tampering and fraud is
possible. For this, the controller of ATM needs to have
complete secured control over the ATM operations. The
ATM Controllers are working on windows based operating
systems, which also provide ease to designers for
programming and modeling its operation. ATM controllers
are sophisticated chip elements designed and programmed
to make the transaction simple and user-friendly.
The ATM must be able to provide the following services
to the customer:
 A customer must be able to make a cash withdrawal
from any suitable account linked to the card;
approval must be obtained from the bank before
cash is dispensed.
 A customer must be able to make a deposit to any
account linked to the card, consisting of cash and/or
checks in an envelope. The customer will enter the
amount of the deposit into the ATM, subject to
manual verification when the envelope is removed
from the machine by an operator. Approval must be
obtained from the bank before physically accepting
the envelope.
 An ASIC Implementation of Automated Teller Machine Controller for Secured Financial Transactions
 A customer must be able to make a transfer of
money between any two accounts linked to the card.
 A customer must be able to make a balance inquiry
of any account linked to the card.
The ATM will communicate each transaction to the bank
and obtain verification that it was allowed by the bank.
Ordinarily, a transaction will be considered complete by
the bank once it has been approved. In the case of a
deposit, a second message will be sent to the bank
indicating that the customer has deposited the envelope. If
the customer fails to deposit the envelope within the
timeout period, or presses cancel instead, no second
message will be sent to the bank and the deposit will not be
credited to the customer. If the bank determines that the
customer's PIN is invalid, the customer will be required to
re-enter the PIN before a transaction can proceed. If the
customer is unable to successfully enter the PIN after three
tries, the card will be permanently retained by the machine,
and the customer will have to contact the bank to get it
back. If a transaction fails for any reason other than an
invalid PIN, the ATM will display an explanation of the
problem, and will then ask the customer whether he/she
wants to do another transaction.
The ATM will provide the customer with a printed
receipt for each successful transaction, showing the date,
time, machine location, type of transaction, account,
amount, and ending and available balance of the affected
account. The ATM will have a key-operated switch that
will allow an operator to start and stop the servicing of
customers. After turning the switch to the "on" position,
the operator will be required to verify and enter the total
cash on hand. The machine can only be turned off when it
is not servicing a customer. When the switch is moved to
the "off" position, the machine will shut down, so that the
operator may remove deposit envelopes and reload the
machine with cash, blank receipts, etc.
The ATM will also maintain an internal log of
transactions to facilitate resolving ambiguities arising from
a hardware failure in the middle of a transaction. Entries
will be made in the log when the ATM is started up and
shut down, for each message sent to the Bank (along with
the response back, if one is expected), for the dispensing of
cash, and for the receiving of an envelope.
B. Design of an ATM Controller
Basically in this work controller for an ATM is created.
There are many different parts of the controller that is
designed. First ATM controller should store the important
information from the Card Swiper. When the CardScanned
line goes high, a new card has been scanned and the data is
valid on both the CardNumber line and the PIN line. Next
ATM controller must be able to parse an entered PIN.
When the Key Entered line goes high, at most one of the
bits of Key will be high. A valid PIN is one that matches
International Journal of VLSI System Design and Communication Systems
Volume.02, IssueNo.01, January-2014, Pages:0112-0120
the one stored from the card, so it is 4 bits long and
contains 1s and 0s. Once the PIN has been entered, the
Enter key should be pressed. (If the Clear button is pressed,
the inputted PIN should be reset). 3 invalid PINs results in
a Locking of the account. When a PIN is invalid, the state
machine should continue to try to get a new PIN until 3
invalid ones have been entered.
Once a valid PIN is entered the user has an option to
either withdraw or deposit money. A deposit consists of
getting the amount from the keypad and then checking
with memory to see if the current balance would overflow
(16 bits) based on the deposit amount. If the amount causes
an overflow, the resulting balance is not written back
memory the “anything Else” signal is asserted as well as
the “Invalid Transaction” signal. In the event that the
transaction is valid, the user is taken to a screen where they
can verify the transaction and new balance (“verify”) from
which an “Enter” input sends a request to update the
balance in memory and upon completion prompts them
with “anything Else”
A withdraw works very similarly. A withdraw amount is
entered from the keypad and then the controller must get
the current balance from memory and determine if you can
remove that much from the account. Again, if it is possible,
the new balance is written to memory, if not then nothing
is written to memory and the Invalid Transaction line goes
high to the display, and then the controller should ask if
there is another transaction to be completed. When the “is
there another transaction?” (“anything Else”) screen is up,
the “0” is no and “1” is yes. “0” will return the user to the
initial state of waiting for a card to be swiped, and “1”
returns them to the “which transaction?” state.
The handshaking with memory works as follows:
 The controller sets Req to high with a valid
account number
 If Lock is HIGH then,
1. Memory will set ReqDone to high when it is
done locking the account.
2. When Req is set to low, ReqDone will go
low.
 Else if Write is LOW then…
1. Memory will set ReqDone to high and have the
current balance on AmmountOut.
2. When Req is set to low, ReqDone will go low.
 Else if Write is HIGH then…
1. Memory will set ReqDone to high when done
writing the new value that is valid on Ammount In
2. When Req is set to low, ReqDone will go low.
C. ATM Controller Block Diagram
All the above blocks integrate together to form the
controller of ATM. The ATM controller as a whole
interacts with all the other blocks of ATM – Card swiper,
 PONNA. DIVYA, AMMIREDDY LAVANYA, TADI. CHANDRA SEKHAR
Key pad, LUT, memory and Display unit. The block
diagram in the figure 1.8 shows the detailed interaction of
the ATM controller with other blocks as well within itself.
To summarize the operation, the ATM controller is
activated on swipe of a card at the card swiper. It then
checks its lock status and asks to enter the PIN only when
unlocked. User has to enter the correct PIN within three
trials, after which ATM corresponds with the memory to
lock the account and no further transaction on the account
Figure2. Block Diagram for ATM Controller
In all cases, and asks if he wants another transaction. If
yes, which option is asked for else, the ATM resets with a
welcome signal, waiting for the next card to be swiped. At
every step, proper signals are generated to display the next
instructions to the user. The display section has a LUT
defined for each signal w.r.t. which the display screen
changes. The signals that trigger the change of display are
also used as the internal control signal to activate various
modules of the controller. This results successful
transactions every time, with elimination of any possibility
of miscalculation.
D. Moore Machine State Diagram for ATM:
Basically FSM is a representation of the different
transition taken place in a system. A state machine is an
effective way to implement the control functions. The
Moore Machine for the overall ATM controller is
represented in fig3. The description of state code and state
input signal are tabulated in table1 and table2.
International Journal of VLSI System Design and Communication Systems
Volume.02, IssueNo.01, January-2014, Pages:0112-0120
is possible. On getting the PIN matched, user is asked for
the option for the operation he wants to do. For both
withdrawal and deposit, he is been provided with the
current balance of the account and asked for the transaction
amount. A viable transaction amounts prompts user to
verify the transaction, else flags an invalid transaction to
the user. Similarly, if user, opts to neglect the verify
option, the transaction goes to be invalid. If verified, the
account details are updated and displayed.
Operation: Initially the system is in idle state and when it
is ready to operate, S0 state is selected which represents
the scan card. When the user gets the card inserted, scan
line goes high which represents the next state S1. If the
card line goes low, control signal will return back to the
scan card state. In state S2, card number and pin number is
stored in the registers. If any error occurs in storing the
card information, the signal will go the state S0. After
storing the card information, control signal will leads to the
screen in which the user allowed to enter the pin which is
represented by the state S3. When the invalid pin is
entered, signal will again goes to state S3 and allow the
user to enter pin again. The counter will be installed which
is represented as S4 state, to count the number of trials. If it
exceeds three times, the account gets locked and control
signal return to scan card (S0) state. When the valid pin is
entered i.e. pin get matched, control signal will lead to the
state S5 in which user can select the transaction type.
There are two types of transaction can be made as follows.
 An ASIC Implementation of Automated Teller Machine Controller for Secured Financial Transactions

1. Deposit Table1. State Code Descriptions

2. Withdraw
Deposit state is represented by S6 in which the user
allowed to deposit the amount through amount entering.
User will be taken again to transaction type screen by
making cancel deposit to high. The amount entered will be
added with the old balance that stored in memory and
checked whether it overflow 16bit, represented by state S7.
If balance get overflowed, control signal will go to invalid
state S8 and then to anything else state S9. The state S10
represents entered amount is valid and is verified. Once
verification is over, the updating of balance is made which
is represented by the state S11. After updating, the signal
will goes to the anything else state S9 from which user will
be allowed to make more transaction by taking to state S5
else to the state S0.

Table2. Input Signal Descriptions

After checking process will be carried out, if amount

entered is invalid, control signal will go to invalid state S8
Figure3. Moore Machine Diagram for ATM and from which signal goes to another transaction state S9.
If the entered amount is valid, then state S14 will be
Withdraw state is represented by S12 in which the user processed which will verify the amount and leads to the
allowed to enter the withdraw amount from his account. If updating balance state S11. In this state, the amount will
the withdraw process is cancelled, signal will again goes to get updated in memory. After updating, user is taken to
the transaction type state S5 else the amount entered will another transaction state S9 from which he can make more
be checked through the state S13. transaction else taken to scan card state.
International Journal of VLSI System Design and Communication Systems
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 PONNA. DIVYA, AMMIREDDY LAVANYA, TADI. CHANDRA SEKHAR
Figure4. General Implementation Flow Diagram
Initially the market research should be carried out which
covers the previous version of the design and the current
requirements on the design. Based on this survey, the
specification and the architecture must be identified. Then
the RTL modelling should be carried out in Verilog HDL
with respect to the identified architecture. Once the RTL
modelling is done, it should be simulated and verified for
all the cases. The functional verification should meet the
intended architecture and should pass all the test cases.
Once the functional verification is clear, the RTL model
will be taken to the synthesis process. Three operations
will be carried out in the synthesis process such as
 Translate
 Map
 Place and Route
The developed RTL model will be translated to the
mathematical equation format which will be in the
understandable format of the tool. These translated
equations will be then mapped to the library that is,
mapped to the hardware. Once the mapping is done, the
gates were placed and routed. Before these processes, the
constraints can be given in order to optimize the design.
Finally the BIT MAP file will be generated that has the
design information in the binary format which will be
dumped in the FPGA board.
International Journal of VLSI System Design and Communication Systems
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E. Implementation Using Verilog HDL:
The implementation of the above Moore machine state
diagram is done by using the Verilog which is the third
generation of verilog IEEE 1800-2005 standard. Basically,
data type is one that will not consider the actual state
encoding that is used in the design and it will allow
implementing the FSM of that design. The user-defined
variables are get updated automatically. The inputs of the
FSM are taken as input to the code that is tabulated in table
2.1 and the output is taken as ‘z’. In the input, pin entered
is of 4-bits and the amount entered for both deposit and
withdraw is of 16-bits which are declared as ‘Logic’. The
output is declared as the ‘Logic’ which is of four states 0,
1, x and z. This data type is identical to reg data type and is
a user defined vector size. The user-defined variables,
shown in table2, are declared in the data type.
Totally three always blocks are used in the code in
which two are sequential and one is combinational. Always
block can be used to infer the combinational and sequential
logic respectively. In first always block, if reset signal is
set the signal will goes to ‘scan card’ state else goes to next
state. Second always block represents the state machine
operation and hence if the input signal is high, control
signal will goes to next state else will goes to the previous
state i.e. corresponding state respectively. The sensitivity
list has ‘negedge clk’ which represents that the change
takes place at every negative edge of the clock signal. Here
the counter is installed which will be counting the entering
of invalid pin. If it exceeds three times, the account gets
locked and the signal will return to initial state and resets
the counter. The (ipin_count) ‘Invalid pin count’ is
declared as a ‘logic’ data type is used to increment the
count. An addition operation is used in the verify state after
which the entered amount gets added with previous
balance. Similarly, a subtraction operation is performed for
withdraw operation in order to subtract the entered amount
with the previous balance. If the net balance is larger than
16-bits, then the transaction will become invalid. In third
always block, the output are declared with respect to the
state. Once the balance gets updated, the output signal is
made to high.
III. RESULTS AND DISCUSSION
The ATM controller and its functionality were discussed
in the previous chapters. Now this chapter deals with the
simulation and synthesis results of the ATM controller
design. Here Modelsim tool is used in order to simulate the
design and checks the functionality of the design. Once the
functional verification is done, the design will be taken to
the Xilinx tool for Synthesis process and the netlist
generation. The Appropriate test cases have been identified
in order to test this modelled ATM controller design.
Based on the identified values, the simulation results which
describes the operation of the ATM controller has been
 An ASIC Implementation of Automated Teller Machine Controller for Secured Financial Transactions

achieved. This proves that the modelled design works
properly as per the process.
A. Simulation Results
The test bench is developed in order to test the modeled
design. This developed test bench will automatically force
the inputs and will make the operations of ATM controller
to perform.
1. Verification Test Cases for the Design
Above code description explains the implementation
process and the different modes of operation. Now the
implemented Verilog code is ready for the verification
process that can be performed by passing the suitable test
cases sequentially. So test passing of test case can be done
through the test bench. These test cases will clearly explain
the operation of an ATM controller and that are can be
verified. Here two initial blocks are available in which the
first block is for declaring the clock and other block is for
providing the test cases in order to verify the operation of
ATM controller, at incremental time period.
The identified test cases are simulated through the
simulation tool and the main module is synthesized using
the synthesis tool. The simulation results are obtained by
using the identified test cases, which shows the different
modes of operation.
Case-1: In this case, the account gets locked due to the
entry of invalid pin for three times is shown in fig5.

Figure5. Account Lock State

The reset signal is set to low and hence process starts
from scan card state. By proper inputs given, the enter pin
state can be reached. At this state, if invalid pin is entered,
the counter starts to work and when count exceeds three,
account gets locked which is clearly shown in fig5.
Case-2: This case shows the overflow condition during
deposit operation i.e. the summation of entered amount and
previous balance exceeds the 16- bits representation.

Figure6. Occurrence of Deposit Overflow Condition

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 PONNA. DIVYA, AMMIREDDY LAVANYA, TADI. CHANDRA SEKHAR

The valid pin (1111) is entered that leads to transaction
type from which deposit is chosen. Once the amount is
entered (65520) for deposit, the deposit check process id
carried out. During checking process, if it exceeds 16-bits,
overflow condition occurs and hence invalid state is
obtained.
Case-3: Here the amount cannot be withdrawn which is
greater than the current balance available in the account
shown in fig7.

Figure7. Occurrence of Invalid Condition in Withdraw minimum period as 11.496 ns. Here, OFFSET IN is the
The withdraw process is chosen in which the withdraw minimum input arrival time before clock and OFFSET
amount (18416) should satisfy the condition mentioned. OUT is maximum output required time after clock.
Once it is not satisfied, during the withdraw amount
checking state it will get caught and hence the invalid state 2. RTL Schematic
is obtained. The RTL (Register Transfer Logic) can be viewed as
black box after synthesize of design is made. It shows the
B. Synthesis Result inputs and outputs of the system. By double-clicking on the
The developed ATM Controller design is simulated and diagram we can see gates, flip-flops and MUX.
verified their functionality. Once the functional verification
is done, the RTL model is taken to the synthesis process
using the Xilinx ISE tool. In synthesis process, the RTL
model will be converted to the gate level netlist mapped to
a specific technology library. This ATM Controller design
can be synthesized on the family of Spartan 3E. Here in
this Spartan 3E family, many different devices were
available in the Xilinx ISE tool. In order to synthesis this
design the device named as “XC3S500E” has been chosen
and the package as “FG320” with the device speed such as
“-4”. The design of ATM Controller is synthesized and its
results were analyzed as follows.

1. Timing Summary:
Speed Grade: -4
Minimum period: 11.496ns (Maximum Frequency:
86.987MHz)
Minimum input arrival time before clock: 6.892ns
Maximum output required time after clock: 4.394ns
Maximum combinational path delay: No path found
In timing summery, details regarding time period and
frequency is shown are approximate while synthesize.
After place and routing is over, we get the exact timing
summery. Hence the maximum operating frequency of this
synthesized design is given as 86.987 MHz and the
Figure8. Schematic with Basic Inputs and Output
IV. CONCLUSION
Basically, ATM controller allows the user to interact
with the memory and hence the security level is increased.
This also makes the transaction in account gets easier. This
work helps to understand the concept of Finite State
Machine and designing architecture of a system. The
familiarization of the procedure to develop the State
Machine diagram of a system through system level

International Journal of VLSI System Design and Communication Systems

Volume.02, IssueNo.01, January-2014, Pages:0112-0120
 An ASIC Implementation of Automated Teller Machine Controller for Secured Financial Transactions

analysis is improved. The ATM block diagram is studied

and the corresponding Moore Machine State diagram is
also analyzed. The FSM is modeled in Verilog HDL and
verified for all the appropriate scenarios. The simulation
results have been verified for the different appropriate test
cases. Finally Hence the maximum operating frequency of
this synthesized design is given as 86.987 MHz and the
minimum time period as 11.496 ns.

V. REFERENCES
[1] K. Rauhala, "Living List Document of Wireless ATM
Working Group", ATM Forum/ltd-watm-01.01, February
1997.

[2] J. Deane, "WATM MAC requirements," ATM Forum/

96-0786, June 1996, MAC layer design issues are
addressed in this document.

[3] D. Raychaudhuri and N. Wilson, "ATM Based

Transport Architecture for Multiservices Wireless Personal
Communication Network", IEEE J. Selected Areas in
Comm., Oct. 1994, pp. 1401-1414.

[4] S. K. Biswas and B. Sengupta, "Call Admissibility for

Multirate Traffic in Wireless ATM Networks",IEEE, 1997.

International Journal of VLSI System Design and Communication Systems

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