CentralTexas What Is Theta JA-CTEA

Package Thermal
Performance
“What is Theta-JA?”
Bennett Joiner & Sriram Neelakantan

June 2013
TM
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are
the property of their respective owners. © Freescale Semiconductor, Inc. 2008. 1
Questions that are addressed:
• How hot will it get?
• How is the temperature rise predicted?
Power dissipation on top
• How is the temperature measured? surface of die
Die temperature: TJ
Case Thermocouple
Ambient
Board Temperature Temperature
Power dissipated in the die is conducted to the top surface of the

package and to the board and then dissipated to the
environment. Orange arrows show the heat flow.
Tj “junction” or die temperature

TA Ambient or air temperature near the device
TB Board temperature at the edge of the device
TC Case temperature
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the property of their respective owners. © Freescale Semiconductor, Inc. 2008.
One Dimensional Thermal Conductivity
A (area of conductor)
T1 L T2
k  A  (T1  T2 ) (T1  T2 ) L
Q or 
L Q kA
Thermal Resistance °C/W
Q - Heat dissipated (watts)
k - Thermal conductivity W/m K
T - Temperature
A - Area
L - Thermal path length
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Cooling: Convection and Radiation (and Conduction)
Convection: Q  h  A  (TS  TF )
h  (TS  TF ) 0.25
Natural Convection h = 5 to 10 W/m2 K
Radiation:
Q      A  (TS4  TW
4
)
Radiation heat transfer is about the same
magnitude as natural convection
These equations are given in all the standard textbooks. Q is heat flow in watts, h is the
convection coefficient, A is the area being cooled, TS is the temperature of the surface being
cooled, TF is the fluid temperature,  is Stefan-Boltzmann constant,  is the emissivity of
the surface, TW is the wall temperature that is cooler than the surface being cooled.
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Electrical vs. Thermal Resistance
Electrical Resistivity Thermal Conductivity

Copper  = 10-6 ohm-cm Copper k = 398 W/m K
Typical plastic  = 1013 to 1015 ohm-cm Typical Plastic k = 0.2 W/m K
20 orders of magnitude difference 3 orders of magnitude difference
You can’t ignore the thermal insulators
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Thermal Resistance Measurement
• Assemble package with thermal die (special die with heater resistors
and a temperature sensor (diode or resistor)
Die
• Solder the package to the thermal test boards
• Apply power, measure the temperatures per the JEDEC specifications
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Junction to Ambient Thermal Resistance (Theta-JA)
Standardized estimate of thermal performance on thermal test board
TJ  TA 
Package
R JA or JA 
P
Specifications
Test Method:
JESD 51-2A
Test Boards:
JESD 51-3
JESD 51-5
JESD51-9 One cubic foot enclosure, natural convection
JESD51-10
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Most Customers don’t use single layer boards, so …
Junction to Ambient Thermal Resistance (Theta-JA) on

Multilayer Board (Usually 2 signal, 2 planes or 2s2p)
Example
196 15x15 MAP PBGA for 6.4 mm die size, 84ASA10536D001
Theta-JA (RJA) (1s board) 51 °C/W
Theta-JA (RJA) (2s2p board) 26
Both are JEDEC specified values (JESD51-2A and JESD51-6). You can find
cases where each is the “right” answer. Make sure that you ask for and report
both values.
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Multiple Components on a Board
120 Natural Convection Results
100
Theta-JA (C/W)
80
60
40
20
0
2s2p Board 1s Board 8 Pkg, 2s2p 16 Pkg, 2s2p
Board Board
Theta-JA (2s2p) 24 °C/W

Theta-JA (1s) 52
Theta-JA (8 packages) 59
Theta-JA (16 packages) 104
Theta-JA using JEDEC specifications

are predictors of thermal performance.
Modeling of application is required.
Eight 119 14x22 mm PBGA on each side of board, 1 W each
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Determine Junction Temperature for Customer
• Customers need to verify junction temperature for components in their

application. The Thermal Characterization Parameter (JT or Psi-JT)
meets that need. It varies slightly with air flow. We normally report
natural convection values.
 JT 
TJ  TC 
P
Natural Convection
Case Thermocouple
Thermocouple should be made with 40 gauge wire with both wire and bead
attached to the top center of the package with thermally conductive epoxy.
Test method defined in JESD51-2. Wire routed next to package body.
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Junction to Case Thermal Resistance
 JC or R JC 
TJ  TC 
P
Tj
Thermal Grease
between Package
and Cold Plate
Thermocouple
Cold Plate
Other surfaces insulated
Theta-JC is used to predict device

Specifications:
performance with a heat sink MIL-SPEC 883, Method 1012
Case thermocouple placed inside cold plate

when tested at Freescale Thermal Labs
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Junction to Board Thermal Resistance
For surface mount devices, most of the heat is dissipated to the board and
then to the rest of the environment. Hence, the thermal resistance to the
board is the most important thermal path. It is determined per the JEDEC
specification JESD51-8.
Board temperature
RJB or JB = (TJ - TB)/P measured with
thermocouple soldered to
trace at center of package
Requires 2s2p
Test Board
Insulation Cooling Channels
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Thermal Resistances (Quick Summary)
Usage
Junction to RJA Single Layer tightly packed array of devices
Ambient Board
Junction to RJA Four layer commonly Used
Ambient board (2s2p)
Junction to RJB sealed box, or customer use in
Board modeling
Junction to RJC heat sinks
Case
Junction to JT Natural determine junction
Package Top Convection temperature from
thermocouple reading
RJX = (TJ – TX)/P
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Application Environments ->
Which Thermal Resistance to Use
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Junction Calculation Summary:
TJ = TA + P*(RJA) Depends on board and local power density
TJ = TB + P*RJB Sealed enclosures, board temperature dominates
TJ = TA + P*(RJC + Rinterface + RSA) With heat sink, include thermal resistance

of interface material and sink to ambient
thermal resistances
Validation of design using case temperature or determination of junction

temperature at test or burn-in.
TJ = TC + JT * P
These equations are simplifications. Heat flows more than one path
which is not included in these equations.
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Package Performance and Design
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Typical Leadframe Package Performance
Abbreviation Enhancement Name Typical Description Wire Theta- Theta-JA
i/o Count Bond JA (1s (2s2p
? board) board)
°C/W °C/W
SOIC, Small Outline 8 to 32 Gull wing Yes 65 to 45 to 90
TSSOP, Package lead, two rows 150
SOP
HSOP, Heat Sink 16 to 32 Die pad should Yes 40 to 70 20 to 30
EP-SOIC Small Outline be soldered to
Package, board
Exposed Pad
QFN Exposed Pad Quad Flat No 16 to 64 I/O pads are Yes 60 to 20 to 150
Lead solder to 280
board, Die pad
should be
soldered to
Board
QFP, LQFP, Quad Flat 32 to 208 Gull Wing Yes 30 to 90 20 to 80
TQFP, Package Leads, four
FQFP, sided
PQFP, etc
EP-QFP Exposed Pad 32 to 100 Die Pad should Yes 50 to 90 20 to 40
be soldered to
board
QFP with Usually Yes 20 to 50 15 to 45
internal 100 to
spreader 240
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Thermal Performance of 100 14x14 LQFP
80
70
X-flag
60
Theta-JA (1s board)
5.1 Solid
50
7.62 Solid
40
8.89 Solid
30 11 Solid X X-Flag
Solid Flag
20
10
0
0 2 4 6 8 10
Die Size (length, mm)
Larger Flag and Die has better thermal performance.

Solid Flag has better thermal performance than X-Flag
Simulations done by Sriram Neelakantan
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Typical Array Package Performance
Abbreviation Enhancement Name Typical Description Wire Theta- Theta-JA
i/o Count Bond JA (1s (2s2p
? board) board)
°C/W °C/W
PBGA Plastic Ball 16 to Yes 30 to 90 20 to 50
Grid Array 1000
TE-PBGA Thermally Wide Four layer 20 to 60 15 to 40
Enhanced range substrate with
thick planes
TE-PBGA2 TE-PBGA Wide Internal Yes 10 to 20% lower
with internal range Spreader thermal resistance
spreader
TBGA Tape Ball Wide Die connected Yes 14 to 20 11 to 15
Grid Array, range to Large
also Copper Plate
fabricated
with laminate
rather than
tape
interconnect
FC-PBGA Flip Chip on Wide Flip Chip No 17 to 50 12 to 25
and FC- either range exposed die vs
CBGA ceramic or lid or spreader
plastic
laminate
substrate
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Typical PBGA (MAP and OMPAC) Thermal Performance
RJA = (TJ – TA)/P => P = (TJ – TA)/ RJA Use 4 layer Substrate
2.5
to create TE-PBGA
2
Power (watts) at (Tj-Ta)=35 C
1.5
0.5
0
10 12 15 27 35
Body Size (mm)
Assumptions: Multilayer application, lots of board area, only low power devices nearby,
used junction to ambient thermal resistance on 2s2p test board in natural convection.
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Factors in thermal performance:
• Die Size
• Substrate Design
• Balls under die – Don’t depopulate under die
160 15x15 MAP PBGA 50 °C/W at 36 mm2 die to 88 °C/W for 16 mm2 Die
• Vias under die – vias are cheap, use more than 10

• Metal under the die and bottom side spreader
• Conductive vs. non-conductive die attach (thickness)
• Solder Mask Thickness – thin is better
• Substrate Thickness – thin is better
• Die thickness for GaAs die
Don’t ask for this design:

No connection from flag
to balls
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Sample of MAP PBGA Designs
60
60
50
Theta-JMA (2s2p) C/W
50
Theta-JMA (2s2p) C/W

40 40
30 30
20 20
10 10
0 0
5 10 15 20 2 4 6 8 10
Body Size (length, mm) Die Size (length, mm)
45
40
35
Theta-JB (C/W)
Strong correlation of 30
25
thermal performance with 20

15
die size 10
5
0
2 4 6 8 10
Die Size (length, mm)
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Stacked Die
Die_1 Power
Die Attach
Die_2 Power
C
Die Attach
Package
Three Die
Environment Stack, Hi power
die on top
• Highest power die should be on bottom of stack
• Die attach thermal resistance is 1 to 10 °C/W determined by die size and material
• Choose a ball map which allows ground balls under die with vias through the
substrate
• If the DRAM has a maximum temperature rating of 85 °C, it is not a good idea to
stack it with other power dissipating components if you have to meet a 85 °C board
temperature. Case temperature of 85 °C would be ok.
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Package on Package Thermal Test Vehicle
• 604 15x15 MAP PBGA with 7.77x7.77 test die
• Memory (160 15x15 MAP) with 7.77x7.77 test die and 10.4x8.1 spacer die
Top Die
Spacer Die
Bottom Die
Thermal Test Board Test Board Vias
Junction to Board Thermal Simulation, 0.4 W in bottom die, 0.1 W in top die
Air between packages and between package and board was simulated but not shown
for this illustration
Advantages: Standard memory pinouts, memory die is a little cooler
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Heat Sinks Issues
25 TM
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Use Heat Sinks Above 3 W
TA
Heat Sink RSA
Sink to ambient
TS
Interface RCS
Case to sink
TC
Package RJC Theta-JC Determines

Junction to case
TJ Whether Heat Sink Useful
TJ = TA + (RJC + RCS + RSA)*P
Simple View of Heat Sinks assuming all the heat flows to the heat sink
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Theta-JC Values Heat Sinks
PBGA about 5 to 10 C/W 20 to 40%
improvement possible
TBGA about 2 C/W dissipate 10 W or more

with air flow
FC exposed die < .1 C/W dissipate 70 W instead

of 1 W.
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Maximum Power in Natural Convection
Variables
• Package Internal Resistance – Theta-JB and Theta-JC depend on die size as
well as package size and construction
• Temperature Range TJmax – Ta available for cooling, Ta is local ambient to
device
• Radiation may be more than half the heat flow for natural convection
 Emissivity of surfaces
 Temperature of surfaces
• Air Flow –
 Space for natural convection
 Forced Convection
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PBGA, TEPBGA, TEPBGA2
• Theta-JC and Theta-JB are given for customer to create two resistor model
• Thermal performance for given package size and construction changes with
die size.
• For this example, Theta-JC changed 30%.
• Models for Computational Fluid Dynamics (CFD) Simulations are better
10
Thermal Resistance (C/W)

9 Theta-JB
8
7
Die 6
5 Theta-JC
4
3
416 27x27 TEPBGA2 2
(with the internal spreader) 1
0
40 50 60 70
Die Area (mm^2)
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PBGA, TEPBGA, and TEPBGA2
Hand calculation of the heat sink
performance will give wrong
answer 100
Natural Convection
80
• Model must consider heat flow path though
% Heat Flow
60 Heat Sink %
the heat sink and the heat flow to the 40 Board %
printed circuit board. 20
0
• Heat flow to the board can be 20% to 75% of 30x30x9.4 35x31x23 43x41x16.5 53x53x25
Heat Sink Size (mm)
the total heat flow.
Simulation for 516 27x27 TEPBGA2
Recommend attachment of the Mounted on 100x100 mm 2s2p board
with two solid 0.030 mm thick planes
heat sink to the board

• Clip to substrate not recommended.
Bending force by clip on substrate edge
can cause early solder joint failures.
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Heat Sink Choices
Specified heat sinks are not provided because of the range
of applications and environments that customers use.
Reference heat sinks are sometimes provided to help
customers estimate the heat sink requirements.
Example
• Heat sink was designed for CompactPCI
board spacing
• Spring clip to plastic frame mounted to
board
• Force on heat sink centered over die
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FC-PBGA (laminate substrate) with no lid or “die sized lid”
Recommend clip heat sink to board

• Force centered over die (45 newtons maximum)
• Manage warpage of printed circuit board if necessary (Backing Plate)
Glue attachment of heat sink is not recommended (limited area, device
not qualified with those forces, die-sized lid uses silicone adhesive with
limited peel strength)
Clip to substrate not recommended. Bending force by clip on substrate
edge can cause early solder joint failures.
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FC-PBGA with Full Footed Lid
Recommend clip heat sink to board

• Force: 45 newtons maximum
• Manage warpage of printed circuit board if necessary (Backing Plate)
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TBGA (Cavity Down, heat spreader, wire bond package)
• Thermal interface material must accommodate the fact that the

heat spreader (top of package) is not absolutely flat. Recommend
considering 0.1 to 0.15 mm variation of interface thickness.
• If heat sink adhesive is used, adhesive must stick to epoxy
painted surface.
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Thermal Data Usage
• Package Selection
• Determination of test (characterization) temperature requirements
• Calculation of HTOL (High Temperature Operating Life) acceleration
factors from junction temperature
• Customer design team needs the data (expects it to be available in
datasheet)
• Customer reliability team needs thermal data to validate customer’s
design
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BACK UP
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How fast does it heat?
50
45 1.7 W
40
Temperature Rise (C)
35
30
25 0.9 W
20
15
0.66 W
10
5
0
1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02
Time (sec)
Calculation of the rate that the die heats in a 604 15x15 POP package. Power is applied to
the center 1/3 of the die area. There is no memory package.
The package is assumed to be in natural convection on a 100x100 mm printed circuit
board with two planes. The heating is calculated to 100 seconds. The die will reach
maximum steady state temperature in approximately 3000 seconds.
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FC-CBGA
Flip-Chip Ceramic Ball Grid Array

• Most products for network applications use HiCTE ceramic with a high
temperature coefficient of thermal expansion (12 ppm) instead of
traditional ceramic with a thermal expansion about 7 ppm. The
thermal conductivity of the HiCTE ceramic is only 2 W/m K instead of
16 W/m K of the standard ceramic.
• Recommend clip heat sink to board. Clip to substrate is acceptable
for the stiff ceramic substrate, but is not recommended because future
devices will probably have laminate substrates.
• Glue attachment of heat sink is not recommended (limited area,
device not qualified with those forces)
Note: All current Flip Chip NPI packages are laminate
substrate, FC-PBGA
38 TM
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Package Thermal

Bennett Joiner & Sriram Neelakantan

Power dissipated in the die is conducted to the top surface of the

Tj “junction” or die temperature

Electrical Resistivity Thermal Conductivity

20 orders of magnitude difference 3 orders of magnitude difference

You can’t ignore the thermal insulators

• Solder the package to the thermal test boards

• Apply power, measure the temperatures per the JEDEC specifications

Junction to Ambient Thermal Resistance (Theta-JA) on

Theta-JA (2s2p) 24 °C/W

Theta-JA using JEDEC specifications

Eight 119 14x22 mm PBGA on each side of board, 1 W each

• Customers need to verify junction temperature for components in their

Theta-JC is used to predict device

Case thermocouple placed inside cold plate

Insulation Cooling Channels

RJX = (TJ – TX)/P

TJ = TB + P*RJB Sealed enclosures, board temperature dominates

TJ = TA + P*(RJC + Rinterface + RSA) With heat sink, include thermal resistance

Validation of design using case temperature or determination of junction

Larger Flag and Die has better thermal performance.

• Vias under die – vias are cheap, use more than 10

Don’t ask for this design:

Theta-JMA (2s2p) C/W

thermal performance with 20

Thermal Test Board Test Board Vias

Package RJC Theta-JC Determines

TJ = TA + (RJC + RCS + RSA)*P

TBGA about 2 C/W dissipate 10 W or more

FC exposed die < .1 C/W dissipate 70 W instead

Thermal Resistance (C/W)

printed circuit board. 20

heat sink to the board

Recommend clip heat sink to board

Recommend clip heat sink to board

• Thermal interface material must accommodate the fact that the

Flip-Chip Ceramic Ball Grid Array

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