Noname manuscript No.
(will be inserted by the editor)
A Chaos-based Complex Micro-Instruction Set for Mitigating
Instruction Reverse Engineering
Md Sakib Hasan∗1 · Md Badruddoja Majumder1 · Aysha S. Shanta1 ·
Garrett S. Rose1
Received: date / Accepted: date
Abstract Chaos computing provides a large number of
functions from a single hardware. Large scale reconfig-
urability can be achieved flexibly by tuning only a few
parameters from a chaos based computing system. Im-
plementation of reconfigurable complex functions from
a single chaos circuit can alleviate area and power con-
cerns due to decreasing technology nodes. It is possible
to make a multi-input multi-output complex instruc-
tion set using the chaos generated functionalities where
operations are more uniform than conventional imple-
mentations. Lack of uniformity in implementation of
instructions in traditional computing system provides
opportunity for attackers to reverse engineer based on
side channel power analysis. In this paper, it is pro-
posed that chaos based implementation of a complex
instruction set is immune to classification based reverse
engineering attack. Cross obfuscation and self obfusca-
tion schemes are proposed in this work which leverage
reconfigurability of chaotic system for obfuscating the
power profile of the instruction set and it has been made
immune to reverse engineering attacks. The design uti-
lizes 3-input multi-output instructions by using a sin-
gle chaotic iterative map. We analyzed the immunity
of this design against classification based reverse engi-
neering attack for six different classification algorithms
with five dimensionality reduction techniques.
∗
Md Sakib Hasan
343 Min H. Kao Building
1520 Middle Drive
Knoxville, TN 37996-2250 USA
Tel.: +1-865-974-0229
E-mail: mhasan4@utk.edu
1
Department of Electrical Engineering and Computer Sci-
ence, The University of Tennessee, Knoxville, TN, USA E-
mail: {mmajumde,ashanta1,garose}@utk.edu
Keywords chaos computing, side channel, power
profile, obfuscation, instruction classification, hardware
security
1 Introduction
Since Lorenz’s discovery of chaotic motion on a strange
attractor in 1963 [27], chaos has attracted a lot of atten-
tion in areas such as chemistry, physics, biology, ecology
and financial systems [35]. Many natural and engineer-
ing systems have been modeled using dynamical sys-
tems [10, 26]. Over the years, non-linear dynamics in
chaotic systems has become an active field of research
due to advancements in chaotic neural networks and
chaos communications [1, 16, 25]. Applications of chaos
are significant in the field of engineering, especially in
cryptography, secure communication, plasma technolo-
gies and lasers [2, 13, 18].
Computing based on chaotic progression of state in
non-linear circuits, also known as chaos computing, has
been an exciting research area. Researchers have worked
on various aspects of chaos computing exploring recon-
figurability, flexibility and security in the non-linear sys-
tems [5, 7, 22]. Chaos based computation can facilitate
a single hardware to perform a large number of op-
erations by changing a small set of parameters in the
circuit topology. A single operation can be performed
in many ways by changing the threshold voltage, con-
trol bits, initial state, iteration number and bifurcation
parameter.
Researchers have proposed different chaos based im-
plementations of basic logic gates. Higher input func-
tions are possible to implement using chaos in addition
to 2-input basic logic functions [21]. Chaos computing
demonstrates promise in the field of secure and confi-
2 Md Sakib Hasan∗1 et al.
dential computing. It has been proposed as a means of
obfuscating power profile and hence mitigating power
analysis based side channel attack [28, 31].
In this work, a new chaos based design for imple-
menting a complex micro-instruction set comprising 3-
input multi-output (1−8) digital operation is proposed.
Since each instruction in traditional instruction set con-
tains distinguishing power signatures, they can be clas-
sified with high accuracy using standard classification
algorithms. Training power signatures are collected from
a reference computing machine for performing instruc-
tion reverse engineering in different machines. This work
shows that by leveraging different configurations of chaos
operation, each machine can perform instructions with
unique power profile. Moreover, an uniform implemen-
tation of the instruction set is also proposed where each
operation exhibits very similar power signatures and
can not be distinguished. It has been demonstrated that
both of these methods can help mitigate side channel
reverse engineering attacks performed using different
classification and dimension reduction algorithms.
The paper is organized as follows. Section 2 provides
background and necessary details about chaos comput-
ing and its application to perform reconfigurable and
flexible logic operations. Design and working principles
of a chaotic map circuit is described in Section 3. Sec-
tion 4 describes the design of complex micro-instruction
set. Section 5 goes through different classification algo-
rithms and dimensionality reduction techniques used to
reverse engineer instruction using side channel power
signatures. Classification results of CMOS based tradi-
tional implementation of the instruction set is provided
in Section 6. Both of the proposed defense models along
with their corresponding results are explained in Sec-
tion 7 and 8, respectively. Section 9 discusses about lim-
itations and possible future directions for this research
work. Finally, the paper is concluded in Section 10.
2 Chaos Computing Preliminaries
Despite existing proof of tremendous success of digital
systems, there are areas where the systems do not meet
the demands and specifications of current applications.
Traditional computer systems are built from Boolean
circuits which contain switches (transistors). The tran-
sistors open and close based on the the incoming input
applied to the gates of the transistors. Different circuit
topologies need to be designed in CMOS technology to
implement different logic functions [21]. Hence, digital
systems require millions of transistors which may cause
problems such as excessive power consumption and heat
production in a chip. As a solution to this problem, non-
linear dynamical systems are studied which can gener-
ate multiple logic functions using the same design.
In chaotic systems, the non-linear dynamics of CMOS
circuits and their intrinsic computational capability is
being explored. The circuit maps the initial state of
the circuit to future states. The dynamical system can
evolve in continuous time or in discrete time. Continu-
ous time chaotic systems have high complexity and low
efficiency compared to discrete time chaotic systems.
In order to design a discrete time chaotic map, the out-
put of the map is connected to the input of the circuit
creating a feedback path [23].
A disadvantage of using chaotic logic gate is that
they require more hardware compared to standard CMOS
logic gates. In order to overcome this limitation, each
chaotic gate should be able to generate increased func-
tionality. The number of functions that a single chaotic
circuit can implement increases exponentially with the
number of iterations. The functions generated by the
chaotic circuit can be dynamically chosen to implement
different logic functions in each clock cycle. The chaotic
system is able to exhibit different behaviors by changing
the initial state of the circuit or by changing the circuit
parameters. In practice, all the functions may not be
accessible or usable due to noise or instability [22].
Chua’s circuit is one of the most popular chaotic
oscillators which uses an element called “Chua diode”
(piecewise-linear) to implement the non-linearity of dy-
namical systems. Several approaches such as “cubic-
like” non-linearity or cubic non-linearity have been dis-
covered to replace the Chua diode [33]. Previously, arith-
metic operations were performed using arrays of chaotic
elements. Chaotic systems are now used to implement
logic gates which are capable of implementing AB, A +
B, AB, A + B, A ⊕ B, A ⊕ B, ON and OFF. The one-
dimensional system is able to implement only eight of
the 16 possible functions because the initial state is a
function of the sum of the inputs [7]. This problem can
be resolved by assigning each of the inputs to its own
state variable.
Chaotic circuits are made reconfigurable and flexi-
ble by changing parameters in the circuit topology. In
1998, Sinha et al. proposed that chaotic systems can
be used to build computers [32]. Murali et al. used a
thresholding mechanism to implement a NOR gate with
continuous-time chaotic system [30]. Rizk et al. also ap-
plied a threshold technique to Chua’s circuit in order
to obtain all the functions such as AND, OR, NAND,
NOR and NOT. Chua’s circuit has been used to de-
sign a flipflop which is a building block for memory
devices [4]. Rose constructed a chaos based arithmetic
logic unit where different functions are selected by al-
tering the control input and iteration number [31]. Bohl
A Chaos-based Complex Micro-Instruction Set for Mitigating Instruction Reverse Engineering
Fig. 1: Chaos circuit for implementing 3-input logic op-
erations.
et al. proposed the use of chaos in the field of security
for logic obfuscation and mitigation of power analysis
based side channel attack. The chaotic power profile of
the logic computations helps to eliminate side channel
attacks [3]. Chaos computing is still a nascent field with
plenty of opportunities for innovative ideas and exciting
research. This work proposes the use of 3-input multi-
output logic gates in order to mitigate power analysis
based side channel attack on micro-instructions by ap-
plying various classification algorithms.
3 Chaotic Map Circuit
If a non-linear function, f transforms any point xn from
a closed interval l = [a, b] into some point xn+1 in the
same interval i.e. f : l → l, then
xn+1 = f (xn )
is called a discrete map of the interval l for n = 1, 2, ..., n.
A one-dimensional non-linear map is the easiest way to
generate chaotic signals in discrete time. Generally map
circuits are designed to imitate one of the widely known
chaos maps such as a logistic map or a tent map. How-
ever, any differentiable unimodal function can portray
the same qualitative behavior. Feigenbaum has studied
this universality of iterated map’s route from periodic-
ity towards chaos in great detail [11, 12]. Chaos maps
are also achievable with V-shaped functions similar to
an inverted tent map where the branches are defined by
different equations.
In this paper, a three transistor map circuit shown
in Fig. 1 is used to generate chaotic signals in discrete
time. This paper uses a scaled down implementation of
a well-studied chaotic map circuit topology [9,20,22] in
65 nm process. The map characteristics can be altered
by changing the bias voltage, Vc which is also the bi-
furcation parameter of the map circuit. The transistors
in the map circuit were sized as follows: top n − M OS
= 1.2 µm/60 nm, bottom n − M OS = 0.12 µm/60 nm
3
and p − M OS = 0.12 µm/60 nm. The transistor sizes
are chosen after experimenting with several different ge-
ometries and comparing their performance in regards to
area, power, delay and the width of chaotic region in
the bifurcation diagram. The DC characteristics of the
map circuit for different values of Vc is shown in Fig.
2. As can be seen from the figure, the output is a V-
shaped curve revealing the inherent properties of the
map circuit which is desired for generating chaos.
The bifurcation diagram in Fig. 3 displays a thou-
sand iterations of the steady state output values against
the bifurcation parameter, Vc . For values of Vc < 520
mV , the output has a stable period of 2, i.e. it oscillates
between two values. At Vc = 520 mV , the first bifur-
cation occurs resulting in period doubling. The next
period doubling occurs at 637 mV resulting in a sta-
ble orbit of 8 cycles. The rate of period doubling keeps
on increasing progressively faster and eventually as Vc
approaches 642 mV , the circuit enters into chaotic re-
gion and starts oscillating aperiodically. Three distinct
chaotic regions are clearly visible in this figure with
in-between periodic windows. The evolution of output
voltage for four values of bifurcation parameter is shown
in Fig. 4. Here, the number of iteration, n is shown in
x − axis and corresponding output voltage, vn is shown
in y − axis for 60 iterations. The iterated outputs are
discrete points indicated by red dots which are joined
by straight lines to make the sequence clearly visible.
In order to implement a chaos generator, two sample-
and-hold (S/H) circuits are required along with the map
circuit as shown in Fig. 1. A two phase clock is used
where the output of the map circuit is sampled onto ca-
pacitor, C1 in the first phase, φ1 . In the second phase,
φ2 , the output is transferred to the second capacitor, C2
where it is held at the input of the map circuit for the
next iteration [9]. A 9-bit digital-to-analog converter
(DAC) is used to convert the binary input signal made
of 3 data (D) bits and 6 control (C) bits into analog
input of the map. After a certain number of iterations
(φs ), sampled output is compared against a threshold
voltage, δ using a comparator and a binary output, O
is generated. In addition to Vc and C, the functionality
also depends on the choice of φs and δ.
The worst-case delay occurs when the input goes
from V DD (1.2 V ) to GN D (0 V ). It can be seen in the
semi-logarithmic plot in Fig. 5 that the worst-case delay
increases very fast as the value of Vc increases. So, it is
prudent not to use the third chaotic region above Vc =
890 mV , where the delay is very high. Implementing
logical functions requires several iterations so the design
has been constrained within the first two chaotic regions
where the delay is relatively small. The feedback circuit
along with the DAC and the comparator used in this
4 Md Sakib Hasan∗1 et al.

Table 1: Evolution of chaotic output with iterations (VC

= 690 mV , C = (111010)2 = 58, δ = 1.03 V , φs = 5).
xn (V) y (V)
i=1 i=2 i=3 i=4 i=5
0.136(000) 1.2 0.52 0.36 1.06 0.43
0.287(001) 1.19 0.51 0.39 0.91 0.35
0.437(010) 0.72 0.27 1.19 0.51 0.38
0.587(011) 0.24 1.2 0.52 0.37 1.02
0.737(100) 0.27 1.19 0.51 0.38 0.96
0.888(101) 0.34 1.13 0.47 0.56 0.25
1.038(110) 0.42 0.79 0.3 1.18 0.51
1.188(111) 0.51 0.39 0.93 0.36 1.04

Fig. 4: Evolution through successive iterations for dif-

ferent values of bifurcation parameter.

Fig. 5: Worst-case delay changes with bifurcation pa-

Fig. 2: Transfer curve of map circuit. rameter, Vc .

Fig. 3: Bifurcation diagram of the chaotic oscillator.

work is modeled in Verilog-A and integrated with the 3-
transistor non-linear circuit using Cadence Spectre for
simulation.
4 Complex Micro-Instruction Set Design
The input-output data for different values of Vc was
obtained from Cadence Spectre. A MATLAB code was
developed to explore the large design space spanned by
four control parameters and was used to set the con-
figuration for all the instructions. In order to limit the
delay within reasonable time, the analysis has been con-
strained within 21 iterations. Multi-output functions
Fig. 6: Schematic for implementation of a chaos-based
full adder circuit.
like ADD, SUB, decoder and encoder require a com-
mon pair of (Vc , C) for all the output functions. For
example, in order to design a decoder, we need 8 pos-
sible 3-input functions with the same Vc and C along
with eight different values of δ and φs . As a result, it is
possible to use a single chaotic map circuit to get mul-
tiple functionality. A schematic diagram of 1-bit full
adder and 3 × 8 decoder is shown in Fig. 6 and Fig. 7
respectively. An example of evolution of analog values
for different possible inputs of a 3-input AND configu-
ration is shown in Table 1.
A Chaos-based Complex Micro-Instruction Set for Mitigating Instruction Reverse Engineering
Fig. 7: Schematic for implementation of 8 Boolean func-
tions of a 3 × 8 decoder using a single chaos circuit.
5 Adversarial Model
It is assumed that an attacker can gather a set of la-
beled power traces and this information can be used
to classify unknown instructions. The attack model is
a supervised learning problem using multi-class (11 in
this work) classification. This work tries to tackle the
problem of power analysis based side channel attack us-
ing several methods. The general procedure is described
in the following subsections.
5.1 Data Collection
At first, 2000 observations were collected for each of
the 11 instructions namely, AND, OR, XOR, NAND,
NOR, XNOR, ADD, SUB, MUX, DEC (decoder) and
ENC (encoder). ADD and SUB have 3 inputs and 2 out-
puts, DEC has 3 inputs and 8 outputs and ENC has 3
inputs and 2 outputs. The remaining seven instructions
have 3 inputs and 1 output. The collected data has been
partitioned into training and testing sets. 1600 (80%)
observations have been used to train the classifier and
then the classifier is used to predict the label of remain-
ing 400 (20%) test data. This partitioning of data has
been used in all the classification results shown in this
paper.
5
Fig. 8: Percentage of total variance in the first few prin-
cipal components.
Fig. 9: Sum of difference of means among the instruc-
tion sets’ power profiles from the training data set used
for cross-obfuscation classification.
5.2 Dimensionality Reduction
As the amount of data gathered for different classes
grow, the curse of dimensionality makes it very dif-
ficult to work with the entire feature space. Dimen-
sionality reduction techniques are feature selection al-
gorithms used to compress data while preserving the
variance of the original data as much as possible. In lit-
erature, several dimensionality reduction methods have
been proposed. In this paper, we have implemented five
techniques including two of the most common tech-
niques namely, Principal Components Analysis (PCA)
and Fishers Linear Discriminant Analysis (FLDA). In
addition, we have implemented three other methods,
Sum of Difference of Means (SDM), Means-PCA and
Means-Variance (MV).
5.2.1 Principal Components Analysis (PCA)
Principal Components Analysis (PCA) tries to reduce
the dimensionality of the data while maximizing its
variance to the full extent. This is achieved by pro-
jecting the data orthogonally onto a lower dimensional
subspace. This lower dimensional subspace can be de-
6 Md Sakib Hasan∗1 et al.
fined by a D-dimensional unit vector, u1 . The projec-
tion of each observation, xn , onto this subspace is given
by u1 T · xn . If all the observations are stacked up into
a matrix, the projection of each row of the matrix can
be represented as UT X, where U is a matrix consisting
of eigenvectors of the covariance matrix, σ. The projec-
tion of the observations into a D-dimensional subspace
that maximizes the projected variance is given by D
eigenvectors, u1 , ..., ud with the D largest eigenvalues
λ1 , ..., λd [34]. The effectiveness of PCA depends on the
number of reduced dimensions and on the nature of the
analyzed data. In this work, first few principal compo-
nents contain most of the variance of the features as
shown in Fig. 8. While using PCA, the dimensionality
of the problem has been reduced to first 30 principal
components for all cases since most of the information
is retained in the reduced data.
5.2.2 Means-PCA
PCA maximizes the overall variance of class observa-
tions but does not take the variance between classes
into account. A reasonable choice is to maximize the
variance of inter-class observations since moving the
class means apart may result in a higher classification
rate. Here the class means are considered as instances
and the projection coefficients are computed using the
techniques discussed in Section 5.2.1. These projection
coefficients are then used to transform the observations.
In this method, the number of reduced dimensions are
K − 1, where K = number of classes.
5.2.3 Sum of Difference of Means (SDM)
In the past, differential power has been used to correlate
information leakage of a device with its power consump-
tion [24]. In this work, this method has been used to re-
duce the dimensionality of the instruction-level traces.
The method of computing the new dimension, D, from
the original dimension, L is as follows. First the abso-
lute difference between each pair of mean vector is cal-
culated. Then, these differences are summed and finally,
first D points among the highest peaks are chosen. The
results of the training data set used in cross-obfuscation
classification is shown in Fig. 9. The first 30 highest
peaks are chosen for all cases so that the results are
consistent with PCA.
5.2.4 Means-Variance(MV)
Means-variance is another method of dimensionality re-
duction motivated by the same underlying principle as
SDM described in Section 5.2.3. For a dimensionality
reduction technique geared towards multi-class classifi-
cation, a reasonable choice is to take the feature points
accounting for the maximum variance of the original
data across the different classes. In order to identify
these points the mean of each class, µk is needed, where
1 ≤ k ≤ K. If the mean values are put into a matrix
(with k-th row being the mean of the k-th class), a
K × L matrix will be created, where L is the dimen-
sion of the original data. The variance of each column
is the inter-class variance of each feature point. Finally,
the dimension is reduced by taking the first D columns
with the highest variance.
5.2.5 Fishers Linear Discriminant Analysis (FLDA)
Fishers Linear Discriminant Analysis (FLDA) is an ap-
proach used in pattern recognition to find a linear com-
bination of features which characterizes two or more
class observations [8,14]. The resulting combination may
be used for dimensionality reduction before classifica-
tion. However, instead of maximizing the variance of the
intra-class data like PCA, information regarding the co-
variance of different classes is taken into consideration.
These are the between-class and within-class covariance
matrices. If N number of L-dimensional observations
for each class, C are considered, then the within-class
covariance, σW and the between-class covariance, σB
are computed as:
k
X
σW = Ni σ i (1)
i=1
and
k
X
σB = (µi − µ)(µi − µ)T (2)
i=1
where Ni , k, µ, σi and µi are the number of observa-
tions, the number of classes, global mean, the covari-
ance and the mean of the power trace for each class Ci ,
respectively. A D-dimensional unit vector u1 is consid-
ered onto which the data is projected. This time the ob-
jective is to maximize both the projected between-class
and the projected within-class covariance. It has been
−1
shown in [8] that u1 has to be the eigenvector of σW σB
for maximization of projections. The D-dimensional sub-
space is created by the first D eigenvectors u1 , . . . , uD
−1
of σW σB with the largest eigenvalues λ1 , . . . , λD . The
maximum value of D can be K − 1 which is used in this
work.
A Chaos-based Complex Micro-Instruction Set for Mitigating Instruction Reverse Engineering
5.3 Instruction Classification
After the templates are created using dimensionality re-
duction techniques, the next step is to use a classifica-
tion method to classify the test data and determine its
accuracy. In a supervised learning setting, the training
data is an ordered pair (x, y) where x is an instance and
y is its class label. The goal of the algorithm is to assign
a class for a given instance x. Many different classifiers
are used in machine-learning problems and their rela-
tive superiority depends on the speed, implementation
cost, accuracy and most importantly, the nature of the
problem. In this subsection, we briefly discuss several
classification algorithms used in this work.
5.3.1 k-Nearest Neighbors Algorithm (kNN)
The kNN is a non-parametric lazy supervised learn-
ing algorithm. The algorithm is called non-parametric
because it does not make assumptions about the data
and data generalization is not needed. In this algorithm,
the training means storing the training data along with
their class labels. During classification, the classifier
computes the distance between the instance, x and all
training instances, x ∈ X. It then keeps the k closest
training instances, where k ≥ 1. The class that is most
common among the instances is assigned to x. In kNN
there are two major design choices; (a) the value of k
and (b) the distance function. The most common dis-
tance function used in kNN is the Euclidean distance
function [36] [6]. The Euclidean distance, deuc , between
two instances x1 and x2 is computed as:
v
u L
1 2
uX
deuc (x , x ) =t (x1i − x2i )2 ,
i=1
where x1 and x2 have L features and x1i and x2i are the
i-th sample points.
We have used two more distance functions namely,
Correlation and Cosine learning distance functions. Cor-
relation distance is measured as:
PL 1 2 T
( L
P
x1 )( L
P 2
i=1 (x .(x ) ) i=1 x )
1 2 L − i=1 L 2
dcor (x , x ) =
σx1 σx2
The cosine distance between two points x1 and x2
can be defined as:
x1 .(x2 )T
dcos (x1 , x2 ) = qP . (5)
L 1 2
PL 2 2
i=1 (xi ) i=1 (xi )
7
5.3.2 Support Vector Machine (SVM)
A support vector machine or SVM [19] is a supervised
learning algorithm primarily used for classification. Given
a set of training examples, each marked as belonging to
one or the other of two categories, an SVM training al-
gorithm builds a model that assigns new examples to
the appropriate category making it a non-probabilistic
binary classifier. An SVM model is a representation of
examples as points in space mapped in such a way that
the examples of separate categories are divided by a
wide gap. New examples are mapped into the same
space and predicted to belong to a category depend-
ing on which side of the gap they fall into. SVM can be
used as a non-linear classifier by using suitable kernel
functions e.g. Gaussian radial basis function. The stan-
dard SVM supports only binary classification, but it
can be extended by transforming multi-class classifica-
tion to multiple binary classification problems [17]. De-
pending on the application, different number of binary
classifiers such as ‘onevsone,’ ‘onevsall,’ ‘binary com-
plete,’ and ‘denser random’ are used in practice. In this
work, we have reported the results for ‘onevsall’ and
‘onevsone’ techniques and the results also show a K-
way multiclass problem, ‘onevsall’ and ‘onevsone’ train
k and k(k−1) binary classifiers, respectively.
2
5.3.3 Decision Tree(DT)
A decision/classification tree is a simple representation
for classifying examples. Each internal node of the tree
is labeled with an input feature. The arcs coming from a
node are labeled with each of the possible values of the
output feature or the arc leads to a subordinate decision
node on a different input feature. Each leaf of the tree is
(3) labeled with a class or a probability distribution of the
classes. In order to predict a response, one has to follow
the decisions in the tree from the root node down to a
leaf node which contains the results of classification.
In this work we have used decision tree classifier using
‘onevsall’ and ‘onevsone’ techniques.
5.3.4 Discriminant Analysis (DA)
Discriminant analysis create a linear combination of
features that characterizes or separates two or more
. (4)
classes. It is often used for dimensionality reduction
as described in section 5.2.5. For two classes, DA ap-
proaches the problem by assuming that the conditional
probability density functions p(x|y = 0) and p(x|y = 1)
are both normally distributed with mean and covari-
ance parameters µ0 , Σ0 and µ1 , Σ1 , respectively. In
this work, we have used Linear Discriminant Analy-
sis based on the assumption of homoscedasticity, i.e.
8 Md Sakib Hasan∗1 et al.
Σ0 = Σ1 and that the covariances have full rank. In
this paper, Linear Discriminant Analysis leverages the
‘onevsall’ and ‘onevsone’ techniques.
5.3.5 Naive Bayes(NB)
Naive Bayes is a conditional probability model based
on Bayes’ theorem with additional simplifying assump-
tions. Given a problem instance to be classified, repre-
sented by a vector x = (x1 , . . . , xn ) which has n features
(independent variables), it assigns to the instance prob-
abilities, p(Ck |x1 , . . . , xn ) for each of k possible out-
comes or classes and label the data as belonging to the
class with the highest probability. Combining Bayes’
theorem and very simplistic conditional independence
assumption, theQproblem boils down to determining the
n
value of p(Ck ) i=1 p(xi |Ck ) for each class and then
choosing the class with maximum value. In this work,
the prior probability is estimated from the training set
and features are assumed to follow a Gaussian distri-
bution.
5.3.6 Multivariate Gaussian Probability Density
Function
Given µk and σk of each instruction, classification is
performed as follows. Let W be the power consumption
waveform captured at runtime and assuming that its
samples are drawn from a Multivariate Gaussian Nor-
mal Distribution model [15]. The noise introduced into
the power waveform, W, is extracted by subtracting the
mean value from the waveform as in
nk = (W[1] − µk [1]), (W[2] − µk [2]), .., (W[p] − µk [p])
(6)
where, µk is the mean of instruction Ik and p is the
number of selected features after the original dimen-
sionality is reduced. The probability of observing the
noise, nk in the device’s power trace is then computed
as:
1 1
N (nk , (µk , σk )) = exp(− (nk )σk−1 (nk )T ). (7)
(2π)D/2 2 input multi-output operations, each implemented with
The instruction with the template that generates
the highest probability of observing noise, nk is classi-
fied as the correct instruction.
6 CMOS Classification
Traditional CMOS based implementation of the instruc-
tion set is vulnerable to power based classification at-
tack. Each instruction exhibits distinguishable power
signatures. Therefore, instructions can be classified us-
ing a sufficient amount of power data by applying dif-
ferent random operands. As demonstrated in previous
work, instructions implemented on a traditional CMOS
based processor can be classified with a high accuracy
[28, 29].
This work shows the classification of CMOS based
traditional implementation of the instruction set which
has been performed using all the classification algo-
rithms described earlier. For each classification algo-
rithm, several dimension reduction techniques are used.
The data has also been analyzed with no reduction tech-
nique performed on it. Classification results for the dis-
cussed techniques are tabulated in Table 2. The best
classification accuracy was achieved for 1-NN with co-
sine distance after using all the sample points of the
dataset. A confusion matrix showing detailed result for
each instruction of this classifier is shown in Table 3.
The overall accuracy is 94.2% which is very close to the
ideal value of 100%.
7 Cross Obfuscation
As proven in Section 6, traditional implementation of
instructions in a processor can be accurately profiled
based on its power trace. Instruction power profiles can
be successfully used to reverse engineer instructions on
any other machine using classification algorithms de-
scribed earlier. However, with chaos-based computing,
functionality can be chosen from a large space where a
single function can be implemented using different con-
figurations, each with a unique power signature. Conse-
quently, profiling instructions based on the power sig-
natures from a reference machine is not sufficient to
classify instructions in other machines. This idea was
first proposed in [28], where seven two-input ALU in-
structions were implemented using three basic chaotic
logic gates, AND, OR and XOR. A sequence of Vc along
with variable number of iterations φs was used with no
control bit and fixed threshold.
In this work, the same technique has been extended
for preventing classification attack among eleven three-
a single chaos-based logic gate. The control operation
has been simplified by using a single Vc (chosen inside
the chaotic region in Fig. 3) for a particular operation
with variable threshold, δ and 6-bit control input, C for
expanding the design space.
Five different set of configurations are chosen in the
chaos circuit for getting all the instructions in the in-
struction set. As already described, 4 different parame-
ters of the chaos circuit comprise the configuration for
each operation. The parameters are bias voltage, Vc ,
A Chaos-based Complex Micro-Instruction Set for Mitigating Instruction Reverse Engineering 9

Table 2: Classification accuracy among instructions using different classifiers and dimensionality reduction algo-
rithms for CMOS implementation.

Category Sub-category Dimensionality Reduction Algorithm

No Reduction PCA PCAmean SDM MV FLDA
KNN 1-NN(euc) 92.27 92.09 91.11 80.5 78.72 86.36
3-NN(euc) 91.84 91.80 90.84 79.2 77.96 87.04
5-NN(euc) 91.44 91.45 90.57 79.01 78.23 87.35
1-NN(corr) 85.31 93.84 92.05 20.5 19.32 85.47
3-NN(corr) 93.35 93.39 91.9 54.33 52.01 86.4
5-NN(corr) 93.07 92.94 91.39 70.24 67.69 86.05
1-NN(cos) 94.2 93.89 92.23 79.82 76.98 86.05
3-NN(cos) 93.57 93.27 91.89 79.29 76.89 87.02
5-NN(cos) 93.17 92.9 91.44 78.98 76.79 86.77
SVM onevsall 82.7 80.66 73.5 58.3 57 82.47
allpairs 90.55 89.14 84.23 78.23 74.61 85.86
DT onevsall 88.61 86.55 85.98 75.2 75.31 83.73
allpairs 91.84 89.91 88.82 77.14 77.52 85.16
LDA onevsall 78.86 70.95 66 65.34 63.57 78.93
allpairs 93.95 92.23 83.55 81.91 81.1 81.73
NB onevsall 43.59 69.93 77.61 52.27 54 82.52
allpairs 63.95 78.02 78.39 52.52 53.98 82.07
MVG N/A 71.22 70.27 94.13 91.61 91.11 87.16

Table 3: Confusion matrix of classification accuracy for different instructions in CMOS implementation. Rows and
columns represent the test instruction and percentage of their matched class respectively.

Instruction Matched Class (%)

AND OR XOR NAND NOR XNOR ADD SUB MUX DEC ENC
AND 94.75 1.75 0.25 2.5 0 0 0 0 0 0 0.75
OR 1.25 82.75 0 7.75 1.25 0 0 0 1 1.25 4.75
XOR 0.25 0 95.5 0 0 4.25 0 0 0 0 0
NAND 1.75 5.5 0 91.5 0.5 0 0 0 0.5 0 0.25
NOR 0 0 0 0 96.2 0 0 0 0.25 0 3.5
XNOR 0 0.25 2 0 0 97.25 0 0 0 0.25 0.25
ADD 0 0 0.75 0 0 0 94 5.25 0 0 0
SUB 0 0 0 0 0 0 1.5 98.25 0.25 0 0
MUX 0 0.25 0 0 0 0 0 0 98.25 0 1.5
DEC 0 0 0 0 0 0 0 0 0.25 99.75 0
ENC 0 0.75 0 1 6.75 0 0 0 2 1.5 88

Table 4: Different configurations for instruction set used in cross-obfuscation

Operation Configurations
Config.1 Config.2 Config.3 Config.4 Config.5
Vc C δ φs Vc C δ φs Vc C δ φs Vc C δ φs Vc C δ φs
AND 0.69 58 1.02 5 0.74 63 1.17 3 0.62 0 0.69 4 0.69 58 1.02 9 0.72 41 1 9
OR 0.71 40 0.3 3 0.65 26 0.3 5 0.62 46 0.27 8 0.63 24 0.27 8 0.74 49 0.24 3
XOR 0.65 0.42 28 5 0.67 41 0.51 7 0.73 63 0.5 15 0.71 23 0.61 15 0.69 54 0.96 15
NAND 0.74 63 0.32 5 0.66 61 0.34 4 0.62 0 0.4 3 0.65 39 0.38 3 0.7 8 0.25 3
NOR 0.63 34 0.61 7 0.69 54 1.17 8 0.74 63 1.19 1 0.72 45 1.08 10 0.66 60 0.78 21
XNOR 0.65 28 0.69 6 0.66 63 0.81 15 0.69 63 0.82 13 0.71 23 0.42 14 0.72 62 0.51 18
ADD 0.65 28 0.42 5 0.65 40 0.51 5 0.65 45 0.42 5 0.65 26 0.42 5 0.72 58 0.52 19
SUB 0.65 28 0.69 6 0.65 48 0.77 6 0.68 41 0.51 8 0.65 51 0.6 6 0.72 57 0.83 15
MUX 0.69 62 0.55 7 0.62 38 0.63 8 0.65 55 0.94 8 0.65 53 0.86 0.65 0.74 19 1.018 11
DEC 0.64 36 1.09 15 0.68 23 0.92 10 0.71 63 1.18 8 0.67 49 0.72 6 0.68 7 0.49 21
ENC 0.71 50 0.95 10 0.67 4 0.7 5 0.62 36 0.76 2 0.65 39 0.53 2 0.74 0 1.03 6
10
Fig. 10: Classification accuracy of instructions among
different chaos configurations for best case classification
method, SVM with different dimensionality reduction
techniques.
control input, C, comparator threshold voltage, δ and
output sampling iteration, φs . The values of the pa-
rameters used in the five configurations are tabulated
in Table 4. For multi-output functions like ADD, SUB,
DEC and ENC, (δ, φs ) pair for the first output is shown.
Cadence Spectre simulator was used to generate 2000
power traces for each instruction where every trace cor-
responds to random transitions of the 4-bit operands
in the instruction. Out of the 2000 power traces, 1600
traces are used for training and the remaining 400 traces
are used for testing the classification accuracy. For 400
testing power traces of each instruction, the matched
instruction class is found for each of the traces in the
testing set. A cross classification analysis has been per-
formed among instructions from the 5 configuration
sets shown in Table 4. In each of these classification
experiment, training power samples are collected from
instructions of one configuration of chaos circuit and
test samples from another. We performed our experi-
ment with training data from configuration 1 and test
data from all configurations, 1 through 5. The training
data is used to train several classifiers with different di-
mensionality reduction techniques. Then it is used to
classify instructions from the testing data set obtained
from all configurations. This experiment emulates the
case where an attacker collects instruction power pro-
files from processor 1 and uses the profiles to classify in-
structions on another processor, say processor 2. Here,
processor 1 and processor 2 use configurations 1 and 2,
respectively, for the implementation of the instruction
set. With this methodology, we expect each instruction
Md Sakib Hasan∗1 et al.
in configuration 2 to be confused during classification
with other instructions in configuration 1.
A summary of the classification attack is tabulated
in Table 5 for different classification algorithms and di-
mensionality reduction techniques discussed in Section
5. In order to avoid clutter, we have only included ‘onev-
sone’ technique for SVM, DT, LDA and NB classifiers
and 1-NN results with cosine distance function for KNN
since these are the classifiers that produced the best re-
sults. Analyzing the results in the table, it is possible
to find the best case classification and dimensionality
reduction algorithm for each of the cross obfuscation
experiment cases.
The results clearly show that when the training and
testing are done for the same configuration (1,1), the
classifier has very high accuracy (91.91% for SVM with
FLDA). The classification accuracies of the remaining
cases are relatively much smaller showing the efficacy
of cross-obfuscation methodology. The right most col-
umn in Table 5 shows average accuracy of four cross-
obfuscation cases (1,2 - 1,5). Best average classification
accuracy of 14.91% among the four pairs was achieved
for SVM with ‘onevsone’ classifier using the FLDA di-
mensionality reduction technique. Classification accu-
racy for each of the cross obfuscation cases among 5
configurations with best case classification for all di-
mensionality reduction techniques is shown in the bar
plot of Fig. 10. Detailed classification results for one
train-test pair (1,4) are shown using confusion matrix in
Table 6. It is to be noted that the configurations shown
in Table 4 were randomly chosen searching through a
large design space. As a result, it is possible to get two
configurations very close to one another resulting in a
higher classification accuracy. However, this classifica-
tion accuracy can be made even lower by deliberately
choosing configurations in a way so that it maximizes
the difference in power traces among similar instruc-
tions from different configurations.
8 Self Obfuscation
In addition to cross-obfuscation, chaos-based design pro-
vides a unique method for self obfuscation where differ-
ent instructions from the same machine have similar
power traces making it very difficult for classification.
The power trace is mostly determined by the choice of
Vc and C. If a set of instructions can be implemented
using the same Vc and C, using different δ and φs , then
their power traces become very similar. The configura-
tion used in this method is shown in Table 7. The value
of Vc and C have been fixed at 0.69 V and 58((111010)2 )
and other control parameters were varied to obtain de-
sired functionality. For multi-output functions like DEC
A Chaos-based Complex Micro-Instruction Set for Mitigating Instruction Reverse Engineering 11

Table 5: Classification accuracy of instruction set among different chaos-based machines (cross-obfuscation) using
several classification and data reduction algorithms.

Category Data Reduction Configuration Pair

1,1 1,2 1,3 1,4 1,5 Average(1,2-1,5)
KNN(=1) No Reduction 89.18 11.73 5.18 8 6.36 7.82
PCA 88.91 8.36 4.91 5.18 5.36 5.95
PCAmean 85.64 11.73 6.18 6.09 5.91 7.47
SDM 73.55 11.09 8 9.09 8.64 9.2
MV 74.55 11 8 8.91 8.64 9.14
FLDA 89.36 16.27 7.09 8.82 10.09 10.57
SVM No Reduction 90.36 13.09 9.36 15.45 15.27 13.3
PCA 91.09 15.27 6.09 14.27 15.27 12.73
PCAmean 89.82 12.91 6.27 10 12 10.3
SDM 51 13.73 7.55 8.27 8.09 9.41
MV 51.64 14.55 6.73 8.55 7.82 9.41
FLDA 91.91 14.91 10.91 15.91 17.91 14.91
DT No Reduction 88 7.09 8.36 11.27 6 8.18
PCA 86.36 10.36 9.27 11.73 10.82 10.55
PCAmean 86.73 11.09 5.73 11.09 10.45 9.59
SDM 82 10 5.91 8.09 6.45 7.61
MV 81.18 14.36 6.55 7.45 6.18 8.64
FLDA 90.82 17.09 5.45 12.91 13.27 12.18
LDA No Reduction 90.73 11.64 3.18 2.82 2.27 4.98
PCA 90.82 14.55 7.55 14.73 14.91 12.93
PCAmean 89.2 12.18 9 12.91 14.36 12.11
SDM 72.73 10.45 5.36 3.18 5.45 6.11
MV 77.18 5 5.27 4.27 4.27 4.7
FLDA 91.27 19.36 6.73 14.18 18 14.57
NB No Reduction 82.36 12.73 11.73 11.64 10.27 11.59
PCA 85.09 8.73 8.82 10.36 10.55 9.61
PCAmean 85.09 11.73 8.45 12.55 11.55 11.07
SDM 43.09 12.64 9.73 8.64 6.82 9.45
MV 42.27 11.82 8.64 8.55 6.82 8.95
FLDA 91.27 23.09 8.18 16.18 17.36 16.2
MVG No Reduction 81.09 0.55 11.27 11.64 10.82 8.57
PCA 92 17.27 5.09 14.09 14.9 12.84
PCAmean 91.18 15.45 5.18 11.09 11.91 10.91
SDM 81.18 8.27 9.45 10.36 9.36 9.36
MV 77.27 9.91 8.82 10.45 7.91 9.27
FLDA 91.45 18.82 4.82 14.18 15.82 13.41

Table 6: Confusion matrix of classification accuracy of different instructions for chaos-based cross-obfuscation im-
plementation. Rows and columns represent the test instruction and percentage of their matched class, respectively.

Instruction Matched Class (%)

AND OR XOR NAND NOR XNOR ADD SUB MUX DEC ENC
AND 0 0 0 0 80 0 0 0 0 20 0
OR 0 0 0 0 85 0 0 0 0 15 0
XOR 0 25 0 0 0 0 0 0 24 11 40
NAND 0 1 0 0 5 0 0 0 44 15 35
NOR 0 4 0 1 0 0 0 0 52 10 33
XNOR 0 26 0 7 0 0 0 0 23 12 32
ADD 0 0 62 0 0 37 0 0 0 0 1
SUB 0 0 0 7 2 0 12 79 0 0 0
MUX 0 3 0 0 1 0 0 0 61 21 14
DEC 0 34 0 0 0 0 0 0 42 0 24
ENC 0 0 0 0 4 0 0 0 39 22 35
12
and ENC, (δ, φs ) pair only the first output is shown.
This strict design choice constrained the design space.
However, it does not create design issues since multiple
configurations are not required for this method. The
results are shown in Table 8. The best results were ob-
tained for NB with ‘onevsone’ technique with a classi-
fication accuracy of 11.67%. This result is very close to
the ideal value of 11.11% (1/9) for perfect obfuscation
involving 9 instructions. The confusion matrix repre-
senting detailed classification results for this classifier
is shown in Table 9.
The results for ADD and SUB are not shown in
these tables, since they have sequential operation in
contrast to the other 9 instructions. Therefore, even
with same Vc and Cb , they can not be fully obfuscated
and can be classified with a relatively high accuracy.
The accuracy of classifying ADD in this configuration
using NB classifier with ‘onevsone’ technique is 77.5%.
Additional design techniques have to be used for obfus-
cating such instructions.
9 Discussion and Future Work
The classification results of a complex micro-instruction
set using power traces for traditional CMOS implemen-
tation as well as two obfuscation schemes using chaos-
based systems are reported in this paper. The results
from various classifiers using five different dimensional-
ity reduction techniques are shown for comparison. The
classification accuracy clearly shows that CMOS imple-
mentations are vulnerable to side channel power analy-
sis attack, whereas chaotic circuit implementation can
alleviate this problem to a large extent. The cross ob-
fuscation scheme can produce indistinguishable power
traces provided the gate design is done carefully in
a manner so that different implementations of identi-
cal instruction have sufficiently different configurations.
The self obfuscation method is an extension of cross
obfuscation which gets rid of designing multiple imple-
mentations since the power traces of a single implemen-
tation can be made almost indistinguishable when two
of the four configuration parameters namely Vc and C
are chosen to be identical across the instruction set. The
obfuscation is almost ideal even for the best performing
classifier.
There are many opportunities for extending this
work in the future. First of all, the map circuit used
in this work is a scaled down topology from [9]. De-
tailed analysis is required to optimize the circuit de-
sign to reduce power consumption, delay and area. The
width and location of chaotic region in the bifurcation
diagram is also an important factor in choosing design
parameters. This particular chaotic map is chosen as
Md Sakib Hasan∗1 et al.
an example to illustrate the premise that chaos-based
design can be effective for immunity against side chan-
nel attack. However, the design methodology does not
depend on this particular three transistor chaotic map
circuit topology. Any combination of ingenuous topol-
ogy and/or emerging device can be used as long as we
get the ‘V’ shape, or alternatively, inverted ‘V’ or tent
shape transfer curve. New device and/or topology can
improve the overhead related to chaos-based design to
make it competitive against conventional CMOS de-
signs. Moreover, in order to overcome the susceptibility
of chaotic gates to noise, detailed noise analysis needs
to be done to make the design robust.
As can be seen from Table 5, cross obfuscation ac-
curacy varies among various designs. More quantitative
measures and metrics can be developed to aid the de-
sign process for multiple implementations.
Self-obfuscation is a more advanced form of obfus-
cation which renders the power traces of an instruc-
tions set inherently indistinguishable. However, to get
the same Vc and C for all the instructions is a very
challenging task. Moreover, in its current form it can
not obfuscate sequential instructions such as ADD and
SUB. New design techniques need to be explored to
overcome this short-coming.
The overhead of using chaotic map for digital circuit
implementation needs to be reduced. Since the main
objective of this work is to illustrate that chaos-based
systems can be used to implement arbitrary complex
3-input multi-output functionality and that the corre-
sponding large design space can enable designers to se-
cure hardware against side channel power attack for
instruction classification. It is a fact that if a single
basic gate is implemented, the chaotic design has large
overhead. However, the chaotic design is reconfigurable,
and unlike CMOS implementation, one can implement
both simple basic gates and relatively complex func-
tionality like ADD, SUB, MUX and DEC using the
same configuration. Moreover, as shown in [28], a suit-
able combination of chaotic and CMOS gates can lead
to an almost ideal obfuscation. The preliminary results
show that the number of chaos gates required increases
roughly logarithmically with the number of bits. More
careful analysis needs to be done to come up with an op-
timization method combining chaotic and CMOS gates
for overhead reduction.
10 Conclusions
In this work, it is shown that a chaos-based design can
be used to generate simple as well as complex 3-input
multiple-output functions using a simple 3-transistor
A Chaos-based Complex Micro-Instruction Set for Mitigating Instruction Reverse Engineering 13

Table 7: Classification of different instructions for chaos-based self obfuscation implementation. Rows and columns
represent the test instruction and percentage of their matched class, respectively.

Config Instructions
AND OR XOR NAND NOR XNOR MUX DEC ENC
δ 1.02 0.28 0.46 0.37 1.18 0.56 0.44 1.18 0.93
φs 5 7 18 4 1 19 9 1 3
Vc 0.69
C 58

Table 8: Classification accuracy among instructions using different classifiers and dimensionality reduction algo-
rithms for chaos-based self obfuscation implementation.

Category Sub-category Dimensionality Reduction Algorithm

No Reduction PCA PCAmean SDM MV FLDA
KNN 1-NN(euc) 10.1 10.94 11.01 10.79 10.79 10.74
3-NN(euc) 10.76 10.96 10.66 11.29 11.29 10.67
5-NN(euc) 11.07 11.03 11.21 10.94 10.94 10.79
1-NN(corr) 10.9 11.56 11.29 11.11 11.11 10.46
3-NN(corr) 11.26 11.17 11.03 11.11 11.11 10.5
5-NN(corr) 11.18 10.96 11.43 11.11 11.11 10.88
1-NN(cos) 10.35 10.81 10.79 10.47 10.476 10.51
3-NN(cos) 10.53 11.24 10.86 10.47 10.47 10.58
5-NN(cos) 11.32 10.95 11.11 10.72 10.72 10.68
SVM onevsall 11.65 10.81 11.62 11.33 10.94 9.69
allpairs 10.94 10.94 11.27 10.19 10.17 11.08
DT onevsall 10.94 11.06 11.11 10.67 10.47 10.14
allpairs 10.17 11.22 10.61 10.81 10.58 10.44
LDA onevsall 10.25 9.64 10.31 10.83 11.17 11.06
allpairs 10.33 10.33 10.39 10.89 11.44 10.28
NB onevsall 11.25 11.42 11.08 11.25 11.03 11.64
allpairs 10.94 11.67 10.31 11.53 11.03 11.47
MVG N/A 11.11 11.14 10.97 11.14 11.06 11.22

Table 9: Confusion matrix of classification accuracy for different instructions in chaos-based self obfuscation im-
plementation. Rows and columns represent the test instruction and percentage of their matched class, respectively.

Instruction Matched Class (%)

AND OR XOR NAND NOR XNOR MUX DEC ENC
AND 4.75 10.75 2.75 5 55 6.75 7.75 2.75 4.5
OR 5.25 12.75 2.5 3.25 52 7.75 7 0.75 8.75
XOR 7 10.75 1.75 3.75 56.5 5.5 6.75 1.25 6.75
NAND 5.75 11.25 2 7.25 51 8.25 8.5 1.75 4.25
NOR 5 9.25 0.75 5 56.75 7.75 6.5 0.75 8.25
XNOR 4 9.75 1.5 4.75 58.5 6.25 6 1 8.25
MUX 5.5 10.25 2.5 6 51.75 7 8.5 1 7.5
DEC 3 10.5 2.25 5 57 6.5 7.75 1.75 6.25
ENC 6.25 13.5 2.75 4.25 54 7.25 5.5 1.25 5.25

chaotic map circuit. The parameters in the chaotic os-
cillator has been chosen carefully in order to minimize
delay, area and power consumption. Two different de-
sign methodologies have been proposed for obfuscation
namely, cross obfuscation and self obfuscation. Cross
obfuscation ensures that an attacker cannot reverse en-
gineer instructions on any other machine by accumulat-
ing data from a reference machine. Self obfuscation is
possible by using chaos gates with a suitable common
configuration for certain parameters since it leads to
similar power traces among different instructions in the
same machine. It has been successfully demonstrated
using various dimensionality reduction techniques along
with several classification algorithms that the logic func-
tions built from properly designed chaos gates can en-
sure security against power based side channel attack.
Proposed design is found to be capable of bringing the
accuracy of instruction classification close to a level of
perfect ambiguity in classification.
14
Acknowledgements
The authors would like to thank Mesbah Uddin from
the University of Tennessee for his help and support.
Funding Information
This work is based upon work supported by the Air
Force Office of Scientific Research under award number
FA9550-16-1-0301.
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