FLIP-FLOPS

P RAHUL BHARADWAJ

17CS02003

Aim :
➢ To implement a D-Flip flop.
➢ To implement a T flipflop using D flip-flop.
➢ To implement a JK flip-flop using D flip-flop.
➢ To implement T flipflop, D flip-flop, JK flip-flop using manual clock.
➢ To design a simple clock divider to convert 100MHz to 1 Hz.

D-Flip flop:

Excitation Table :
Characteristic Table : Q(t) Q(t+1) D
0 0 0
D Q
0 1 1
1 1 1 0 0

0 0 1 1 1

Characteristic Equation : Q(next) = D

T-Flip flop:

Characteristic Table Excitation Table

Q(t) Q(t+1) T
T Q
0 0 0
1 ~Q 0 1 1
1 0 1
0 Q
1 1 0

Characteristic Equation : Q(next) = T Q ’ + T ’ Q

JK-Flip flop :
Characteristic Table : Excitation Table

J K Q(t+1) Q(t) Q(t+1) J K

0 0 0 0 0 0 X
0 1 Q 0 1 1 X
1 0 1 1 0 X 1
1 1 Q’ 1 1 X 0

Characteristic Equation : Q(next) = J Q ’ + K ’ Q

Verilog Code

module D_flip ( //code for D flipflop

input d,
input clk,
input rst,
output reg q, // ‘reg’ means register which stores the prev. values
output reg qbar
);

// an always block executes and reexecutes indefinitely

always@(posedge clk) //’posedge’ means responds to positive edge of clock
begin
if(rst==0)
begin
q<=0;
qbar<=1; //’begin’ and ‘end’ statements are used to start & close the loop
end
else
q<=d;
qbar<= ~d;
end

endmodule
module T_flip ( //code for T flipflop
input t,
input clk,
input rst,
output q,
output qbar
);
wire w1;
assign w1 = T ^ Q ; // T ^ Q gives us the input to D flipflop
D_flip A(rst, clk, w1, Q, Qbar);

endmodule

module JK_flip( //code for JK flipflop

input rst,
input clk,
input J,
input K,
output Q,
output Qbar
);
wire w2;
assign w2 = (J && Qbar) || (~K && Q); // input to D flipflop
D_flip B(rst, clk, w2, Q, Qbar);
endmodule

module clkd(
input clk, //code for clock divider
output reg clkout
);
reg [25:0] count; // an internal register ,just like a variable
always@(negedge clk) //responding to negative edge of the clk
begin
count<=count+1;
if(count==50000000) //change the state of clk for every 0.5 sec
begin
clkout <= ~clkout;
count<=0;
end
end
endmodule

NOTE: Set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]

is used in XDC file to design flipflop using manual clock.
Behavioural Implementation of JK Flipflop:

module JK_flip(
input J,
input K,
input clk,
output reg Q,
output reg Qbar,
input pst,
input clr
);
always@(negedge clk,posedge clr,posedge pst)
//responds to -ve edge of clk,+ve edge of clr,pst
begin
if(clr==1)
begin
Q<=0;
Qbar<=1;
end
else if(pst==1)
begin
Q<=1;
Qbar<=0;
end
else if(J==0&&K==0) // following the state table
begin
Q<=Q;
Qbar<=Qbar;
end
else if(J==0&&K==1)
begin
Q<=0;
Qbar<=1;
end
else if(J==1&&K==0)
begin
Q <= 1;
Qbar <=0;
end
else if(J==1&&K==1)
begin
Q<=Qbar;
Qbar<=Q;
end
end

endmodule
Important Observations:

In the experiment, the reset was given as a synchronous input but we desire it to be
asynchronous. Synchronous reset means reset is sampled with respect to clock. In other
words, when reset is enabled, it will not be effective till the next active clock edge whereas In
asynchronous reset, reset is sampled independent of clk. That means, when reset is enabled
it will be effective immediately and will not check or wait for the clock edges. The necessary
changes to the HDL code when we take asynchronous reset goes as follows..

module D_flip (

input d,
input clk,
input rst,
output reg q,
output reg qbar
);
always@(posedge clk or posedge rst)

begin
if(rst==0)
begin
q<=0;
qbar<=1;
end
else
q<=d;
qbar<= ~d;
end
endmodule

Conclusion :
From the part of experiment done in the lab we learnt how to implement D-flipflop,
JK flipflop, t flipflops and also the implementation of Clock divider on FGPA.
We learnt Verilog syntax or HDL code for the implementation of flipflops on FGPA.
We also learnt the working of Flipflops using the clock manually (manual clock).

Flip flops will find their use in many of the fields in digital electronics .
They are the main components of sequential circuits. Particularly, edge triggered flip
flops are very resourceful devices that can be used in wide range of applications like
storing of binary data, counter, transferring binary data from one location to other.