Eco Flow

ECO Flow
© Mirafra Technologies 1
Agenda
 ECO – Engineering Change Order

 ECO Flow
 Functional ECO
 Timing ECO
 Priority-wise Violations Fixing
 Distributed Multi-Scenario Analysis (DMSA)
 Power Recovery ECO
 Physical Aware ECO
 Metal ECO-Metal configurable Gate Array spare cells
ECO- Engineering Change Order
Correction of a logic error during the PD-flow– Functional

ECO
Exchange of timing critical modules during the PD-flow for

logic redesign– Timing ECO
ECO Flow
• An engineering change order (ECO) is an incremental change
made to a complete or nearly complete design. You can use
ECOs to fix functional, timing, noise, and crosstalk violations
without synthesizing, placing and routing the entire design. You
can also use ECOs to implement late-arriving design changes
while maintaining design performance.
• We source the ECOs in the form of tcl scripts in the design to

for logical connectivity and perform incremental placement
and legalization and incremental routing to
connect/disconnect the added logic physically.
Functional ECO Flow
1. PD-Designer sends the current netlist to the logic designer

2. Logic designer inserts manually cells and nets and writes a TCL-script
3. PD-Designer executes the TCL script on his netlist
Spare cells for ECOs
(Note : If there are spare cell present in the design , these can be mapped to the
logic added in the design)
ECO Flow
• Disadvantage
Time consuming and can be faulty
After passing the netlist to the logic designer, the physical
designer is not allowed to change the net and cell names
No cloning or inserting of inverters is allowed
Remaining false cells increase fan-in, consume area and power
(Better to remove these cells)
• Advantage
ECO is possible in very late stages of PD (Metal-ECO)
Timing ECO
• If your design has timing and design rule violations, or you want to
optimize area or power, PrimeTime SI and PrimeTime ADV ECO
guidance can automatically fix design rule and timing violations.
• With this capability, you can evaluate possible fixes quickly and
minimize time-consuming iterations in the physical implementation
flow.
• Fixing design rule violations has the highest priority.
• Setup or hold fixing does not degrade design rule violations, but fixing
design rule violations can degrade setup or hold violations.
• You should first fix design rule violations, followed by setup violations,
and then hold violations, as described in the following flow.
Priority-wise Violations Fixing
• Clock Transitions
• Data Transitions
• Data Cap
• Setup violations
• Hold Violations
• Min-Pulse and Min-Period violations
• SI Violations (Noise/Glitch)
You can use fix_eco_drc , fix_eco_timing -type setup ,

fix_eco_timing -type hold command to generate timing ECOs to fix
timing violations.
Distributed Multi-scenario Analysis (DMSA) :
Primetime has the ability to run a distributed multi-scenario analysis
(DMSA) ECO even if the number of scenarios exceeds the number of
available hosts. You can use this capability when running the ECO
fixing commands.
We need to enable DMSA ECO fixing by setting
eco_enable_more_scenarios_than_hosts to true.
Make Sure you have sufficient hosts and memory before running
DMSA options as it need multiple hosts and huge memory.
If number of hosts are less, Scenarios will be taken sequentially ,
which will cause huge run time.
Script modifications for faster turnaround time
Power Recovery ECOs
• PrimeTime can optimize your design by performing power
recovery. The tool recovers power on paths with positive
slack by swapping cells based on
• Cell area
• Threshold voltage
• User-defined power attribute
• Use fix_eco_power to generate the ecos for Power

reduction in the design.
Report Power
• Use report_power command to find the power consumed in the design before
and after the Power ECOs implemented.
Fix_eco_power
With the fix_eco_power command, you can reduce
leakage power with the following operations:
•Cell Swapping Based on Library Cell Names :-When the

library cells follow the recommended naming convention.
•Cell Swapping Based on User Defined Attributes :- When

the library cells do not follow the recommended naming
convention.
fix_eco_power -pattern_priority {best ok worst}
-attribute vt_swap_priority
We can use DMSA for Power Recovery as well
Physically-Aware ECO
• The Primetime tool works well with IC Compiler and StarRC to fix
design rule constraint, timing, and noise violations while considering
physical placement and routing information.
Benefits of Physical Aware ECOs:
• Improves ECO fixing rates and predictability
• Adds placement locations to changed cells
• Avoids large displacements when resizing cells
• Considers available space, placement density, and wire
delay when inserting buffers
• Performs on-route buffering when fixing violations
• Results in faster ECO convergence by minimizing the
disturbance to the physical layout
Requirements for Physically-Aware ECO
Insert filler cells
• After achieving the routing closure in the ECO routing, filler
cells are used to fill the remaining gaps in the design.
• There are two advantages of filling.
Ensure the continuity of the power and ground rails in the floorplan.
Ensure the continuity of the N+/P+ well.
Without Filler Insertion After Filler Insertion

Cont’d…
• As Mentioned previously, Fillers are used to provide N/P
well continuity.
• There are special type of cells/fillers which are used while
filler insertions .
• There are in-built transistors in these cells without any
connectivity. These cells act as spare cells in the design.
• These cells are called as Gate array cells, Which are
mapped to gates after Base is frozen.
• Base freeze : No option changing Base layers.
Metal ECO-Metal configurable Gate Array
spare cells
• A gate array is an integrated circuit whose internal structure is
an array of gates with interconnects initially unspecified [2].
• The GA implementation can be divided into two steps.
1. Making transistor masks which is an array of uncommitted
transistors gates on the GA chip
2. Metal interconnection between the transistors to configure a logic
functionality.
Array of unconnected transistors
GA type base cell to realize
metal-only ECO
GA type base cell to realize
metal-only ECO
Thank You

Eco Flow

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Eco Flow

Caricato da

Copyright:

Formati disponibili

ECO Flow

 ECO – Engineering Change Order

Correction of a logic error during the PD-flow– Functional

Exchange of timing critical modules during the PD-flow for

• We source the ECOs in the form of tcl scripts in the design to

1. PD-Designer sends the current netlist to the logic designer

You can use fix_eco_drc , fix_eco_timing -type setup ,

• Use fix_eco_power to generate the ecos for Power

•Cell Swapping Based on Library Cell Names :-When the

•Cell Swapping Based on User Defined Attributes :- When

Without Filler Insertion After Filler Insertion

Potrebbero piacerti anche