UNIT-I

Short answer questions

1. Convert the gray code 1101 to binary.

2. How do you perform subtraction using the 2’s complement method.
3. What do you mean by self-complementing codes, give examples?
4. State DeMorgan’s theorem.
5. Convert (2468)10 to ( )16.
6. State and prove consensus theorem.
7. Convert the decimal number 250.5 to base 2.
UNIT-II
1. How can a two input X-OR gate be used as an inverter?
2. What are essential prime implicants?
3. What are the advantages of tabulation method over K-map.
4. Convert the given expression into canonical SOP form F = AB+BC+CA
5. How do you obtain the dual of an expression
6. What is a prime implicant chart

Long answer Questions

UNIT-I & II

1. Convert the following numbers

i. (41.6875)10 to binary ii. (1001001.011)2 to decimal iii. Find the 9’s complement of
number (25.639)10
2. i) Subtract 111001 from 101011 using 2’s complement.
ii) What are universal gates? Realize AND, OR gates using NAND gate.
3. Decode the message assuming that at most a single bit error occurred in each code word
when it is transmitted through a noisy channel using 7-bit Hamming code. 1110111,
0011011, 1101101, 1011101
4. Using 2’s compliment method perform i) (57)10 - (28)10 ii) (-75)10 + (26)10
5. What is meant by parity checking? Explain the parity checking method for single bit error
detection and correction with suitable examples.

6. Explain the concept of positive logic and negative logic. Also draw the truth tables for
positive logic AND gate and negative logic OR gate.
7. Obtain the dual of the following Boolean expressions
i) AB+(AB)’+AB’C ii) A’B’C’+A’BC’+AB’C’+ABC’
8. Find the complement of the following expressions i)AB+A(B+C)+B’(B+D) ii)A+B’C(A+B+C’)
9. Obtain the minmal SOP expression for ∑m(2,3,5,7,9,11,12,13,14,15) and implement it using
NAND logic.
10. i)Find the complement of the function F=X(Y'Z'+YZ)
ii)Reduce the following Boolean expression to two literals F = A C+B+B +AB + C
11. Draw the multiple level NOR circuit for the following expression: A(B + C + D) + BCD
12. Draw a NAND logic diagram that implements the complement of the following function.
F(A,B,C,D) = ∑(0, 1 ,2, 3, 4, 8, 9, 12)
13. Using K-Map obtain minmal SOP for the given function.
F(A,B,C,D,E)=∑(18,19,20,21,22,23,26,29,30,31)+d(10,11,13,14,15,27,28) and draw the logic
circuit for simplified expression using only NAND gates.
14. Using Quine-McCluskey method, minimize the function f(W,X,Y,Z)=∑m(0,1,5,7,8,10,14,15)
 PRASAD V POTLURI SIDDHARTHA INSTITUTE OF TECHNOLOGY
SUBJECT: SWITCHING THEORY AND LOGIC DESIGN
TUTORIALS(A.Y-2019-2020)

Tutorial-I
1. Convert (2468)10 to ( )16 and (250.5)10 to base 2.
2. Convert the following numbers
i. (41.6875)10 to binary ii. (1001001.011)2 to decimal iii. Find the 9’s complement of
number (25.639)10
3. Using 2’s compliment method perform i) (57)10 - (28)10 ii) (-75)10 + (26)10
4. Convert the gray code 1101 to binary.
5. What do you mean by self-complementing codes, give examples?
6. State DeMorgan’s theorem.
7. State and prove consensus theorem.
Tutorial-II
1. Decode the message assuming that at most a single bit error occurred in each code word
when it is transmitted through a noisy channel using 7-bit Hamming code. 1110111,
0011011, 1101101, 1011101
2. What are universal gates? Realize AND, OR gates using NAND gate.
3. Explain the concept of positive logic and negative logic. Also draw the truth tables for
positive logic AND gate and negative logic OR gate.

Tutorial-III
1. Obtain the dual of the following Boolean expressions
i) AB+(AB)’+AB’C ii) A’B’C’+A’BC’+AB’C’+ABC’
2. Find the complement of the following expressions i)AB+A(B+C)+B’(B+D) ii)A+B’C(A+B+C’)
3. i)Find the complement of the function F=X(Y'Z'+YZ)
ii)Reduce the following Boolean expression to two literals F = A C+B+B +AB + C
4. How can a two input X-OR gate be used as an inverter?
5. Convert the given expression into canonical SOP form F = AB+BC+CA
6. What are the advantages of tabulation method over K-map.
7. Obtain the minmal SOP expression for ∑m(2,3,5,7,9,11,12,13,14,15) and implement it using
NAND logic.
Tutorial-IV
1. Draw the multiple level NOR circuit for the following expression: A(B + C + D) + BCD
2. Draw a NAND logic diagram that implements the complement of the following function.
F(A,B,C,D) = ∑(0, 1 ,2, 3, 4, 8, 9, 12)
3. Using K-Map obtain minmal SOP for the given function.
F(A,B,C,D,E)=∑(18,19,20,21,22,23,26,29,30,31)+d(10,11,13,14,15,27,28) and draw the logic
circuit for simplified expression using only NAND gates.
4. Using Quine-McCluskey method, minimize the function f(W,X,Y,Z)=∑m(0,1,5,7,8,10,14,15)
 Tutorial-7
1. Distinguish between serial and parallel adder.
2. Why binary to octal converter is called as 3x8 decoder.
3. Discuss a few applications of multiplexers and distinguish between multiplexer and decoder.
4. Realise the following functions using decoder and additional OR gates.
F1=AB+B’C+AD’ F2=∑m(0,1,3,5,13,14,15) F3=∏M(0,1,3,10,14,15)
5. Implement the full adder using decoder and OR gates
6. Design of even parity bit generator for 4bit input.

Tutorial-8
1. Why do go for priority encoder rather than normal encoder.
2. Implement the following using PLA
F1=∑m(0,4,7) F2=∑m(1,2,3,6)
3. Write a brief note on PLDs.
4. How is the size of PLA is specified.
5. Implement two input EX-OR gate from 2 to 1 multiplexer.
6. Write the demerits of PROM.
7. How can a ROM device can be considered as combinational circuit.
8. Implement the following function Using PAL F1(A,B,C,D)=∑m(6,8,9,12,15)
F2(A,B,C,D)=∑m(1,4,7,10,13) F3(A,B,C,D)=∑m(4,7,10,11) F4(A,B,C,D)=∑m(4,7,9,15)
9. Realize the following function using 8 to 1 multiplexer.
10.Implement the following function using 8:1 MUX and 4:1 MUX F(A,B,C,D)=
∑m(0,1,2,4,6,9,12,14)
11.Realize the following using PROM
F1=∑m(0,4,7) F2=∑m(1,3,6) F3=∑m(1,2,4,6)

Tutorial-9
1. Compare synchronous seq circuits s and Asynchronous sequential circuits& Convert D FF to T
FF
2. Design a modulo-8 ripple counter.
3. Design a modulo-12 ripple counter.
4. Design a modulo-6 Graycode synchronous counter.
5. Draw and Explain the a) SR Latch and SR FF’S b) D-FF &D-Latch d)T FF
6. Explain the operation of negative edge triggered J-K -flip-flop with active low preset
and clear using NAND gates. Give its truth table.
7. what is shift Register? Draw the block diagram and timing diagram of a shift register
that shows the serial transfer of information from register A to register B.
8. Explain synchronous and ripple counters. Compare their merits and demerits.
9. Give the block diagram of synchronous and asynchronous sequential circuits and list
out the merits and demerits.
10. What is race around condition? How it can be eliminated ?
11. Compare combinational and sequential circuits.
 Tutorial-10
1. Design a serial adder based on Mealy model.
2. Distinguish between moore and mealy machines.
3. Write down the steps involved in Synchronous sequential machines. Explain it with
examp
4. Design a circuit to detect the sequence 1101.
5. Design a modulo-12 up synchronous counter using T- flip flops and draw the circuit
diagram.
6. Design clocked sequential circuit with single input and single output to produce an
output Z= 1 when ever the input X completes sequence of pulses 10101 overlapping is
also allowed. Draw the circuit using T-Flip
7. Explain the following related to sequential circuits with suitable examples. a) State
diagram 6 M b) State table c) State assignm