Assignment 3

Using Sentaurus TCAD, simulate the Log(Id)-Vgs (for Vds =1V) and Id-Vds (for Vgs
=1V) characteristics and compare the energy band profiles in lateral (S-->D) direction for
Vgs = 0V, Vds = 0V and

Vgs = 0V, Vds = 1V for Bulk n-MOSFETs having following specifications:

Contact: Al (WF=4.1)

Semiconductor: Si

Gate Metal: Gold (WF=5.1)

Gate Insulator: SiO2

Gate Insulator thickness: 3 nm

Bulk thickness: 300 nm

Source/Drain Length: 100 nm

Source/Drain doping: 1E19 cm-3

1. For channel doping (channel length 500 nm):

A. 1E16 cm-3

B. 1E17 cm-3

C. 1E18 cm-3

2. For channel length (channel doping 1E17 cm-3):

A. 100nm

B. 500nm

C. 1000nm

Solution :
Following are the graphs of the Log(Id)-Vgs (for Vds =1V) and Id-Vds (for Vgs =1V)
characteristics
1:A – channel doping 1E16 cm-3, channel length -500nm

Fig : Id Vs Vgs (Vds= 1)

Fig : ID Vs Vds(Vgs=1)
1:B – channel doping 1E17 cm-3, channel length -500nm

Fig : Id Vs Vds (Vgs= 1)

Fig : log(ID) Vs Vgs

1:C – channel doping 1E18 cm-3, channel length -500nm

Fig : Id Vs Vds (Vgs= 1)

Fig : log(ID) Vs Vgs

2:A – channel length -100nm ; channel doping 1E17 cm-3

Fig : Id Vs Vds (Vgs= 1)

Fig : log(ID) Vs Vgs

2:B – channel length -500nm ; channel doping 1E17 cm-3

Fig : Id Vs Vds (Vgs= 1)

Fig : log(ID) Vs Vgs

From the graphs, (IV characteristics : Id Vs Vds)

• The common observation from the above plots is that the drain current magnitude is
increasing with increase in doping concentration. It is to note that the values of gate
voltage in all the cases are kept constant.
• The increasing drain current leads to the increasing slope of the IV characteristics curve,
inverse of which decreases which is nothing but the ON resistance of the MOSFET .
• The accumulation and inversion gets stronger with increasing doping of the channel but
the threshold voltage increases. This results in lower saturation voltages of the MOSFET
as Vsat = Vgs-Vt and Vgs =1V in our study.
• The drain current depends on drain to source voltage parabolic in the ohmic or the linear
region. Eventually, the allowed charges considered in the conduction are based on
gradual channel approximation and can be seen form the graph.
• The resistance of the channel is proportional to its width-to-length ratio; reducing the
length leads to decreased resistance and hence higher current flow. Thus, channel-length
modulation means that the saturation-region drain current will increase slightly as the
drain-to-source voltage increases

From the graphs, (Transfer characteristics: (Id Vs Vgs)

• The drain current increases beyond certain value of Vgs , called the “Threshold voltage”
of MOSFET. On increasing the doping concentration of the channel, the threshold voltage
increases. This results in large margin on the ON state and less margin in the OFF state of
the MOSFET. For a particular Vds, the mosfet is in initial cutoff state, then the saturation
region and finally the linear region as the Vgs progresses.
• As the Vgs increases, the lateral field in the junction increases. This leads to formation of
inversion charges at the oxide substrate interface. This point being called Onset of
Inversion. As the Vgs goes further, the electron concentration increases enough to level
the majority concentration in substrate. This value of Vgs called Threshold voltage. After
further increase, the current increases rapidly due to firmly formed channel.
• Id is inversely proportional to the channel length .The lateral field applied due to Vgs
distributes equally among the channel. Therefore, the increase in Vgs has no significant
effect on the length and finally the drain current.
Following are the graphs of the Lateral Energy band profiles in lateral (S-->D)
direction for Vgs = 0V, Vds = 0V and Vgs = 0V, Vds = 1V

1:A – channel doping 1E16 cm-3, channel length -500nm

Fig : Energy Band Profile for Vgs=Vds=0(Equilibrium)

Fig : Energy Band Profile for Vgs=0,Vds=1

1:B – channel doping 1E17 cm-3, channel length -500nm

Fig : Energy Band Profile for Vgs=Vds=0(Equilibrium)

Fig : Energy Band Profile for Vgs=0,Vds=1

1:C – channel doping 1E18 cm-3, channel length -500nm

Fig : Energy Band Profile for Vgs=Vds=0(Equilibrium)

Fig : Energy Band Profile for Vgs=0,Vds=1

2:A – channel length -100nm ; channel doping 1E17 cm-3

Fig : Energy Band Profile for Vgs=Vds=0(Equilibrium)

Fig : Energy Band Profile for Vgs=0,Vds=1

2:B – channel length -500nm ; channel doping 1E17 cm-3

Fig : Energy Band Profile for Vgs=Vds=0(Equilibrium)

Fig : Energy Band Profile for Vgs=0,Vds=1

From the graphs, (Lateral Energy band profiles in lateral (S-->D) direction for Vgs
= 0V, Vds = 0V and Vgs = 0V, Vds = 1V)
• The equilibrium energy of the substrate being the p-doped region is higher than the n-
doped source and drain. On increasing the Vgs, the electron concentration increases in
the channel and hence the respective energy bands lower according to the potential
developed near the gate region , keeping the energy gap constant as the semiconductor
is not changed. The increase in the Vds value bends down the energy band to the drain
side because the drain substrate reverse bias increases.
• The fermi level is aligned in every region because of the absence of the external bias .
• The channel glitch is formed in the source gate interface when the precision cut is formed
very near to the channel because of the potential developed due to inverting charges in
the channel. This pheneomenon is given as “EC_near” and EV_near” in the respective
plots. As we go far from the channel, the energy diagram starts resembling to typical
energy profiles of the MOSFETs.