QP-I/17MT14502

MAHENDRA ENGINEERING COLLEGE

(AUTONOMOUS)
Continuous Assessment Test - II – Aug - 2019
Regulations – 2017
Academic Year 2019 – 2020, Odd Semester
Programme : BE Year :III Semester: V
Subject Code:17MT14502 Subject Title :Microprocessor & Microcontroller
Date: 04.09.2019 Time: 2.45pm-4.15pm Maximum Marks: 50
PART – A (1x6=6) (Multiple choice one mark questions)
The ________of the memory chip will identify and select the register for the EPROM
1 CO3 K1
a) internal decoder b) external decoder c) address decoder d) data decoder

The mode of 8237 in which the device transfers only one byte per request is
2 CO3 K2
a) block transfer mode b) single transfer mode c) demand transfer mode d) cascade mode

The timer generates an interrupt, if the count value reaches to

3 CO3 K3
a) 00FFH b) FF00H c) 0FFFH d) FFFFH
Among the five interrupts generated by 8051, the highest priority is given to the
4 CO4 K1 interrupt
a) IE0 b) TF1 c) TF0 d) IE1
The storage of addresses that can be directly accessed is
5 CO4 K2 a) external data RAM b) internal data ROM c) internal data RAM and SFRS
d) external data ROM and SFRS
Which of the following is bit-addressable register?
6 CO4 K2
a) SBUF b) PCON c) TMOD d) SCON
PART – B (10x2=20)( Two mark questions)
State the advantage and disadvantage of parallel communication over serial
7 CO3 K1
communication.
8 CO3 K1 Name the applications of programmable interval timer.
9 CO3 K2 Summarize the modes used by the DMA processor to transfer data.
10 CO3 K4 Point out the uses of handshake signals in mode-2 configurations of 8255.
11 CO3 K2 What is meant by key bouncing?
12 CO4 K4 Distinguish between microprocessor & micro controller.
Describe hardware and software interrupts in 8051. Mention
13 CO4 K1
Its vector addresses.
14 CO4 K2 What is meacant by PSW in 8051?
15 CO4 K1 List the interrupts available in 8051. Mention its vector address & priority.
16 CO4 K3 Show the bit manipulation instructions. Give two examples.
PART – C(2x12=24) (12 Marks questions)
17
CO3 K1 Explain the operation of parallel communication interface with a neat diagram.
(i) (6)
Discuss how a PIC, 8259 is interfaced to an 8086 based
(ii) CO3 K2
system. How does 8259 service an interrupt? (6)
Illustrate in detail about the architecture of 8051microcontroller with neat
18 CO4 K4 (12)
diagram.

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Course Outcome (CO):

S.No. Question numbers Course Outcome Marks

1 1,2,3,7,8,9,10,11,17 CO1 25

2 4,5,6,12,13,14,15,16,18 CO2 25

Bloom’s Taxonomy Level

K1- Remember, K2- Understand, K3- Apply, K4- Analyze, K5- Evaluate and K6- Create

Bloom’s
K1 K2 K3 K4 K5 K6
Taxonomy level
Percentage of
36.84 36.84 10.52 15.79 - -
Questions

Subject Teacher HOD

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