Amkor’s Next Generation

of Packaging Solutions … the future is now!

Amkor Confidential I Sep-15 1

Agenda
Strategic Technology Roadmap

Differentiating SLIM & SWIFT

Development Overview

Conclusions

Amkor Confidential I Sep-15 2

Semiconductor Packaging Evolution

Improve board Improve

Reduce cost
space floor plan performance
 Desire to integrate  Avoid cost of  Higher bandwidth
multiple chips on a expensive silicon  Lower power
single package nodes below 14nm
platform  Keep package size pin
 Reduce floor space of out the same while
package platform (thin reducing chip size
& small)

Amkor Confidential I Sep-15 3

Semiconductor Packaging Interconnect Evolution
Evolving
Organic Substrate Foundry
Lowest Cost
OSAT

Substrate

GAP!

Bump BEOL
Highest Cost

PCB Design Rule ~8 < 1µm Wafer Design Rule

100µm 10µm 1µm 10nm

Amkor Confidential I Sep-15 4

Amkor’s Package Technology Integration Roadmap
Mobile Products High Perform Products
Substrate Level rtMLF
(On Board RDL)
fcCSP FCBGA

WLCSP
Wafer Level 10um
Adv Subst Process
(Bump Line RDL) (dual substrate)
5um
SWIFT™
(Single die / Multi die) Thin Film on Subst

Foundry Level 2um

(BEOL RDL) SLIM™ SLIM™ Si Interposer

• SWIFT: Silicon Wafer Integrated Fan-out Tech

• SLIM : Silicon-less Integrated Module
HVM LVM Proto Develop

Amkor Confidential I Sep-15 5

TSV Transition To SLIM / SWIFT
 Efficient way to connect die to die and die to board at lower cost

Typical 2.5D cross section SLIM package for the same TV

Amkor Confidential I Sep-15 6

Flip Chip CSP and SiP Migration to SWIFT
 Mainly to reduce form factor and profile

 SWIFT: Passive integration at wafer level and multi die packaging

Amkor Confidential I Sep-15 7

SLIM & SWIFT Package Definition

SLIMTM SWIFTTM
Silicon-Less Integrated Module Silicon Wafer Integrated Fan-out Technology

Top die 1 Top die 2 Top die 1 Top die 2

S
ol EMC EMC UF

d UF Sold
er
er ball

b
3
al r
d
2
l Passivation3 n
d R
Passivation2
D
R L
D
RDL
Passivation1
L 1st RDL

PBO

Sold Solder
er ball

ball

Top die Top die

U-bump solder joint U-bump solder joint
Fab. BEOL layer
RDL layer RDL layer

BGA BGA

Amkor Confidential I Sep-15 8

SLIM / SWIFT Package Options
Wafer Level Package Format Flip Chip Package Format

SLIM Size
e.g. 11mm

15mm 15mm

Thinner package profile Thicker than WLCSP type

TSV-less interposer size = package size TSV-less interposer size < package size

Amkor Confidential I Sep-15 9

SLIM / SWIFT Package Variants
Wafer Level Flip Chip Package

W-SLIM / SWIFT, TMV/3D

SLIM / SWIFT on Substrate – 2D

W-SLIM / SWIFT, FIPOP/3D

SLIM / SWIFT on Substrate – CSP 2D or 3D POP

W-SLIM / SWIFT, 2D Compatible

Amkor Confidential I Sep-15 10

Amkor’s Advanced WLP Positioning
Performance
 Multi dies, SoC partition, 3D compatible
 < 2um L/S by foundry interposer BEOL
 High performance (CPU/GPU), mobile AP, BB
W-SLIM

 Single/Multi die, SoC partition, 3D

SWIFT  2~10um L/S interconnect by bumping RDL
 Mobile AP / BB, mid-range CPU/GPU

 Single die
WLCSP  RDL > 10um L/S
 RF, WLAN, Power etc.

Products : RF and Analog to Advanced Processors

Amkor Confidential I Sep-15 11
Amkor’s Advanced Flip Chip Product Positioning
Performance  Multi die, SoC partition, HBM, 3D compatible
 RDL ≤ 2um L/S by foundry BEOL interposer
 Ultra Thin
 Lower cost ; SLIM ˂ 2.1D / 2.5D
S-SLIM
 Multi die, SoC partition, HBM, 3D compatible
2.5D  RDL ≤ 2um L/S by foundry BEOL interp. + TSV

 HBM integration
2.1D  RDL 2~10um L/S by substrate

Advanced  Single or multi die

fcCSP / FCBGA  RDL > 10um L/S by subtrate
 3D compatible

Products : AP, BB, CPU, GPU and Networking

Amkor Confidential I Sep-15 12
 Process Differentiation
Leverage high yield process
Die face down
Fab. BEOL process
RDL fabrication first
Chip attach and mold last
Flip chip attach
High accuracy die placement
Self alignment by solder joint
High UPH chip placement
No die shift / rotation issue
Flexibility
Different package form possible
Die thickness / Mold interface
etc.
Amkor Confidential I Sep-15 13
 Simplified Process Flow

Amkor – Die Last Competitors – Die First

2. CoW Top die 1 1. Re-con.

EMC UF
Solder
ball

Passivation3 3rd
Cycle time
1. RDL wafer Passivation2
Passivation1
2nd RDL
RDL
1st RDL 2. RDL
PBO
Sold
er
3. BGA or C4 + Substrate ball
3. BGA
Cycle time

Amkor Confidential I Sep-15 14

Key Process Capability
 Wafer processing (Bumping and MEOL) at K4 and Assembly at K1

Bumping MEOL Assembly

• Fine pitch u-bump • Carrier bond- • CoW chip attach
• NiAu pad debond • Wafer underfill
• Multi-layer RDL • Si grinding and mold
• Low temp. cure • Si etch • CSP or FCBGA w/
PSPI • Oxide etch lid
• Tall Cu post

Amkor Confidential I Sep-15 15

 Key Module Development Summary
Tall Cu pillar for memory interface
Molded 12inch CoW wafer processing - 180um tall Cu demonstrated
- Available

Fine pitch u-bump interconnection

- CoW chip attach with mass reflow
Fine L/S multi RDL
Backside pattern reveal and carrier attach - 40/45um available
- 5/5um available
- Available - 30um demonstrated
- 3L RDL demonstrated

Amkor Confidential I Sep-15 16

Package Level Reliability
 Customer TV data

Test item Pre-con Condition Result

(O/S daisy chain test)

TC B L3/260 55C/125C Pass

– 1000cycle

HAST L3/260 130C/85%RH Pass

– 96hrs

HTS NA 150’C pass

– 1000 hours

Amkor Confidential I Sep-15 17

Board Level Reliability
TC Drop • JESD22-B111 compliant board
Leg
(- 40 ~ 125℃, 1CPH) (1500G, 0.5 ms duration) • 15 units per board
Board UF SS 1st fail Mean life 63.2% life SS 1st fail Mean life 63.2% life • 8L PCB, 1mm thickness
w/o UF 30 199 285 303 30 57 288 320
UF 30 N/A N/A N/A 30 N/A N/A N/A

TV cross section: 10mm x 10mm package body SLIM

40um pitch u-bump

529 I/O, 0.25mm ball on 0.4mm pitch

Amkor Confidential I Sep-15 18

Key Milestones
SLIM
Key Gates
SWIFT
1. Feasibility Complete

2. Validation

3. Intern Qual

4. Corner Eval

5. Cust. Qual

6. Production

Q1 2015 Q2 2015 Q3 2015 Q4 2015 Q1 2016 Q2 2016 Q3 2016 Q4 2016

Amkor Confidential I Sep-15 19

Conclusions
 SLIM / SWIFT bridges the gap between TSV and traditional substrate
and wafer fan-out packaging

 SLIM / SWIFT technology is designed to provide increased I/O and

circuit density within a reduced footprint and profile for single & and
multi-die applications

 Finally, SLIM / SWIFT technology enables the creation of advanced 3D

structures that address the need for increased IC integration in
emerging mobile and networking applications
Amkor Confidential I Sep-15 20
Thank You!

Amkor Confidential I Sep-15 21