A Fast Settling Slew Rate Enhancement technique

for Operational Amplifiers

Siddhartha, Gopal Krishna, Bahar Jalali-Farahani
Electrical Engineering,
Arizona State University
Tempe, AZ – 85287. USA
Siddhartha.Gopalkrishna@asu.edu

Abstract—This paper presents a fast settling SRE (Slew Rate

Enhancement) technique for operational amplifiers. An opamp II. MOS ACROSS TEMPERATURE
using a constant-gm biasing together with the proposed SRE Several important parameters of CMOS devices are
circuit is designed and it is shown that stable large and small
function of temperature. The mobility of electrons and holes
signal characteristics can be achieved across the wide range of
temperature. The opamp was designed and laid out in Jazz depend on the temperature according to [6]:
0.18µm process using 1.8V supply voltage. The core circuit
consumes 3mA while the SRE circuit has a static power (1)
consumption of only 200uA (%6.67 of the power of the core
circuitry). The slew rate of the opamp has increased from 25
As it can be seen from equation (1), the mobility is
V/us to 150 V/us at room temperature. The low variation of both
small signal as well as large signal characteristics of the opamp decreasing with temperature. Threshold voltage also decreases
across the temperature has been verified by Spectre simulation with temperature as follows [6]:
using PSP models.
(2)
I. INTRODUCTION
The combined effect is an improvement in current driving
Electronic circuits are used in a variety of applications
capability as well as transconductance (gm) of the devices at
where they may experience wide temperature fluctuations.
low temperature. These observations are valid at temperatures
Since threshold voltage and mobility are strong functions of
higher than 40K. As the temperature drops below 40K another
temperature and result in significant change in dc operating
phenomenon called carrier freeze happens that results in a
point of devices across a wide range of temperature. Heating
drop in mobility and therefore reduces the gm and current of
and/or cooling systems can be used; however, they impose a
the device.
significant overhead and add complexity to the system.
Recently there has been a growing interest in electronic III. OPAMP BIASING SCHEMES
circuits for wide temperature, and therefore, this has been the
As explained in section II, current driving capability and
subject of several recent research efforts [1]-[3]. Operational
small signal transconductance of the CMOS devices are both
amplifiers are the heart of many analog circuits such as
strong functions of temperature. Therefore huge variations in
integrators, gain stages, filters, and analog-to-digital
both small signal (e.g. gm, and unity gain bandwidth) as well
converters. Therefore, the robust performance of many analog
as large signal (e.g. slew rate) of the Opamp are observed as
circuits over wide range of temperature depends on the stable
the temperature changes across a wide range. High resolution
performance of their opamp.
data converters require high performance Opamps especially
The Opamp presented in this paper is part of a very high
at the front end stage. Fast settling behaviour and small
resolution switched-capacitor sigma-delta ADC for
steady-state error are usually required. Adaptive biasing
instrumentation applications. A biasing scheme is proposed
schemes are therefore needed to ensure that the Opamp
that ensures minimal change in both small signal and large
performance is robust versus temperature.
signal characteristics of the opamp. The design technique has
This section describes the two techniques that are
been verified using accurate compact models of CMOS
commonly used for biasing of the Opamps: constant gm and
devices developed at Arizona State University [4]-[5]. The
constant current. Each of these techniques can only guarantee
paper is organized as follows. Section II briefly describes the
minimum variation in either small or large signal parameters.
effect of low temperature on CMOS devices. Section III
A third technique is also mentioned here which is called the
compares the different biasing schemes commonly used for
constant IC (Inversion Coefficient). The constant-IC method
Opamps. A new Slew Rate Enhancement (SRE) technique
balances the variation in small signal and large signal
with the details of its circuit implementation is brought in
parameters. These methods are compared and their drawbacks
section IV. Section V includes the simulation results. The
are discussed in this section.
paper is concluded in section VI.

978-1-4244-7773-9/10/$26.00 ©2010 IEEE 965

A. Constant Gm
One of the most common techniques of biasing is a beta-
multiplier with self start-up circuit. This method of biasing
ensures that the gm of the biased device is independent of the
process, temperature and supply voltage. It can be shown that
the reference current generated by the biasing circuit obeys
the following equation [7]:
(3)
Ideally, for k = 4,
(4)
Therefore, the transconductance depends only on the value
of resistance (R) and is independent of process, supply voltage
and temperature at least to the first order. If the resistor is
made external to the chip, very stable gm characteristics can be
obtained; however, Iref is not independent of temperature and
hence the slew rate degrades significantly as temperature
decreases.
B. Constant current/Constant Slew-Rate (SR)
Constant current is another common biasing technique
where the current and therefore slew rate is kept constant
across the PVT variations. The method aims at keeping the
large signal characteristics intact across any temperature
variation. However, since the g m drops with an increase in
temperature, the opamp needs to be designed to have enough
bandwidth at highest temperature which results in excessive
power consumption at lower temperatures.
C. Constant Inversion Coefficient (IC)
In an attempt to design a biasing circuit that maintains
minimum changes in both small and large signal parameters,
authors in [1] have suggested a biasing approach based on
constant IC (Inversion Coefficient). The results presented in
[1] show smaller variation in slew rate than what constant-gm
method gives and smaller changes in gm than the one in
constant current method. However, despite the low variation,
the bias current needs to be decided based on both slew rate
and/or gm at the worst corners which would not result in
optimal power consumption.
D. Comparison
Figure1 shows the percentage of variation of gm across the
temperature as a function of input device length for both
constant-gm and constant current methods. Obviously the
transconductance variation is much smaller in constant-gm
technique. Figure 1 also shows that in this process, if a
constant-gm technique is used, in order to get the small
variation, device length must be greater than 1.5 times the
minimum length allowed by technology.
Thus, for small signal parameters it is wise to use constant-
gm approach assuming slew-rate requirement can be taken care
of separately. To achieve this independence, a constant-gm
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Figure 1. % variation of Gm with length of the input devices across temp
together with a slew-rate enhancement technique is proposed
here. The slew-rate boosting can help to meet the large signal
specifications without the need for over-designing the Opamp.
In this approach, the power consumption of the Opamp is
decided based only on the small signal specifications. An
auxiliary circuit as explained in the next section would inject
extra current into the load whenever slewing occurs.
IV. SLEW RATE ENHANCEMENT CIRCUIT
Slew rate enhancement techniques have been reported
earlier where a large capacitive load needs to be driven by
Opamp [8]-[11]. Different techniques have been suggested,
for eg. in [8] bias current of the core opamp is increased
during the slewing condition. This method is not desirable as
the entire core amplifier, and not just the output stage has to
handle large currents during slewing. This could impair the
opamp output swing and cause undesired small signal
transients when SRE is activated.
In [9-11] auxiliary branches carry the extra current required
for charging/discharging of the load during slewing and the
core opamp will remain unaffected. The general block
diagram of these methods is shown in figure 2. Both main
amplifier and SRE opamp sense the same input signal. SRE
amplifier then needs to detect the slewing condition and inject
extra current to the output node. The methods are then
different by how the slewing condition is detected and the
response time of the system (i.e. how fast the extra current can
be injected).
In [10] the core opamp has HBT input devices while the
SRE opamp uses CMOS devices. In order to accurately detect
the slew rate condition, the overdrive voltage of these devices
should be matched which makes it impossible when different
devices are used. Apart from using different devices in the
SRE circuit, the method explained in [10] is the same as [9].
Their approaches are being compared to our proposed
technique here.
Figure 3 illustrates the SRE circuit used in [9] and [10]. It
uses an amplifier stage M1-M5 with the condition that I1 < I2
which is critical for its operation. The load devices M1 and M3
are in linear mode of operation. These two conditions keep
SRE devices M6, M7, M8 and M9 off in normal operating
conditions. During slewing, Vout_p and Vout_n are charged (or
discharged) and discharged (or charged) respectively by SRE
devices. The switching operation of these devices can kick- I1
back noise to the input of the SRE Opamp which is also the
input of the main opamp degrading settling performance of M3 M4
the circuit. This is particularly a concern in switched capacitor P_Pulldn P_Pullup N_Pullup
M5 M6 N_Pulldn M12 M13
circuits where large transients are expected. Also, the low gain Vout_P
N_Pullup
of the amplifier stage means that the SRE devices are turned P_Pullup Vout_N
on slowly and hence this would also affect the transient Vin+ M1 M2 Vin- P_Pulldn M10 M11 N_Pulldn
response. I2
M7 I1
Figure 4 shows the schematic of our proposed SRE circuit. M8
The slewing condition is detected by the SRE Opamp which M9 I2
controls the switches in series with the current sources. The
current sources are turned-on and they would assist in either Figure 4. Schematic of the proposed Slew Rate Enhancement technique
pulling up or pulling down the output. The main concern is to
reliably detect the slewing condition. The SRE auxiliary Also, our proposed circuit uses diode connected load
Opamp should be designed such that it starts slewing at the devices [11] and mirrors the signal in current mode. This
same time as the main Opamp does. This goal is achieved by means that the switching in the detection stage is decreased
matching the input devices of main and SRE amplifiers. In the and the kick-back noise is drastically reduced. Unlike the
auxiliary amplifier this condition generates a logic signal to approach used in [11], the output is converted to a logic level
inject extra current when slewing is detected. The layout signal to drive switches M10-M13 in order to source/sink
matching can be ensured by orientation and proximity. The current to the output. Therefore, as it is shown in the next
current sources can be replaced by resistors which simply pull section, using similar sizes for SRE devices, a faster response
the output node towards either rail. can be achieved.

V. SIMULATION RESULTS
The proposed opamp with adaptive biasing scheme and slew
rate enhancement was designed and laid out in 0.18µm Jazz
process. Figure 5 shows the variation in unity-gain-bandwidth
and gm respectively. An off-chip precision resistor of 18kΩ is
used to set the DC biasing point.

Figure 2. Block diagram of core amplifier and auxiliary SRE circuit

VB2
M3 M4
I2 I2
Figure 5. Variation of Gm across the temperature range
M6 M7 M8 M9
Figure 6 shows the transient slew rate of the Opamp before
Vin+ M1 M2 Vin- and after using the auxiliary SRE circuit. The slew rate is
Vout_N
Vout_P improved from 25 V/us to 150 V/us by using the proposed
2I1 M10 M11 M12 M13
technique. The achievable slew rate depends on the sizes of
VB1
M5 the SRE devices i.e. M10-M13.
Figure 7 compares the slew rate enhancement in proposed
Figure 3. Nagaraj slew rate enhancement circuit described in [9] and [10]
technique with the ones suggested in [9] and [10]. With
similar sized SRE devices, using the proposed technique, the
circuit enters small signal settling regime much faster than the

967
circuit shown in Figure3. Both methods show similar steady
state error as it is governed by small signal settling only but it
can be inferred that the proposed circuit can be clocked at a
higher speed. Therefore, the technique shown in this paper
would be more suitable for higher speed switched-capacitor
circuits especially in sigma-delta modulators.
Figure 6. Transient response for 1.5V input at 5MHz driving 30pF load
Figure 7. Comparison of proposed and existing SRE
Figure 8. Layout of the core Opamp with the SRE circuit
Figure 8 shows the layout of the amplifier. The SRE
amplifier is ~25 times smaller in size as compared to the core
amplifier. Therefore, added overhead because of the SRE
circuit is negligible.
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VI. CONCLUSIONS
This paper presents a method of enhancing the slew rate of
an operational amplifier. It was shown that the proposed
technique has a faster settling compared to the prior work. The
proposed method can be used in conjunction with the
constant-gm biasing technique to ensure the robust operation
of Opamp across large temperature variation.
The proposed technique is especially useful for Opamps
driving large capacitive loads. The power consumption would
reduce significantly as the static power is determined by
settling requirement instead of Opamp driving capability. The
hybrid biasing scheme guarantees minimal variation for unity-
gain bandwidth as well as transconductance of the Opamp.
ACKNOWLEDGMENT
This work was supported by Jet Propulsion Lab under
SURP program. The authors would like to thank M. Mojarradi
for his technical support and assistance during this project.
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