A SIMPLE TECHNIQUE TO SIGNIFICANTLY ENHANCE SLEW RATE AND

BANDWIDTH OF ONE-STAGE CMOS OPERATIONAL AMPLIFIERS

Jaime Ramirez-Angulo and Michael Holmes

Klipsch School of Electrical and Computer Engineering, New Mexico State University

ABSTRACT 4Vdd
A simple technique to modify a conventional one-stage
op-amp for operation as a class AB amplifier is discussed.
-I
This technique leads to significant slew rate and
bandwidth enhancement with essentially equal silicon
area and static power dissipation requirements.
Experimental results of test chip prototype in 0.5pm
CMOS technology are presented. Results verify slew rate
and bandwidth enhancement factors of almost one order
1
of magnitude.

1. INTRODUCTION

It is well known that the maximum gain-bandwidth

product of a one stage operational amplifier (Fig. la) is
limited by the intemal pole(s) of the amplifier, mainly, by
those associated to the internal mirror (nodes A and B in
Fig. la). Typically the condition GB < 20pA is used as a
practical design guideline in order to provide enough
phase margin and to ensure stable operation down to unity
gain [11-[2]. Wireless and other battery powered systems
require high GB values, high slew rates, and at the same
time very low static power dissipation. These
requirements are difficult to achieve with class A
configurations. Class AB amplifiers can be used for this
purpose [3]. In this paper a simple modification to the
conventional one stage op-amp is discussed which
transforms it into a very efficient class AB circuit. The
modified circuit is shown in Fig. lb. In this circuit the
active load transistors M3,4 are reconnected to have a
common gate (node C) and matched resistors R1, R2 are +V..

used to connect the gate and drain terminals of M3, M4.

This simple modification, as will be shown below, leads
(bl
Fig. 1 One Stage OTA (a) Conventional Cascode Structure
to essential slew rate and GB improvements. (b) Proposed High Slew Rate Structure

2. ANALYSIS fpA=gm3,4/2XCA where gm3,4 is the small signal

2.1. Conventional op-amp (Circuit of Fig. la):
Fig.la shows a conventional one stage op-amp. We
assume unity gain for all mirrors and matched transistors
M3, M4, M5, M6 and M9 as well as M7, M8, M10. The
internal poles of this op-amp are given approximately by:
transconductance gain of M3,4and C A = C ~is the parasitic
capacitance associated to node A (or B). This is
determined mainly by the gate-source parasitic
capacitances of M3 and M5: CA=Cgs3+Cgs~. The op-amp
open loop gain is given by AOL = gmlKutwhere %, is the
output resistance and gml the small signal
transconductance gain of M1, M2. The output dominant

0-7803-7448-7/02/$17.00 02002 IEEE I1 - 835

pole is given by fpout=1/2n The gain-bandwidth
product is given by GB=gml/2n CL where CL is the load
capacitance. For a given load capacitance the slew rate is
limited by the bias current Ibis and given by: SR=Ibias/ CL.
Ibis is related to the quiescent drain-source saturation
voltage VDS,SATand the transconductance gain factor p of
transistors M3-M6 by the expression Ibi&=p (VDS,SAT)’.
2.2. Analysis of Modified Op-Amp of Fig. lb:
For quiescent (or common mode) operation the drain
currents of all transistors M1-M 10 have equal values (Ibi$
2) while the current IR in resistors R1,2 is zero. The
source-gate voltage of M3,4 is the same as their drain-gate
voltage. For common mode signals these transistors
perform as a low impedance (diode connected) load with
value R L , c1/2gd,4.
~ Upon application of a differential
signal, the signal component (IR) of Id1,2 flows through
reSiStOrS R1,2 (Idl=Ibi,+IR, Id2=Ibis-I~, IR=gml,2Vd)while
the drain currents in M3,4 remain unchanged. The current
IR generates differential complementary voltage changes
at nodes A and B. Given that the common gate of M3,4
(node C) has a constant voltage, the differential signal
impedance at nodes A and B is given by:
Signal voltages at nodes A and B are given by:
The open loop gain of the op-amp of Fig. l b is given by:
The pole at A (B) is given by:
fP A = 1 / 2 ~ RA c ’ A (4)
where:
c ’AzcA/2=Cgs5 (5)
Given that node C is a virtual ground, the parasitic
capacitance at node A (B) does not include the gate-
source capacitance of M3 (M4), and it is reduced by
approximately a factor 2: C’A”CGSS=CA/2.
It can be seen that resistors R1,2 provide class
AB operation to the shell of the op-amp (section formed
by transistors M5-Ml0). The maximum output current is
where A V ~ ~ ~ = I ~ ~ , R represents
~ ~ I ~ ~the
, R ~ , ~ / ~
maximum swing at nodes A and B.
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Remarks on the Modified Op-Amp:
a) By proper selection of R1,2 the maximum output
current can be made essentially larger than the maximum
current of a class A Op-.4mp. From (6) a selection
~ > & leads to 1 0 ~ ~ ->21bias and
V ~ s , s ~ ~ + A v ( j sVDS,SAT
improved slew rate.
b) RAgm determines the open loop gain and GB
enhancement factor.
c) A resistor R between the op-amp output terminal and
CL(Figs, 2a,b) can be used to provide phase lead
compensation. R in combination with CL introduces a
left-half plane zero fi in the op-amp open loop gain at
a frequency fZ=l/RcL. For fZ=fpA the zero cancels the
phase of the intemal op-amp pole and allows to extend
GB even further. The condition for the phase
cancellation is: RCL=C’ARA.
d) The value R1,2 can be used to trade off GB/slew rate
enhancement with phase margin. Implementation of R1,2
with MOS transistors allows a programmable value for
R1,2 and utilization of the same op-amp for different
applications
e) For large values R1,2=ro the op-amp behaves as a
two stage amplifier. R1,2 allow a gradual transition
from a one stage op-amp behavior (for R1,2z1/gm) to
a two stage amplifier (for R1:2=ro). In this last case,
cascoding transistors are not required, and Miller
compensation should be used.
f ) Class AB operation also provides the op-amp with
improved linearity (the analysis is not presented here
for the sake of space). This characteristic is important for
many applications (high resolution D/A converters, linear
OTA-C circuits, etc.). Another attractive feature of the
modified op-amp, related to settling performance, is that
all transistors in the op-amp shell are always on with a
minimum current Ibiad2.
Notice that the presented scheme is especially attractive
since it does not impose additional silicon area (resistors
R1,2 require small size MOS transistors) and/or
additional static power dissipation. The scheme is very
efficient since large dynamic output currents (required for
large SR) only flow in the oip-amp shell (transistors M5-
M10) while the internal section (Ml-M4) has the same
dynamic power dissipation as the conventional op-amp
2.3. Design Example
Consider the op-amp shown in Fig. 2a which was
designed for fabrication in 0.5pm CMOS technology.
PMOS transistors were used to implement programmable
resistors R1,2 that can take values from 1.2 to 12kR by
adjusting the gate voltage VR from -2.5V to -1.OV.
 Vdd
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IR
l
l factor close to 20.
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(b)
Fig. 2 Implementation of High Slew Rate CMOS Op-Amp
(a) Op-amp Intemal Structure @) Voltage Follower
Connection with on Chip Phase Lead Compensating Resistor
Utilization of Ibim=80pA,CL=SpF, and transistors sizes
shown in Fig. 2a, lead to VDS,S~FO. lV, transconductance
gain g,,,=750pAN2 for M3-M6, and g,,,1,2 =375pAN2,
with C G S ~ ,C~s5,6=lpF.
~= A conventional op-amp with the
same bias current and transistor sizes as those of the
modified op-amp is considered for comparison purposes.
The conventional op-amp has: GB=12MHz, fpA=42MHz,
and SR=16 V/pS. By selecting R=8KR (such that g,R=3)
values GB’= 36MHz, SR’=141V/ps and fpA=30MHz
result for the modified op-amp (a series resistor R=400i2
for phase lead compensation was also included). It can be
seen that GB increases by a factor 3 and slew rate by a
factor 8.8. The internal pole is reduced from 42MHz to
30MHz but phase lead compensation allows stable
operation.
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3. SIMULATION AND EXPERIMENTAL RESULTS
3.1. Simulation Results
Fig. 3 shows a comparison of the pulse response of the
op-amp of Fig. 2a in voltage follower configuration (Fig.
2b) and the conventional op-amp (Fig. la) with identical
transistor sizes and Ibi,=80pA. Control voltages VR=-
2.5,-1.5,-1 were used for the simulations Fig. 4 shows a
comparison of the frequency response with the same
control voltages. OSpm CMOS technology parameters
and transistor sizes of Figs. 1 and 2 were used for the
simulations. It can be seen that the bandwidth increases
from 1.5MHz to 8.35MHz Slew rate enhancement is a
3.1. Experimental Results
A test chip prototype including a conventional and a
modified op-amp was fabricated in 0.5pm CMOS
(MOSIS) technology (Fig. 5). The op-amp had
dimensions of approximately 300x 150pm2. Experimental
values for GB and SR (with I,im=80pA, CL=SpF, VDD=-
VSS=2.5V, VR=-2.5v) showed a factor 3 improvement
for both SR and GB. The modified op-amp had
experimental values GB’=20MHz and SR’=11V/pS while
the conventional op-amp had experimental values
GB=7MHz and SR=3.5V/pS.
4. CONCLUSIONS
A simple scheme to improve slew rate and gain-
bandwidth of a one stage op-amp was presented. The
scheme was verified experimentally and it is especially
attractive since it requires no additional silicon area andor
power dissipation. It allows wide range programming of
the op-amp characteristics, and due to this advantage, it is
believed it can find widespread utilization.
5. ACKNOWLEDGMENTS
The authors would like to thank Texas Instruments Inc.
and NASNISE for funding of this research project.
6. REFERENCES
[I] B. Razhavi, Design of Analog CMOS Integrated Circuits,
McGraw-HiN, New York, pp. 303,2000.
[2] K.R. Laker and W.C. Sansen, Design of Analog Integrated
Circuits and Systems, McGraw-Hill, New York, 1994.
[3] K. de Langen, J.H. Huijsing , “Compact Low-Voltage
Power-Efficient Operational Amplifier Cells for VLSI,” IEEE J.
0fSolidSt. Circts., Vol. 33, NO. IO, Oct. 1998, pp.. 1482-1496.
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Fig. 4 Frequency response comparison for conventional and modified op-amp: Top trace: Frequency response of
conventional op-amp, Middle trace: Frequency response of modified op-amp for three values of VR, Bottom trace:
comparison of responses of conventional and new op-amp.

Fig. 5 Microphotograph of fabricated op-amps: Approximate dimensions are 14Ox300pm.

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