Address Decoding and Memory Mapping: Memory address decoding is nothing but to assign an address for each location in the memory chip. The data stored in the memory is accessed by specifying its address. Memory address can be decoded in two ways: i) Absolute or Fully decoding and ii) Linear Select or Partial decoding ‘There are many advantages in absolute address decoding, i) Bach memory location has only one address, there is no duplication in the address, ) Memory can be placed contiguously in the address space of the microprocessor iii) Future expansion can be made easily without disturbing the existing circuitry There are few disadvantages in this method i) Extra decoders are necessary ii) Some delay will be produced by these extra decoders. The main advantage of linear select decoding is its simplified decoding circuit. This reduces the hardware design cost. But there are many disadvantages in this decoding. {) Multiple addresses are provided for the same location ii) Complete memory space of the microprocessor is not efficiently used iii) Adding or interfacing ICs with already existing circuitry is difficult. Absolute Address Decoding: The 8085 microprocessor has 16 address lines. Therefore it can access 2'® locations in the physical memory. If all these lines are connected to a single memory device, it will decode these 16 address lines internally and produces 216 different addresses from (0000H to FFFFH so that cach location in the memory will have a unique address AL Ay | Hex Aes 0-0} owl ° ‘AwAu Ay Ay [Au Aw Ar Ae [Ar As As Ay [Ay Ap oo 0 Of 0-0 0 OFO00 GTO 0 000 0/000 0/000 clo 001) comm 000 0/000 0/000 a\0 01 0| com Fig. 1.6 Memory Address Above diagram shows the various memory addresses used in Microprocessor. If more than one chips are used then some logic must be used to select one particular chip. This is done with the help of decoder, TALS138 address decoder to generate the chip select signals for eachmemory block. In thisdecoder when the address lines A13, Al4 and A1S are 000, theoutput fineYO will be activated as shown in Fig 1.7. This in turn selects the firstmemory block. Similarly when these lines are 0OL (C20, B=0 and A=1) YI will beactivated and the second memory block will be selected. Block Select 7aisi3s ee Fig 1.7: Memory block decoder In this type of memory interfacing, all the address lines (AO to AIS) have beenused. Each location in the memory will have a single address. This type of addressdecoding is called as absolute or fully decoded addressing. — A, sal % a a) uo jon [jan a th oe ete FO efor [Oot ou on oe Li 00 00 a—_16 3 Memory 1 Memory 2 Memory 1 Memory 2 Fig. 1.8: Role of CS signalAccording to the value of Ao and Al , any one register will be selected and to select one memory chip we need one chip select signal CS signal as shown in the next diagram. If CS" is *O’memory 1 will be selected else memory2 will be selected. And the complete picture of the interfacing is shown below. A1S-A8. al ven - MEMW Fig. 1.9: The complete interfacing diagram The simple view of RAM is that it is made up of registers that are made up of flip-flops (or ‘memory elements). The number of flip-flops in a “memory register” determines the size of the memory wordROM on the other hand uses diodes instead of the flip-flops to permanently hold the information, For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do the following: Select the right memory chip (using part of the address bus). Identify the memory location (using the rest of the address bus). Access the data (using the data bus).aan fee) 21 |2 | Selhellal/2lalele Litt ttt t Fig. 1.10 Memory Interface Diagram ‘Tri-State Buffers: An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states: Logic 0, logie1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely. This circuit has two inputs and one output. The first input behaves like the normal input for the circuit. The second input is an “enable”. If itis set high, the output follows the proper circuit behaviour. If it is set low, the output looks like a wire connected to nothing. Input /Output Devices: Pavallel Interfacing: There are two ways to interface 8085 with /O devices in parallel data transfer mode: Memory Mapped IO and {0 mapped IO. Memory mapped VO: It considers them like any other memory location. They are assigned a 16- bit address within the address range of the 8085.The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory. WO mapped VO: It treats them separately from memory: VO devices are assigned a “port number” within the 8-bit address range of OOH to FFE. The user in this case would access these devices using the IN and OUT instructions onlyTO mapped IO V/s Memory Mapped 10: Memory Mapped 0 10 mapped 10 + 10 reated as memory. + 16-bit addres ng. + More Decoder Hardware. + Can address 2!°=64K locations. + Less memory is available. + Memory Instructions are used + Memory control signals are used. + Arithmetic and logic operations can be Performed on data. + Data transfer byw register and 10, + 10 is treated 10. + 8 bitaddressing. + Less Decoder Hardware + Can address 2°=256 locations. + Whole memory address space is available. + Special Instructions are used like IN, OUT. + Special control signals are used. + Arithmetic and logic operations cannot be Performed on data. + Data transfer bAw accumulator and 10.