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A Novel Configuration for dc to ac Inverter

Utilizing Buck Converter
M. Jahanmahin, A. Hajihosseinlu, A. Tavakoli, S .mansourpour, and E. Afjei


Abstract-- A dc to ac inverter is used to change the input
voltage to a desired alternative voltage which has sinusoidal
waveform with controllable magnitude and frequency. This
paper proposes a novel configuration for dc to ac inverter with
only two switches which controlled by new method. In this
technique, the gate pulse contains several states which each
state based on an AC PWM method. This new configuration
based on a dc to dc Buck converter. This paper provides the
analysis and simulation results. Fig. 1. The new inverter circuit

Index Terms-- dc-ac inverter, dc-dc Buck converter, This circuit composed an inductor (i.e. L), two capacitors
sinusoidal waveform. (i.e. C1, C2), and two switches (i.e. S1 and S2) which can be
divided in to two parts. The first part of this circuit contains
I. INTRODUCTION
input dc voltage source, S1, S2 switches, L inductor and C1

I n past decades, semiconductor power conversion circuit

such as PWM inverters and PWM rectifiers are very
important and essential technology for the energy storage
capacitor. This part is similar to a dc-dc Buck converter.
Second part includes C2 capacitor works as a filter for
cancellation of dc component which is in series with the load.
power plants, telecommunication system and electric vehicle, In experimental cases these ideal switches can be replaced by
because more high quality power source, high-speed response a power transistor which has an inverse parallel diode. In
and control ability are required for them [1],[2]. In order to order to analyze this particular inverter, it is necessary to look
attain these requirements, high-frequency switching of power at the dc-dc Buck converter first. In next section the
semiconductor devices such as IGBT, and FET are acceptable performance of a dc-dc Buck is briefly considered.
and put into practical use in the industry. However, high
frequency switching includes some significant difficulties
such as increase in the switching power losses, generation of B. Review of the dc-dc Buck converter analysis
leak current due to high rate of voltage change with respect to A general topology of a dc-dc Buck converter is shown in
time and electrical insulation break down due to high rate of Fig. 2 and its gate pulse is shown in Fig. 3.
current change with respect to time. The resonant AC link
snubber assisted ZVS-PWM inverter is developed in [3] and
one of these soft-switching inverters that lossless capacitive
snubber commutation mode is effectively available can reduce
the common mode noise as compared with three-phase
conventional hard-switching inverter [4],[5].
Fig. 2. The dc-dc Buck converter[6-8]

II. TECHNICAL WORK PREPARATION

A. The new dc to ac inverter circuit

The new inverter is shown as in Fig. 1.
Fig.3. the gate pulse in Buck converter

D is duty cycle and Ts is the period of switching. When

0 < t < DTs , switch is turned on and inductor is charging up.
The voltage drop on the inductor is equal to (Vin-Vout).
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When DTs < t < Ts, switch is turned off and inductor is For example V1g (t) and V2g (t) are sequences as shown in
discharging. The voltage drop on inductors is (-Vout). Hence; Fig. 5 and Fig. 6.
(Vin – Vout) DTs + (0 – Vout) (1 – D)Ts = 0 (1)
Therefore the expression for the input voltage (Vin) and the
average of output voltage (Vout) can be summarized as:
Vout = DVin (2)
Fig. 5. The waveform of V1g (t)
C. Generation of the gate Pulses
S1 and S2 are complement switches. This means when any
switch is turned on/off, another switch is turned off/on.
The duty cycle produced for the Buck converter is not
constant and varies according to the desired output voltage
and frequency. So: Fig. 6. The waveform of V2g (t)

Vg (t) = Vg (t + KT) (3)

Now G(t) can be readily obtained. Fig. 7 shows G(t) having
Where, K is an integer number. In order to have a better
m = 6, n = 1.
description of the gate voltage, an intermediate function is
defined as G(t) which is;
(4)
Where, u(t) is unit step function. Now, the gate voltage
using G(t) for time 0 < t < T/2 is expressed as;
Vg (t) = G(t) (5) Fig. 7. The waveform of G(t) with m = 6, n = 1.
While for the time T/2 < t < T, is:
Vg (t) = G(T - t) (6) For one whole period (T) of the gate voltage, Vg (t) for
Vig (t) contains n pulses where each pulse turns on S1 m = 3, n =1 is shown in Fig. 8.
switch for DiTs seconds and turns it off for (1-Di)Ts seconds.
During this time the gate pulses to the main switch has the
following form:
(7)
The number of pulses (n) in Vig (t), must be big enough
(n > 5) such that the voltage drop on C1 capacitor (VC1) Fig. 8. One cycle of Vg (t) with m = 3, n = 1.
achieves a stable condition. Di is the variable duty cycle and is
updated after every n pulses as: In experimental cases, these pulses can be made simply by
Di = Di-1 + d (8) a microprocessor such as AVR or can be provide by PWM
method.
Where; i = 2, 3…, m
D1 = Dmin (9)
Dmin and d are two parameters which selects by user to D. Analysis of new dc to ac inverter
determine the magnitude peak of ac output voltage. Usually d As known, a sinusoidal waveform with T period can
is a smaller than Dmin and it superimposes onto the duty cycle divided into two parts with the same duration (T/2). First part
every n pulses until reaches to its maximum (Dmax).This state started when waveform is in its minimum and ends when it
occurs when i = m, hence: reaches its maximum. In this time the waveform is strictly in
ascending order. When the first part is finished, second part
Dm = Dmax (10)
starts and continues until the waveform reach to its
Description of G(t) is based on Vig (t) which is shown in
minimum. In this duration of time this part the waveform is
Fig. 4.
strictly in descending order.
This section contains two parts. First part studies first half
cycle (i.e. 0 < t < T/2) and second part analyzed the second
half cycle (i.e. T/2 < t < T). At this point each part is
explained briefly in the following manner.
Fig. 4. The waveform of Vig (t)

1) First part
As seen in Fig.1, Zth can be expressed as:
Zth (S) = RLoad + (1/C2S) (11)
Assume Zth only has real part and its imaginary part is
zero. Therefore Zth is equal Rth. Under this assumption, the
topology of new dc-ac inverter is similar to the dc-dc Buck
converter; hence according (2), the voltage of C1 capacitor
(VC1), in each time is equal to DVdc .
If the switching frequency is high enough and also
ignoring the output ripple voltage, for a fixed duty cycle
(i.e. Di-1) the dc voltage source with magnitude Vdc and the
switches in Fig. 1, can be modeled by a dc voltage source with
magnitude Di-1Vdc. In steady state conditions, L is short
circuited and its current is IL1(0-) which is given in (12); C1
capacitor is open circuited and its voltage is VC1(0-) is given
in (13). It is assumed that this mode occurs at t= 0-. Fig. 9
shows this circuit under above condition.
Fig. 9. The new inverter at t = 0-
In Fig. 9 it is clear that:
IL (0-) = Di-1Vdc / Rth (12)
And:
VC1(0-) = Di-1Vdc (13)
When the gate voltage changes from V(i-1)g (t) to Vig (t),
namely t = 0+, the duty cycle change to Di and the magnitude
of modeled dc voltage source switches to DiVdc ; L and C1 are
charging up. Fig. 10 shows this circuit at t = 0+.
Fig. 10. The new inverter at t = 0+
Initial value of L and C1 are given in (12) & (13). Assume
L > 4C1Rth2, hence VC1 (t) can be expressed as:
VC1 (t) = V1 exp (λ1 t) + V2 exp (λ2 t) + Di Vdc (14)
In this equation, λ1 and λ2 are the corresponding
characteristic equation roots, given in below:
(15)
3
(16)
V1 and V2 determine with Initial values of L and C1 at
t = 0+. So:
(17)
(18)
These equations show the duration for mnT s second which
the gate voltage is G(t) and show how VC1(t) is charging up
and trying to reach DiVdc.
In order to draw the waveform, VC1(t) one needs to have
some knowledge about its concavity. Turning point in this
equation is the root of Second order derivative of the VC1(t)
equation and is calculated to be;
(19)
If t < tturn the concavity is positive and if t > t turn it is
negative.
In an ideal sinusoidal waveform the concavity is positive
when 0 < t < T/4 and is negative when T/4 < t < T/2. This
means that turning point is at t = T/4.Therefore if m and
n parameters are determined such that this point is
placed at 0.5nmTs. This point is obtained by the following
manner;
(20)
The waveform of VC1(t) will be almost similar to a
sinusoidal waveform.
Fig. 11 shows an ideal half cycle sinusoidal waveform and
the resulting VC1(t). In this figure the sinusoidal waveform is
shown by dashed line and only plot for first half cycle while
the VC1(t) is rising from its minimum to its maximum. It is
noticeable key that this voltage has dc component hence its
peak-peak voltage is 6v and its frequency is 50Hz.
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The peak to peak magnitude of this voltage (Vp-p) and its

frequency (f) are given at below:
Vp-p = (Dmax – Dmin)Vdc (22)
f = 1/T = 1 / (2mnTs) (23)
The relation between m with d is:

(24)
Fig. 11. First half cycle of VC1(t)

2) Second Part This new and novel inverter is simulated by MATLAB

In this part (8) replaced by (21): with fs = 40 kHz, n = 20, m = 20, d = 0.032, Vdc = 10v,
Di = Di-1 - d (21) Dmax = 0.8 and Dmin = 0.2. The output voltage expected to be a
Now V1 and V2 are changed to –V1 and –V2 sequentially. sinusoidal waveform with Vp-p = 6v and f = 50 Hz. This
Thus VC1(t) waveform has a symmetry at t = T/2. Fig. 12 voltage is shown in Fig. 14.
shows comparison between an ideal sinusoidal waveform with
VC1(t) for this condition. This figure is only plot for second
half cycle while the VC1(t) is decreasing from its maximum to
its minimum.

Fig. 14. The output voltage

Vout(t) is analyzed using MATLAB FFT tools and its

harmonics are derived and shown in Fig. 15.

FFT window: 22 of 38 cycles of selected signal

2
Fig. 12. Second half cycle of VC1(t)
0

Fig. 13 is shown voltage of C1 capacitor for a perfect -2

cycle. 0.25 0.3 0.35 0.4 0.45 0.5

Time (s)
0.55 0.6 0.65

Fundamental (50Hz) = 0.3573 , THD= 8.65%

2.5
Mag (% of Fundamental)

1.5

0.5

0
0 20 40 60 80 100
Frequency (Hz)

Fig. 13. A perfect cycle of VC1(t) Fig. 15. Harmonics of the output voltage

E. Deduction and simulation results Fundamental frequency of Vout(t) is 50Hz and total
VC1(t) obtained by this type of modulation is now similar to harmonic distortion (THD) is 8.65%.
a sinusoidal waveform which summoned with a dc voltage.
C2 capacitor is placed in the circuit to cancel the dc output
voltage. This voltage is strongly similar to a sinusoidal
waveform.

F. DC Cancellation
In the presentation analysis for the new inverter, it is
assumed the Zth(s) which is given at (13) only has real part
and its imaginary part is zero. For output frequency, Zth(jω)
can be summarized as:
Zth(jω) = Rth + jXth (25)
C2 value must how determine that Xth be enough smaller than
Rth. It is realized by follow equation:
C2 >> 1/Rthω (26)
G. Conclusion
In this paper a new and novel Buck converter is set proper
PWM to achieve ac output voltage. The process of obtaining
the function for the main transistor switching has been
developed. Using this function a Buck converter has been
changed to act as an inverter which has much less electronic
power devices. This circuit has been simulated by MATLAB
and the validity of the circuit has been successfully verified.
III. REFERENCES
[1] R. W. De Doncker, I. P. Lyons, “The Auxiliary Resonant Commutated
Pole Converter’’ Conference Records of lEEE Industry Applications
Society Annual Meeting, vol. 2, pp. 1228-1235, October, 1990.
[2] W. McMurray, “Resonant snubbers with auxiliary switches”, IEEE Trans.
on Ind. Appl. vol. 29, no. 2, pp. 355-362, Mar. /Apr., 1993.
[3] J. S. Lai, “Practical Design Methodology of Auxiliary Resonant Snubber
Inverter”, Proceedings of IEEE Power Electronics Specialists Conference,
vol. 2, pp. 432437, June 1996.
[4] K. T. Chau, J. M. Yao, C. C. Chan, “A new soft-switching vector control
approach for resonant snubber inverter”, International Journal of
Electronics, vol. 86, no. I , pp. 101-115, January 1999.
[5] Seong-Ryong Lee, “A Control Strategy of the Three-phase Bridge-type
ZVT Inverter for AC Motor Drives”, Proceedings of ICPE, pp. 529-534,
October 1998.
[6] Rashid M. H. “Power Electronics: Circuits, Devices andApplications”
Second edition, Prentice-Hall, USA, 1993.
[7] Mohan N., Undeland T. M. and Robbins W. P. “PowerElectronics:
Converters, Applications and Design” JohnWiley & Sons, New York,
1995.
[8] R. Erickson, Fundamentals of Power Electronics. New York: Chapman &
Hall, 1997, ch. 9 & 11.
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IV. Biographies
Mohamad Jahanmahin was born in jahrom,
Iran, in 1985. He received the B.S degree in
electrical engineering from Najafabad Islamic
University, Esfahan, Iran, at 2008. He is currently
pursuing the M.S degree in electrical engineering
at Shahid Beheshti University, Tehran, Iran and is
assistance and teacher assistant of Professor
Ebrahim Afjei. He has been working in power
electronics laboratories. His research interests are
power electronics and it’s applications in power
system and drives.
Email: Jahan_mahin@yahoo.com
Amin Hajihosseinlu was born in Bandarabbas,
Iran, in 1990. He is currently pursuing the B.S
degree in electrical engineering at Shahid Beheshti
University, Tehran, Iran. He has been research
assistant and teacher assistant of Professor Ebrahim
Afjei and has been working in power electronics
laboratories. His research interests are power
electronics and it’s applications in power system,
hybrid electric vehicles, digital control applied to
Power Electronics, renewable-energy systems and
electrical machines and drives.
Email: hajihoseinloo@yahoo.com
Ali Tavakoli Khorasagani was born in
Isfahan, Iran, in 1985. He received the B.S degree
in electrical engineering from Najafabad Islamic
University, Esfahan, Iran, at 2008. His research
interests are Design of control systems, Analysis of
sound and power electronics.
Email: mr.alitavakoli@yahoo.com
Sajad mansourpour was born in Bonab, Iran He
received the bachelor degree in electronic
engineering from the University of Shahid Beheshti,
Tehran, Iran. His research interests are power
electronics, renewable energy, machinary and motor
drive.
Email: s.mansourpour@mail.sbu.ac.ir
Ebrahim S. Afjei received the B.S. degree in
electrical engineering from the University of Texas
in 1984, the M.S. degree in electrical engineering
from the University of Texas in 1986, and the
Ph.D. degree from New Mexico State University,
Las Cruces, in 1991. He is currently a Professor in
the Department of Electrical Engineering, Shahid
Beheshti University, Tehran, Iran. His research
interest is in switched reluctance motor drives and
power electronics.
Email: Afjei@yahoo.com