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VLSI DESIGN
UNIT-I CMOS TECHNOLOGY
MOS TRANSISTOR - Introduction
Si Si Si
 Si semiconductor Forms basic material
Si Si Si
for Large Class of ICs
Si Si Si

 MOS [Metal-Oxide Semiconductor]


Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si
Structure is created by
Superimposing several Layer of Si Si Si Si Si Si

Conducting &
Insulating materials To
Form a structure like
Sandwich

Manufactured by using a series


of chemical Processing
steps involves
i. Oxidation of silicon
ii. Diffusion of impurities
iii. Deposition
iv. Etching of aluminum (or)
other materials ……

on a Single crystal of silicon,


As a “Thin flat circular wafers”
around 15 – 30 cm in dia.
 CMOS technology provides 2 types of transistors

N-type transistor (nMOS)


P-type transistor (pMOS)
 Transistor operation based on electric fields

So devices are also called


Metal Oxide Semiconductor Field Effect Transistors
[MOSFET] (Or) simply FETs.
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SYMBOLS

nMOS pMOS
CROSS – SECTION:

 P+ regions indicates heavily doped p-type Silicon

 n+ regions indicates heavily doped n-type Silicon

 Each transistor consists of Stack of the conducting gate,


Insulating layer of silicon dioxide (SiO2) or glass,
Silicon Wafer (called substrate (or) body (or) bulk)
 Gate of Early transistors

Built from metal

So stack was called


Source Gate Drain Metal Oxide Semiconductor (or) MOS
Polysilicon
SiO2

Now
n+ n+ Gate is typically formed
p bulk Si from
Polycrystalline silicon POLYSILICON
 nMOS transistor:

Build with a p-type Body


& regions of
n-type semiconductor adjacent to gate
Called Source (or) Drain

Physically equivalent
& interchangeable.
 Body typically Grounded.
 pMOS transistor:

P-type Source & Drain regions with n-type Body


 Gate: Control I/P

Affects flow of ct. between Source & Drain.


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MOS TRANSISTOR THEORY :

 Majority Carrier device (control conduction) Conducting channel S D

Controlled by 'G' potential.


 N-Mos majority carriers: Electrons

 P-Mos majority carriers: Holes

 Consider,
An Isolated MOS structure NO D (or) S
Only Gate & Body

 Top layer: good conductor (Gate)

Early transistor uses: Matel gate

Modern transistor uses: POLYSILICON


(Silicon formed from many small crystals)
 Middle layer: Very thin insulating film

SiO2 Gate Oxide

 Bottom layer: Doped silicon body (grounded)

Body: (p – type : carriers : Holes) Grounded

Voltage applied Gate

 Gate oxide: Good insulator ' 0' ct. flows


From G body .

 A (-)ve voltage [vg < 0 ] applied G


Result:
(-) ve charge on 'G' .

Mobile (+) vely charged holes


Attracted to the region
below “G”
called
ACCUMULATION MODE.
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polysilicon gate
Vg < 0
silicon dioxide insulator
+
- p-type body Accumulation
( Vgs<< Vt )
(a)

0 < V g < Vt

+
depletion region Depletion
-

( Vgs Vt )
(b)

V g > Vt
+
inversion region Inversion
- depletion region

(Vgs > Vt)


(c)

 A Low (+) ve voltage (0< Vg < Vt) 'G'

Result: Some (+) ve charge on 'G'

holes in body are repelled from region directly below gate .

Result: Depletion region


below the Gate.
Called DEPLETION MODE.

 Vg > Vt Higher (+) ve potential [exceeding threshold Voltage, Vt]


Applied 'G'

Attracts more (+) ve charge 'G'

Holes are repelled further &


Small no. of electrons in the body attracted region
under the gate.

This conductive layer OR


“INVERSION LAYER”
(Electrons in p-type body)
& It is called INVERSION MODE.

 THRESHOLD VOLTAGE: ( Usually (+) ve )

Depends on no. of dopants in the body


& Thickness, tox of the oxide.
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 Consider, Source Gate Drain


Polysilicon
N-Mos transistor :
SiO2
Body: generally grounded
0
n+ n+
S D
p bulk Si

So
pn junction of S & D Body RB.

i) If Gate also ground


no current flows throw RB pn junction

Transistor = OFF
ii) If G volt Creates Electric Field
&
Source Gate Drain
Polysilicon Starts to attract free Electrons
SiO2 underside of Si - SiO2 interface………….

1
n+ n+
S D
p bulk Si

iii) If G volt Enough


Electrons outnumber the holes
&
Forms thin region Under the gate called “channel”.
(INVERSION LAYER)

It forms conducting path of electron


carriers from S D

Transistor = ON.
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 Consider
pMOS transistor

Body: high potential


Gate: high potential

Pn junctions of S & D RB

No current flows
Source Gate Drain Transistor = OFF.
Polysilicon
SiO2

p+ p+

n bulk Si

 When,
Gate = V

(+) ve charges are attracted to the underside Of


Si – SiO2 interface.

 Suff. Low G volt


Inverse the channel &
conducting path of (+) ve carries
formed from S D

Transistor = ON .
NOTE :

High pot. VDD (or) power Logic ‘1’ 5v (or) occasionally Higher

Recently 3.3v, 2.5v, 1.8v, 1.5v…..used


g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Low pot Vss (or) GND Logic '0' 0v


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nMOS DEVICE BEHAVIOR UNDER THE INFLUENCE OF DIFFERENT TERMINAL VOLTAGES


 Consider,
nMOS transistor with a Grounded Source
&
p-type body

[Tr. consists of Mos stack between 2 n-type regions

Called 'S'&'D']
Cut off : no channel ( Ids = 0)
i] Vgs < Vt :

S & D has Free electrons


but No Free electrons.
Body has free holes

Jn. between body & S(or)D RB

Ids = 0
This mode of operation is called
Cut Off.
ii] Vgs>Vt:
Inversion region of electrons (majority carriers) called Channel .

It connects the S & D


creates conducting path.
 No. of carriers & conductivity for in Vgs
 Potential diff. between
drain & source Vds = Vgs – Vgd

 If , Vds = 0; [i.e. Vgs = Vgd]

Vgs > Vt
Vgd = Vgs
o No electric field tending to push ct.
+ g +
- -
From D S.
s d
n+ n+ Vds = 0
 When a small (+)ve potential is applied (Vds)
p-type body Ids flows Channel
b from D S.
Vgs > Vt
+ g +
Vgs > Vgd > Vt This mode of Operation is
- - Ids Linear, Resistive and Unsaturated.
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
Ct. with both Drain Voltage
& Gate voltage.
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 If Vds sufficiently large


Vgd < Vt

Channel no longer inverted near drain


& becomes Pinched Off.

Conduction carried Influence of (+)ve


drain voltage (Vds)

As electrons reach End of the channel


Vgs > Vt
g Vgd < Vt
+ +
- - Injected Depletion region
s d Ids

n+ n+
near the drain
Vds > Vgs-Vt
&
p-type body
b
Accelerated drain.

 Above this Vds Ids Controlled


only by
Gate voltage
&
Ceases to be
influenced by drain.

This mode is called


SATURATION.
Note: nMOS Tr. has 3 modes of operation:

i] If Vgs < Vt Tr. cuts off & No ct. flows

ii] If Vgs > Vt & Vds small Tr. acts as a linear


resistor

Ct. Id  Vds.

iii] If Vgs > Vt & Vds Large Transistor acts as


Ct. source

Ct. flow independent of Vds.


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IDEAL I – V CHARACTERISTICS
 Mos Tr. 3 regions of operation:-
i] Cut off (or) Sub threshold region
ii] Linear (or) Non saturation region
iii] Saturation region

 1st order model (ideal Shockley)

Relates ct & voltage (I-V) for nmos Tr. in 3 regions.

 In cut off :- (Vgs < Vt) no channel


& '0' ct. flows
From D S.

 In linear & sat region Gate attracts carriers (electrons)

To form channel .

Electrons drift from S D

 Field between these regions.


NOTE:
 We can compute current
If w.k. amt. of charge in the Channel & Rate at which it moves.
 W.k.t,
Charge on each plate of capacitor Q = CV

Charge in the channel Q Channel = Cg (Vgc-Vt)

Where,
Cg Capacitance of gate.
Vgc Amt. of voltage attracting charge
to the Channel beyond the min.
required to Invert from p to n.
 Gate voltage reference to the channel

It is not grounded. gate


 If Source is at, Vs & Drain is at Vd +
Vg
+
source Vgs Cg Vgd drain
Vs - - Vd
channel
Average, Vg = (Vs + Vd) / 2 n+ -
Vds
+ n+

VC = (Vs +Vds )/ 2 p-type body


Mean diff between G &
channel pot , Vgc = Vgs – (Vds/2)
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Avg G channel potential , Vgc = (Vgs+Vgd)/2

Vgc = Vgs- Vds/2


 We can model gate as a || plate capacitor with Capacitance  Area over thickness.
el

 If G Length, L
Width, W &
Oxide thickness, tox.
 Then, capacitance, Cg =ox WL
tox
Permittivity, ox= 3.90
polysilicon
gate Permittivity of free space (8.85x10-14 f/cm)
W
ox
tox
tox cox capacitance/unit area of gate oxide
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body  Tr. Dimensions In cut off : Vds < Vt ; Ids = 0

 Concept of MOS Tr. : Use of a voltage on 'G' to induce a charge


in the channel between S & D.

 It may then be caused to move from S D


Under the influence of an Vds.

 Since Charge induce is dependent on Vgs & Vds,

Ids dependent on Vgs & Vds


 Ids = -Isd = Charge induce in channel (QC)
Electron transit Time (Tsd)
Time Required for carriers to cross the channel

o Transit time [Tsd] = Length of channel (L)


Velocity (V)

o Carrier velocity, V= µEds


µ = (650 cm2/v sec) Electron (or)
(840 cm2/v sec) Hole Mobility (surface)
Eds = Electric field [D S]

Eds= Vds / L V = µ Vds/L


Tsd = L2 / µVds
 Charge induced in channel due to Gate voltage Voltage diff. betn
Gate & channel ,Vgs
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i]Assume (Vds < Vdsat) : Gate is not saturated [Vgs > Vt] [Vds < Vgs – Vt]

 In this region voltage along the channel varies linearly with distance, x from
the source due to IR drop in channel.
 Charge/unit area = Eg 
Permittivity
r o
 Induce charge, Qc = Eg  WL

Average Electric field (G channel)


 Now, Eg = [(Vgs-Vt) – Vds/2]
tox Avg. value

oxide thickness

WL (Vgs-Vt) – Vds/2


QC
tox

WL (Vgs – Vt) – Vds/2


tox
Ids
L2 / µVds
QC

WL µVds (Vgs-Vt) – Vds/2


tox L2

WL µVds (Vgs – Vt) –Vds/2


tox L2

o µW (Vgs –Vt) –Vds/2 . Vds


tox L

Ids K(W/L) (Vgs –Vt)Vds – Vds2


2
 In the Non-saturated (or) Resistive region: (Where, Vds < Vgs –Vt )
K = oxµ/tox ; &
With W/L β= K.W/L

 Therefore Ids β (Vgs –Vt)Vds – Vds2


2
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 Gate – channel capacitance ,


Cg = oxWL (||el plate) &
tox
K = C gµ &
WL
β =(Cgµ/WL) (W/L)
β =Cgµ/L2
So that,
Ids = Cgµ (Vgs –Vt)Vds – Vds2
L2 2

For convenient use,


Gate capacitance/unit area , Cox = Cg/WL
Ids = Coxµ W (Vgs –Vt)Vds – Vds2
L 2

 Describes linear region of operation for Vds > Vt

But Vds relatively small,

It is called LINEAR (or) Resistive.


 Because Vds /2 < < Vgs – Vt.

Ids almost linearly with Vds just like an Ideal resistor.

ii] Gate Saturated [Vds >Vds (sat) = Vgs-Vt]

At this pt. IR drop in the channel = Effective G Channel voltage at


drain.
& We may assume,
Ct. remains fairly constant
As Vds further .
2
Ids = K. W/L (Vgs – Vt)
2 (or) Ids = (β/2) . (Vgs –Vt) 2
(or)
Ids = (Cgµ/2L2 ) (Vgs – Vt) 2 2
(or) Ids = Coxµ W (Vgs –Vt)
2L
 This is the Expression for both Enhancement & depletion Mode devices.
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nMOS I-V Summary


 0 Vgs  Vt cutoff


I ds    Vgs  Vt  ds Vds Vds  Vdsat
V
linear
 
2
 
 t
2
 V gs  V Vds  Vdsat saturation
2

Ids (A)
400

Vgs = 1.8
300

Vgs = 1.5
200

Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0 Vds
0 0.3 0.6 0.9 1.2 1.5 1.8

Vgs (-) ve (Depletion mode Tr.)


Vgs (+) ve (Enhancement mode Tr.)

I – V Characteristics of ideal nMOS transistor

 We will be using a 0.6 m process for project


– From AMI Semiconductor
– t = 100 Å
ox
 = 350 cm /V*s
2

– Vt = 0.7 V

 Plot I vs. V
ds ds
– V = 0, 1, 2, 3, 4, 5
gs
– Use W/L = 4/2 
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C – V CHARACTERISTICS
I. Simple Mos - capacitance models
II. Detailed Mos - gate capacitance model
III. Detailed Mos - diffusion capacitance model

 Each terminal of an MOS Tr. has capacitance to the other Terminal .

In general these capacitances are


nonlinear & Voltage Dependent [C – V].

 However, they can be approximated as simple capacitors


When their behavior is averaged across the switching
Voltage of a logic gate.

i] Simple MOS capacitance models:-

 Gate of an Mos Tr. Good capacitor,

Its cap. necessary to attract charge To invert the Channel.

So high gate capacitance


is required to obtain high Ids.
Cgs = Cox WL (parallel plate)

Capacitor is a 2 terminal device

When Tr. = ON

Channel extends from the source. (Reaches drain if Tr; unsaturated)

So,
Gate capacitance terminating at the source
&
Thus called as capacitance Cgs.
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 Most Trs. used in logic are of Min. Manufacturable Length

Results Greatest Speed &


Lowest Power Consumption.

 With this min 'L' as a constant for a particular process,


Cg = Cper micron .W

Where,
Cper micron = Cox L = (ox/tox). L
 If we develop a more advanced manufacturing process in which
“both channel length &
oxide thickness” are reduced by

same factor,
Cper micron remains uncharged.
[1.5 - 2 fF/µm]
 In addition to the Gate,
Source & Drain also have capacitance .

These caps. not fundamental to the


operation of the device.

But impact to circuit performances & hence


are called Parasitic Capacitor.

Arises from the RB p-n junction


betn the S (or) D diffusion
& Body Hence are also called
“Diffusion (or) Depletion Capacitance”.
( Csb & Cdb).

 Size of these Jns.


Depends on the
i] Area & perimeter of the source & drain diffusion
ii] Depth of the diffusion
iii] Doping levels
iv] Voltage

 As diffusion has both High Capacitance & High Resistance

It is generally made as small as possible in the layout.


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ii] Detailed “MOS Gate” Capacitance Model :

 Mos gate Above the channel &


may partially overlap S & D diffusion areas.

 Gate cap. has 2components


i. Intrinsic cap. (over the channel)
ii. Overlap cap. (to the S, D & Body)
1. INTRINSIC CAPACITANCE:
[ Approx. as a simple ||el plate capacitance.]

i.e. Co = WL Cox

 However, bottom plate of the cap depends on the mode


Of operation of transistor .
I. Cut off II. Linear III. Saturation

I. Cut off :
When transistor = OFF [Vgs = 0]

Channel is not inverted


& Charge on the gate is matched
With opp. charge from the body .

Called Cgb . [G – Body capacitance]

As Vgs (but below Vt)

Depletion region forms at the


surface.

This effectively moves the bottom plate


downward from oxide.

Reducing the capacitance.


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II. Linear :
 When, Vgs > Vt

Channel inverts & again serves as a good conductive


Bottom plate.
However,
Channel connected to the S & D
rather than the Body.

 At low values of Vds channel charge is shared betn S & D.

SO, Cgs = Cgd =C0/2

 As Vds region near the drain becomes less inverted.

So,
Greater fraction of the cap. is attributed to the source
&
Smaller fraction to drain.

III. Saturation:
At Vds > Vgs – Vt
Transistor saturation &
Channel pinches off.

At this pt.
All the intrinsic
capacitance is to the source.
Because of pinch off ,
Capacitance in saturation

Cgs = 2/3 C0 .
(For an Ideal Transistor)
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Approximation of Intrinsic MOS Gate Capacitance:


Parameter Cut Off Linear Saturation
Cgb C0 0 0
Cgs 0 C0/2 2/3 C0
Cgd 0 C0/2 0
Cg=Cgs+Cgd+Cgb C0 C0 2/3 C0

2. Overlap capacitance:-

 Gate overlaps the S & D


by a small amt. in a real device
&
Also has fringing fields terminating on the S & D.

This leads to additional Overlap Capacitances.

These capacitances are


Proportional  Width of the Transistor
Cgsol  W

Typical values: Cgsol = Cgdol = 0.2 – 0.4 fF/µm.

Cgs (overlap) = Cgsol W


Cgd(overlap) = Cgdol W
Cgs & Cgd of a long channel nmos transistor
[W = 49.2 µm, L = 4.5 µm]
 Normalized capacitor varying as a fn. of Vds for a no. of

Vg – Vt values .
Note:-
o At Vds = 0;
Cgs = Cgd = C0/2
As Vds Cgs = (2/3) C0
& Cgd = 0
When transistor saturated.
 Short channel transistor [W = 49.2µm, L = 0.75µm]

Overlap cap. More Imp. for short channel transistor.

Cg = Cgs+Cds+Cgh ≈ C0.
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iii] Detailed Mos Diffusion Capacitance Model :

 RB pn Jn. betn Source diffusion


& Body contributes Parasitic Capacitance .

 Capacitance depends on both the


Area „AS‟ &
Sidewall Parameter „PS‟
of source Diffusion region .
o Area, AS = W.D
o Perimeter, PS =2.W + 2.D

 Total parasitic capacitance,


Csb = AS. Cjbs + PS.Cjbssw
Where,
Cjbs units of capacitance/area
Cjbssw units of capacitance/length

 Because of depletion region thickness depends on RB.


These Parasitics are nonlinear.
-M
Area jn. Capacitance, Cgbs = CJ[1+Vsb/ψ0] J.

CJ Jn. Cap. at zero bias & Highly process - dependent


MJ Jn. Gradient co-eff. (Typically value 0.5 – 0.33)
Ψ0 Built-in potential (Depends on doping levels)

ψ0 = VT ln NA ND
n2i
where,
VT = Thermal voltage = (kT)/q ( not threshold)
(26 mv at room Temp. )
K = 1.380 x 10-23 J/K (Boltzmann const.)
T = Abs. Temp.(300k at room temp.)
q = 1.602x10-19c
NA = doping levels of the body & source diffusion
region.
ND = Intrinsic carrier concentration in undoped
Silicon. (1.45 x 1010 cm-3 at 300k)
 Sidewall Capacitance,
Cjbssw CJsw [1+Vsb/ψ0] –MJsw
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NON IDEAL I-V EFFECTS

 In Ideal I-V model


Ids = Coxµ W/L [(Vgs-Vt) Vds – Vds2/2] &
Ids = Coxµ W/2L (Vgs – Vt) 2

Neglect many effects that are important to Modern devices.

I-V Characteristics of a unit nMOS Transistor [180 nm process]

Ids (A) Ids


400 1 mA Saturation Vds = 1.8
Sub- Region
100 A
Vgs = 1.8 threshold
300 10 A Region
1 A
Vgs = 1.5 100 nA
200
10 nA
Sub-
Vgs = 1.2 1 nA threshold
100 100 pA Slope
Vgs = 0.9 10 pA Vt
Vgs = 0.6
0 Vds 0 0.3 0.6 0.9 1.2 1.5 1.8
0 0.3 0.6 0.9 1.2 1.5 1.8 Vgs

 Compares Characteristics in the Linear & Saturation Regions with Ideal Device

Sat. ct. < Quadratically with Vgs

 This is caused by 2 effects


i] Velocity saturation
ii] Mobility degradation

 At high lateral field strengths (Vds / L)


Carrier Velocity ceases ↑Linearly
with field strength.
Called VELOCITY SATURATION.
As result:
Lower Ids than expected
at High Vds.

 At High Vertical Field Strength,(Vds/tox)


Carriers Scatter more Often.

This Mobility Degradation Effect


Leads to Less Ids than expected
at high Vgs.
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 Non – Ideal Transistor sat. ct. slightly with Vds.

Caused by Channel Length Modulation.

This higher Vds Size of Depletion region around


Drain
& thus effectively
Shortens the Channel.
 Several source of leakage:
Result: Current flow in Normally OFF transistor.
 Observed,
At Vgs < Vt

Ct. drops off exponentially


rather then
Abruptly becoming zero.

Called SUBTHRESHOLD CONDUCTION.


 Threshold voltage
Influenced by the voltage diff. betn S & Body

Called BODY EFFECT.


 S & D diffusions are RB diodes
& experiences Jn. leakage into Substrate (Or) Well.

IG = Ideally ZERO

 However,
Thickness of Gate oxides only a small no. of atomic layers

Electrons tunnel the Gate

&
Causes some „G‟ ct. IG

Temperature : Both Mobility & Threshold voltage with r Temp.

Mobility effect: Most imp. for ON transistors.


Result: Lower Ids at High Temp.
Threshold effect: Most imp. for OFF transistors.
Result: High Leakage ct. at high temp.

Note: MOS char. Degrade with Temperature


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1) VELOCITY SATURATION
2) MOBILITY DEGRADATION
3) CHANNEL LENGTH MODULATION
4) BODY EFFECT
5) SUBTHRESHOLD CONDUCTION
6) JUNCTION LEAKAGE
7) TUNNELING
8) TEMPERATURE DEPENDENCE
9) GEOMETRY DEPENDANCE
Refers to the limiting of carrier velocity at high field

1) VELOCITY SATURATION:-
(Different from saturation region of Tr.)

 W. k. t,
Carrier velocity , V = µE
E Electric field
µ Electron (or) Hole mobility
V Carrier drift velocity

Ct. Linearly with the Lateral Electric Field,


Elat = (Vds/L) betn S & D
(This is only true for weak fields.)

 At High field strength ,


Drift velocity rolls off due to Carrier Scattering &
Eventually saturates
 at Vsat.
sat
Carrier velocity Vs electric field

Carrier velocity,
sat / 2
μElat
v  vsat  μEsat
E
1  lat
slope =  Esat

0
0 Esat 2Esat 3Esat
Elat

 At high fields, this ceases to be true

Velocity reaches vsat


 Electrons : 6-10 x 106 cm/s
 Holes : 4-8 x 106 cm/s
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 Without Velocity Saturation,


Saturation current , Ids Coxµ W (Vgs –Vt)2
=
L 2
 If transistor were completely Velocity Saturated,
V = Vsat
&
Saturation ct,
Ids = Cox W (Vgs –Vt) Vsat
Note:
Ids Quadratically dependent on voltage without velocity saturated
&
Linear dependent when fully Velocity saturated.

For moderated supply voltages,


Trs. Operate in a region,
[where the velocity No longer ↑ linear with field]

But completely saturated.


 - Power Law Model :
 0 Vgs  Vt cutoff

 V
I ds   I dsat ds Vds  Vdsat linear
 Vdsat
 I dsat Vds  Vdsat saturation
Ids (A) Simulated
400 -law Where ,
Shockley
Idsat = Pc ( β/2) (Vgs – Vt)
300 Vdsat = Pv (Vgs – Vt)/2
Vgs = 1.8

200 Compares Ids for a velocity – saturated nmos Tr. With


Vgs = 1.5 Ideal (Shockley model) Tr. &  - power law

100 Vgs = 1.2

Vgs = 0.9
0
0 0.3 0.6 0.9 1.2 1.5 1.8 V
Vgs = 0.6  Called Velocity Saturation Index.
ds

 As Trs. becomes more Velocity saturated,

↑ Vgs has Less effect on ct.


& ↓
Reaching  = 1
Trs. completely velocity saturated.
 For simplicity,
Model uses Straight line in the linear region.
 Model is based on 3 parameters (, βPc & PV)
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 As channel Length become shorter Lateral field &


Trs. becomes more Velocity Saturated ,
( Closer to 1)

if supply voltage is held


const.
 Shockley model Over predicts current at high voltage

But,
 - Power fit Reasonably good.

 As Tr. becomes severely velocity Saturated

There is no performance
Benefit to raising VDD.
2) MOBILITY DEGRADATION:-

 Low – field mobility of holes (much lower than that of Electrons )


`
pMos trs. experience less velocity saturation
than nmos for a
Given VDD.
It Shows
[pMOS  > nMOS  ]
 Strong vertical electric fields (from large Vgs)

Scatters carriers against the surface


&
Carrier Mobility, µ.

This effect is called


MOBILITY DEGRADATION.

It replaces µ with smaller µeff.


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3) CHANNEL LENGTH MODULATION:-

 Ideal, Ids independent of Vds for a Tr. in saturation .GND VDD VDD
Source Gate Drain
Depletion Region
Makes the transistor as a perfect current Width: Ld

Source
L
n+ n+
 RB pn jn. between the D & body forms a Leff
p GND bulk Si
depletion region
with a
Width, Ld that with Vdb.

 Depletion region effectively


Shortens the channel length ,
Leff = L – Ld
 To avoid introducing the
Body voltage in our calculations,
Ids (A)
400

Vgs = 1.8
Assume source voltage is close to the body voltage,
300 So Vdb ≈ Vds
Vgs = 1.5
200
Hence Vds Effective channel length.
Vgs = 1.2
100
Vgs = 0.9 Shorter channel length ,
Vgs = 0.6
0 Result: higher current.
0 0.3 0.6 0.9 1.2 1.5 1.8 Vds
[ Ids↑ with ↑Vds in saturation ]
I-V Characteistics of Nmos transistor with channel length modulation
 Modeled by,
2
In sat region , Ids = β [(Vgs – Vt) /2 ] (1+λVds)

λ → Empirical channel length modulation factor.

Note: [Diff ; from the λ which is used in layout design rules]


 As channel length gets shorter,
Effects of the channel length modulation
More important.
Hence,
λ 1
channel length
 NOTE :
Channel length modulation Very Important to analog designers.
(It Gain of amplifiers)
Unimportant for Digital circuits.
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4) BODY EFFECT:

 Apart from G, source & Drain


Body is an implicit 4th terminal .

 All MOS devices are made on a common Substrate(Body)

Result : Equal substrate voltages of


all devices.
 When several devices connected in series.
Result : Increase in Source – to – substrate
Voltage (Vsb)
i.e ( Vsb1 = 0 , Vsb2 ≠ 0)

 Under normal conditions;


When Vgs > V t : (Deletion layer width remains constant)

Vsb

Width of Channel – substrate Depletion Layer

Result : density of trapped charge carriers in


depletion layer

For charge neutrality to hold :


Channel charge must
Result :
Vsb adds channel – substrate potential

Gate – channel voltage drop.

As Overall Effect :
Threshold voltage ,Vt .
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.

 i.e ) Pot. Diff. between S & Body, Vsb Affects the threshold voltage.

Vt  Vt 0    s  Vsb  s 
Where,
Vto Threshold voltage when „S‟ is at the body Potential.

φs Surface potential at threshold.


Φs = 2VTln (NA/n i)
Depends on the doping level, NA
Intrinsic carrier concentration , Ni.

γ Body effect co-efficient


[ typically 0.4 – 1V½]

tox 2q si N A
  2q si N A 
 ox Cox
5) SUBTHRESHOLD CONDUCTION:
 Ideal transistor I-V model assumes
Current only flow from S D

When, Vgs > Vt


 In real transistors,

Current does not abruptly cut off below threshold,


Ids
But rather
1 mA Saturation Vds = 1.8
drops off exponentially.
Sub- Region
100 A
threshold
10 A Region Given by
1 A
Vgs Vt
100 nA
 Vds

10 nA
1 nA
Sub- I ds  I ds 0e nvT
 1  e T
v

 
threshold
100 pA Slope
10 pA Vt

0 0.3 0.6 0.9 1.2 1.5 1.8 I ds 0   vT2 e1.8


Vgs

I-V char. on a logarithmic scale illustrating both Normal


& Subthreshold conduction: This conduction is also known as
Leakage.

Result: Undesired Current when a Tr. is


Nominally OFF.
 Idso Current at threshold
Dependent on process & device geometry.
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 [1 -℮ -Vds/Vt] Indicates leakage = 0 ; if Vds = 0 .

But Full value ,


when Vds is a few multiples
of thermal voltage, VT .
 Subthreshold conduction is
Used in very low-power analog ckts.

o It is also Important for Dynamic circuits & DRAMs .


(It depends on the storage charge on a Capacitor)
o Conduction
thro‟ an OFF Tr. Discharges the capacitor ,
Unless it is refreshed periodically….

 Leakage also Contributes Power dissipation in Idle circuits.

o Leakage Exponentially

 As Vt (or) As Temp.

It becoming a Major problem for

Chips using Low supply


&
Threshold voltages.
 Subthreshold conduction

Exacerbated by Drain – Induced Barrier Lowering (DIBL)


Drain voltage also affect Vt

In which a (+) ve Vds effectively Vt

This effect is especially pronounced in


Short – Channel transistors.

i.e.)
V‟t = Vt - ηVds

Where,
η DIBL co-eff [typically 0.02 – 0.1]

ID = Is [℮ VD/VT - 1]
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Leakage Sources

 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
 Junction leakage
– Reverse-biased PN junction diode current
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Subthreshold leakage
o Biggest source in modern transistors

6) JUNCTION LEAKAGE:

 pn Jns. Between diffusion & substrate (or) well forms diodes.

p+ n+ n+ p+ p+ n+

n well
p substrate

o Well-to-substrate jn. forms Another diode.

o Substrate GND
To ensure diodes RB.

o Well VDD

o However,
RB diodes still conduct a small amount of current , ID.

Diode current,  VvD 


I D  I S  e  1
T

 Is depends on  
– Doping levels  
– Area and Perimeter of diffusion regions
– Typically < 1 fA/mm2

PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.

7) TUNNELING:
 According to Quantum Mechanics
there is a finite probability that carriers
Will tunnel thro‟ the gate oxide.

Result: Gate Leakage at flowing into the gate.

 Probability of tunneling drops off exponentially with


Oxide thickness & so negligible.
 For oxide ,
thinner than 15 – 20 Å.

Tunneling current becomes a factor & may


become comparable to Sub threshold Leakage
in advance processes.

10 9
tox
6
VDD trend 0.6 nm
10
0.8 nm
JG (A/cm )

1.0 nm
10 3
2

1.2 nm

10 0 1.5 nm

1.9 nm
10 -3

10 -6

10 -9

0 0.3 0.6 0.9 1.2 1.5 1.8


VDD

Gate leakage current density, JG Vs Voltage (VDD) for various oxide thicknesses.

 Large tunneling currents impact Not only dynamic nodes


but also
Quiescent Power consumption
&
thus may Limit oxide thickness,
tox
 High Cox Imp. for transistors,
So [Use an alternative gate insulator with a Higher dielectric const.]

Note:
 Key challenge is Finding material that form a high
Quality interface with silicon.
(1 contender is silicon nitride
with a (Si3 N4) dielectric constant of 7.8)

 Tunneling can purposely be used to


Create electrically erasable memory devices.
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.

 Tunneling current is an
Order of magnitude Higher for nmos
than
Pmos Trs. with Sio2 Gate dielectrics
Because,
Electrons tunnel from the Conduction band

While Holes tunnel from the valence band


&
a higher Barrier.

 Note:
Different dielectrics may have different tunneling properties.

8) TEMPERATURE DEPENDENCE:

 Tr. Characteristics are influenced by temp


Carrier mobility With temp.

µ(T) = µ (Tr) (T/Tr)-kµ

Where,
T Absolute temp.
Tr Room temp.&
Kµ Fitting parameter [1.2 – 2.0]

 Mag. of the threshold voltage nearly Linearly with Temp.

appx. Vt (T) = Vt (Tr) - Kvt (T-Tr)


Where,
Kµt typically [0.5 -3.0mv/k]

 Jn. Leakage also ↑ with temp


Because → Is is strongly temp dependent.

 Note: It is cleared that ckts performance is worst at high temp.

called (-) ve temp. co-eff.

 Conversely ,

Circuit Performance can be by cooling.


PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.

 Most system use

Natural convection (or) fans in conjunction with heat sinks,


but
Water cooling,
thin – film refrigerator, (or)
Even liquid nitrogen can performance
if the
Expense is Justified.
 There are Many Advantages of operating at low temp. :

1. Subthreshold leakage is Exponentially Dependent on Temp.

So Lower threshold voltages can be used.


2. Velocity sat. occurs at higher fields
provides more ct.

3. Depletion region become wider

Result: less jn. Capacitance

4. Most wear out mechanisms are Temp. dependent

So trs are more reliable


Note: At low temps. Trs. get breakdown at lower Voltages.

 Temperature Sensitivity :
 Increasing temperature I ds
o Reduces mobility
o Reduces Vt increasing
temperature
 ION decreases with temperature
 IOFF increases with temperature

Vgs

 So what if transistors are not ideal?

 They still behave like switches.

o But these effects matter for…

 Supply voltage choice


 Logical effort
 Quiescent power Consumption
 Pass transistors
 Temperature of operation
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9) GEOMETRY DEPENDENCE:

 Layout designer draws transistor with


Width Wdrawn
Length Ldrawn

 Actual gate dimensions


may differ by some factors Xw & XL

 For E.X:
Manufacturer may create marks with narrower

Polysilicon (or)
May over etch polysilicon

Provides
Shorter channels (-XL)
without Changing the overall
Design rules (or) metal pitch.

 Moreover,
S & D tend to Diffuse laterally under the Gate by LD.

Producing a
Shorter Effective Channel Length

 |||ly,
Diffusion of the bulk by WD ↓d Effective Channel Width.

 Using ware factors,


Leff = Ldrawn + XL – 2LD

Weff = Wdrawn + Xw – 2WD

 A transistor Drawn twice as Long may have an


Effective Length.
( i.e.) more than twice as great.)
|||ly,
2 trs. differing in Drawn widths by a factor of 2
&
Threshold voltage also vary
Somewhat with tr. Dimensions.
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 Long trs. also experience Less Channel Length Modulation.

Combining Threshold,
Effective channel length &
Channel Length modulation

Effects a tr. of

Twice min. Length


Delivers Substantially
< ½ ct. of a min length Device.
 Generally,
When cts. must be precisely matched

It is best to use same


Width & Length for each device,

Ct. ratios can be produced by tying several


Identical transistor in ||el.
 In processes,
Below 0.25µm ,

Effective Length of the tr. also depends


Significantly on the
Orientation of tr.
 Moreover,
Amt, nearby polysilicon also affects Etch rates
During manufacturing
& Channel length.

o Trs. that must match well should have Same orientation.

o Dummy Polysilicon wires


can be Placed nearby to improve Etch uniformity.
PREPARED BY A.KARTHIKAYEN AP/ECE PALLAVAN COLLEGE OF ENGG.

GEOMETRY DEPENDENCE: