2000

EFY
PROJECTS

01
VOLUME

More than 90 fully tested

and ready-to-use
electronics circuits
& IDEAS

2001
Electronics For You
issues
Contents
JANUARY 2001
CIRCUIT IDEAS
1)
2001
ELECTRONIC STARTER FOR SINGLE-PHASE MOTORS ------------------------------------------------------------- 7
2) MODEM 'ON'/'OFF' INDICATOR ------------------------------------------------------------------------------------- 8
3) TOUCH-SELECT AUDIO SOURCE ----------------------------------------------------------------------------------- 9
4) PRECISION ATTENUATOR WITH DIGITAL CONTROL -------------------------------------------------------------- 10
5) PRECISION AMPLIFIER WITH DIGITAL CONTROL ---------------------------------------------------------------- 11
6) RANDOM NUMBER GENERATOR BASED GAME ------------------------------------------------------------------- 12

CONSTRUCTION PROJECTS
1) BUILD YOUR OWN PENTIUM III PC (PART-I) ------------------------------------------------------------------- 14
2) AUTOMATIC ROOM LIGHT CONTROLLER -------------------------------------------------------------------------- 21

FEBRUARY 2001
CIRCUIT IDEAS
1) 9-LINE TELEPHONE SHARER ------------------------------------------------------------------------------------- 27
2) ELECTRONIC CARD LOCK SYSTEM -------------------------------------------------------------------------------- 28
3) PULSED OPERATION OF A CW LASER DIODE -------------------------------------------------------------------- 29
4) GENERATION OF 1-SEC. PULSES SPACED 5-SEC. APART -------------------------------------------------------- 31
5) HIGH-/LOW-VOLTAGE CUTOUT WITH TIMER --------------------------------------------------------------------- 32

CONSTRUCTION PROJECTS
1) BUILD YOUR OWN PENTIUM III PC (PART-II) ------------------------------------------------------------------ 34
2) INTELLIGENT WATER LEVEL CONTROLLER ----------------------------------------------------------------------- 40
3) A UNIQUE LIQUID LEVEL INDICATOR ---------------------------------------------------------------------------- 43

MARCH 2001
CIRCUIT IDEAS
1) AUTOMATIC HEAT DETECTOR ------------------------------------------------------------------------------------- 48
2) MUSICAL 'TOUCH' BELL ------------------------------------------------------------------------------------------- 49
3) NON-CONTACT LIQUID-LEVEL CONTROLLER --------------------------------------------------------------------- 50
4) AC MAINS PHASE-SEQUENCE INDICATOR ------------------------------------------------------------------------ 52
5) HIGH-POWER BICYCLE HORN ------------------------------------------------------------------------------------ 54
6) LUXURIOUS TOILET/BATHROOM FACILITY ---------------------------------------------------------------------- 55

CONSTRUCTION PROJECTS
1) INTERFACE YOUR PRINTER WITH 8085 MICROPROCESSOR ---------------------------------------------------- 58
2) MORSE PROCESSOR ----------------------------------------------------------------------------------------------- 63

APRIL 2001
CIRCUIT IDEAS
1) EEPROM W27C512 (WINBOND) ERASER ------------------------------------------------------------------------- 74
2) INTELLIGENT ELECTRONIC LOCK --------------------------------------------------------------------------------- 75
3) STABLE 455KHZ BFO FOR SSB RECEPTION ---------------------------------------------------------------------- 78
4) AUTO SHUT-OFF FOR CASSETTE PLAYERS AND AMPLIFIERS ---------------------------------------------------- 81
5) HOUSE SECURITY SYSTEM ---------------------------------------------------------------------------------------- 84
6) SIMPLE WATER-LEVEL INDICATOR-CUM-ALARM ----------------------------------------------------------------- 87

CONSTRUCTION PROJECTS
1) ACCESS-CONTROL SYSTEM ---------------------------------------------------------------------------------------- 90
2) TELEPHONE LINE-INTERFACED GENERIC SWITCHING SYSTEM (PART-I) --------------------------------------- 87
Contents
MAY 2001

CIRCUIT IDEAS
1)
2001
PRECISION INDUCTANCE AND CAPACITANCE METER ------------------------------------------------------------ 93
2) UNDER-/OVER-VOLTAGE BEEP FOR MANUAL STABILISER ------------------------------------------------------ 95
3) ULTRA-SENSITIVE SOLIDSTATE CLAP SWITCH ------------------------------------------------------------------- 97
4) 15-STEP DIGITAL POWER SUPPLY -------------------------------------------------------------------------------- 98
5) MICROPHONE FOR COMPUTER ----------------------------------------------------------------------------------- 100

CONSTRUCTION PROJECTS
1) PROGRAMMABLE MELODY GENERATOR (PART-I) --------------------------------------------------------------- 102
2) TELEPHONE LINE-INTERFACED GENERIC SWITCHED SYSTEM (PART-II) -------------------------------------- 110

JUNE 2001
CIRCUIT IDEAS
1) VERSATILE ZENER DIODE TESTER ------------------------------------------------------------------------------- 117
2) DTMF PROXIMITY DETECTOR ------------------------------------------------------------------------------------- 119
3) STEPPER MOTOR CONTROL --------------------------------------------------------------------------------------- 120
4) LOW-COST INTERCOM -------------------------------------------------------------------------------------------- 121
5) HIGH-POWER CAR BATTERY ELIMINATOR ---------------------------------------------------------------------- 122
6) AUTOMATIC PLANT IRRIGATOR ---------------------------------------------------------------------------------- 123
CONSTRUCTION PROJECTS
1) PROGRAMMABLE MELODY GENERATOR (PART-II) -------------------------------------------------------------- 125
2) AUTO CONTROL FOR 3-PHASE MOTORS ------------------------------------------------------------------------- 129

JULY 2001
CIRCUIT IDEAS
1) PC-BASED DIAL CLOCK-CUM-ELECTRONIC ROULETTE ---------------------------------------------------------- 136
2) SIMPLE TELEPHONE RING TONE GENERATOR ------------------------------------------------------------------- 138
3) DUAL-INPUT HIGH-FIDELITY AUDIO MIXER ------------------------------------------------------------------- 139
4) ANTI-THEFT SECURITY FOR CAR AUDIOS ----------------------------------------------------------------------- 140
5) UNIPOLAR/BIPOLAR TRIANGULAR AND BIPOLAR SQUARE WAVE GENERATOR ------------------------------ 141

CONSTRUCTION PROJECTS
1) TELEPHONE REMOTE CONTROL ---------------------------------------------------------------------------------- 143
2) MICROCONTROLLER-BASED SCHOOL TIMER -------------------------------------------------------------------- 146

AUGUST 2001
CIRCUIT IDEAS
1) LONG-RANGE CORDLESS BURGLAR ALARM --------------------------------------------------------------------- 153
2) WATER-LEVEL CONTROLLER -------------------------------------------------------------------------------------- 154
3) INVISIBLE BROKEN WIRE DETECTOR --------------------------------------------------------------------------- 156
4) PC-BASED MULTI-MODE LIGHT CHASER ------------------------------------------------------------------------ 157
5) FUSE STATUS INDICATORS FOR POWER-SUPPLIES ------------------------------------------------------------- 159

CONSTRUCTION PROJECTS
1) DIGITAL CAPACITANCE-CUM-FREQUENCY METER --------------------------------------------------------------- 162
2) FLUID-LEVEL CONTROLLER WITH INDICATOR ------------------------------------------------------------------ 166

SEPTEMBER 2001
CIRCUIT IDEAS
1) A HIERARCHICAL PRIORITY ENCODER -------------------------------------------------------------------------- 171
Contents
2)
2001
DIGITAL MAINS VOLTAGE INDICATOR --------------------------------------------------------------------------- 173
3) ELECTRONIC DICE ------------------------------------------------------------------------------------------------ 175
4) LIGHT-OPERATED ORGAN ---------------------------------------------------------------------------------------- 177

CONSTRUCTION PROJECTS
1) MGMA-A MIGHTY GADGET WITH MULTIPLE APPLICATIONS --------------------------------------------------- 179
2) TRAFFIC AND STREET LIGHT CONTROLLER --------------------------------------------------------------------- 183

OCTOBER 2001
CIRCUIT IDEAS
1) DIGITAL FAN REGULATOR ---------------------------------------------------------------------------------------- 192
2) STEREO TAPE HEAD PREAMPLIFIER FOR PC SOUND CARD ---------------------------------------------------- 194
3) RUNNING LIGHTS AND RUNNING HOLES ----------------------------------------------------------------------- 195
4) HEART BEAT MONITOR ------------------------------------------------------------------------------------------- 197
5) 12V, 3A POWER SUPPLY ----------------------------------------------------------------------------------------- 198
6) A SIMPLE TRANSISTOR TESTER --------------------------------------------------------------------------------- 199

CONSTRUCTION PROJECTS
1) LEAD-ACID BATTERY CHARGER WITH ACTIVE POWER CONTROL ---------------------------------------------- 201
2) MICROCONTROLLER-BASED DIGITAL CLOCK -------------------------------------------------------------------- 204

NOVEMBER 2001
CIRCUIT IDEAS
1) SPELLER EFFECT SIGN DISPLAY --------------------------------------------------------------------------------- 210
2) DARKROOM TIMER ----------------------------------------------------------------------------------------------- 211
3) LONG-RANGE TARGET SHOOTER --------------------------------------------------------------------------------- 212
4) ACTIVE SHORTWAVE ANTENNA ---------------------------------------------------------------------------------- 214
5) POWER SUPPLY FOR WALKIE-TALKIE --------------------------------------------------------------------------- 215
6) HIGH-PERFORMANCE INTERRUPTION DETECTOR --------------------------------------------------------------- 216

CONSTRUCTION PROJECTS
1) AMPLITUDE MEASUREMET OF SUB-MICROSECOND PULSES --------------------------------------------------- 218
2) AUTOMATIC SUBMERSIBLE PUMP CONTROLLER ---------------------------------------------------------------- 221

DECEMBER 2001
CIRCUIT IDEAS
1) DIGITAL RELAY TESTER FOR RAX AND MAX -------------------------------------------------------------------- 226
2) DECORATIVE SIGNBOARD ---------------------------------------------------------------------------------------- 228
3) OVERLOAD PROTECTOR WITH RESET BUTTON ------------------------------------------------------------------ 230
4) FASTEST FINGER FIRST INDICATOR ----------------------------------------------------------------------------- 231
5) CONDENSER MIC AUDIO AMPLIFIER ---------------------------------------------------------------------------- 232
6) SMOKE ALARM --------------------------------------------------------------------------------------------------- 233

CONSTRUCTION PROJECTS
1) TRANSISTOR CURVE TRACER ------------------------------------------------------------------------------------ 235
2) TRIPPING-SEQUENCE RECORDER-CUM-INDICATOR ------------------------------------------------------------- 241
January

2001
Circuit Ideas

2001
 C I R C U I T I D E A S

ELECTRONIC STARTER contact ratings of relay RL3 should be 10

to 15 amperes.
Transformer X1 can be wound us-

FOR SINGLE-PHASE MOTORS DWIV

EDI
ing any suitable size CRGO core. (One
can use a burntout transformer core as
well.) The primary comprises 30 to 31
S.C. turns for use with 1HP motor and addi-
SARAT CHANDRA DAS tional eight turns, if you are using a
0.5HP motor. Fuses F1 and F2 are kit-

A
novel single-phase electronic lay RL2 latches even if switch S1 is sub- kat type. The ‘on’ pushbutton is nor-
starter circuit meant for 0.5HP sequently opened. The other N/O con- mally-‘off’ type, while ‘off’ pushbutton
and 1HP motors is presented tacts RL2(b) of relay RL2, on S2 is of normally-‘on’ type. Capacitors
here. It incorporates both overload and energisation, connect the voltage devel- C1 and C2, apart from smoothing the
short-circuit protections. A special cur- oped across capacitor C2 to relay RL3, rectified output, provide necessary de-
rent-sensing device has been added in which thus energises and completes the lay during energisation and de-
this starter to sense the current being supply to the motor, as long as current energisation of relays. Diodes across re-
drawn by the motor. passing through primary of transformer lays are used for protection as free-
If the motor jams due to bearing fail- X1 is within limits (for a 1HP motor). wheeling diodes.
ure or defect in the pump or any other When the current drawn by motor Starters for 0.5HP and 1HP motors
reason, it would draw much higher cur- exceeds the limit (approx. 5A), the volt- are not easily available in the market.
rent than its normal rated current. This age developed across the secondary of Users are therefore compelled to use
will be sensed by the current-sensing transformer X2 is sufficient to energise 10-amp rated circuit breaker for such
device, which will trip the circuit and relay RL1 and trip the supply to relays motors. A mechanical starter or auto
protect the motor. Some other reasons RL2 and RL3, which was passing via starter would turn out to be costlier
for the motor drawing higher current the N/C contact of relay RL1. As a re- than the circuit given here, which works
are as follows: sult, the supply to the motor also trips. very reliably. Parts used in this circuit
(a) Windings damaged or short-cir- The contact rating for relays RL1 are easily available in most of the local
cuit between them. and RL2 should be 5 amperes, while markets.
(b) Shorting of motor terminals by
mistake.
(c) Under voltage or single phasing
occuring in the mains supply source
(normally, a 440V AC, 3-phase with neu-
tral four-wire system).
The main components used in the
circuit comprise a specially wound sens-
ing transformer X1, another locally
available step-down transformer X2,
single-changeover relay RL1, two
double-changeover relays (RL2 and
RL3), and other discrete components
shown in the figure. The mains supply
to the motor is routed in series with
the primary of transformer X1 via nor-
mally-open contacts of relay RL3. The
primary of transformer X1 is connected
in the neutral line.
To switch on the supply to the mo-
tor, switch S1 is to be pressed momen-
tarily, which causes the supply path to
the primary of transformer X2 to be
completed via N/C contacts of relay RL1.
Relay RL2 gets energised due to the
DC voltage developed across capacitor
C2 via the bridge rectifier. Once the
relay energises, its N/O contacts RL2(a)
provide a short across switch S1 and
supply to the primary of transformer
X2 becomes continuous, and hence re-

ELECTRONICS FOR YOU ❚  JANUARY 2001

 C I R C U I T I D E A S

MODEM ‘ON’/‘OFF’ INDICATOR

eration of the gadget. For this, first switch
on the supply to the gadget and then
switch ‘on’ the modem. Now adjust the
EDI wiper of preset VR1 very slowly until the
T.K. HAREENDRAN DWIV
S.C. LEDs start blinking. Memorise the wiper
position and fix it in this position using a

H
ere is an interesting, low com- tivated transistor inside opto-coupler good-quality glue/compound.
ponent-count, and easy-to-build via resistor R3. Consequently, LEDs D1 After construction, fix the complete
electronic circuit for the and D2 start blinking at the bistable circuit in a suitable and attractive cabi-
Internet surfers. This circuit, using two IC1’s frequency determined by the val- net with one LED in its front panel. Keep
LEDs, indicates the modem status, i.e.
whether it is in use or not.
The incoming telephone line termi-
nating on a master phone is shunted by
a metal oxide varistor.
The circuit is configured around the
popular timer chip NE555N, which is
wired as an astable multivibrator. When
power is applied to the circuit, the
astable starts working as usual. How-
ever, LEDs D2 and D3 connected to its
output pin 3 would not glow as transis-
tor T1 is in off condition and hence re-
sistor R4’s bottom end is hanging in high
impedance state.
However, when the modem is work- ues of resistors R1 and R2 and capaci- the whole unit near the modem and fit
ing, voltage drop across preset VR1 tor C1. another LED near the master telephone
illuminates the LED inside the opto- A 9V, 0.5A AC adapter can be used with the label ‘Modem in Use’.
coupler (IC2). As a result, transistor to power the circuit. Finally, one minor
T1 gets sufficient base-bias through ac- adjustment is required for successful op-

ELECTRONICS FOR YOU ❚  JANUARY 2001

 C I R C U I T I D E A S

TOUCH-SELECT AUDIO SOURCE input of power amplifier. This is indicated

by lighting of LED2.
Pin 9 is the control pin of IC2. In the
EDI
SARAVANAN J. DWIV circuit, the state of multiplexer switches
S.C. is shown with pin 9 ‘high’ (CD source se-
lected). When pin 9 is pulled ‘low’, all the

O
ften you need to connect out- N1 output (IC1, pin 3) goes high while switches within the multiplexer change
put from more than one source the output of gate N2 at pin 4 goes low. over to the alternate position to select
(preamplifier) such as tape re- This causes selection of CD outputs being tape player as source.
corder/player and CD (compact disc) connected to the power amplifier input, EFY Lab note. Although one can con-
player to audio power amplifier. This which is indicated by lighting of LED1. nect pin 7 (VEE) of IC2 to ground, but for
needs disconnecting/con-
necting wires when you
want to change the source,
which is quite cumber-
some and irritating.
Here is a circuit that
helps you choose between
two stereo sources by
simple touch of your hand.
This circuit is so compact
that it can be fixed within
the audio power amplifier
cabinet and can use the
same power supply source.
The circuit uses just
two CMOS ICs and a few
other componenets. The
ICs used are MC14551/CD4551 (quad 2- When touch-plate S2 is touched, the operation with preamplifier signals going
channel analogue multiplexer) and outputs of gates N1 and N2 toggle. That above and below ground level, one must
CD4011 (quad 2-input NAND gate). When is, IC2 pin 3 is pulled ‘low’ while its pin 4 connect it to a negative voltage (say, –1V
touch-plate S1 is touched (its two plates goes ‘high’. This results in selection of tape to –1.5V) to avoid distortion.
are to be bridged using a fingertip), gate recorder outputs being connected to the

ELECTRONICS FOR YOU ❚  JANUARY 2001


PRECISION ATTENUATOR
WITH DIGITAL CONTROL
ANANTHA NARAYAN
W
hen instruments are designed,
an analogue front-end is es-
sential. Further, as most equip-
ment have digital or microcont-roller in-
terface, the analogue circuit needs to have
digital control/access.
The circuit of a programmable attenu-
ator with digital control is described here,
where digital control can be a remote dip
switch, or CMOS logic outputs of a de-
cade counter (having binary equivalent
weight of 1, 2, 4, and 8, respectively), or
I/O port of a microcontroller like 80C31.
The heart of this circuit is the popu-
lar OP07 op-amp with ultra-low offset in
the inverting configuration. A dual, 4-
channel CMOS analogue multiplexer
switch CD4052 enables the change in
gain. An innovative feature of the circuit
is that the ‘on’ resistance (around 100
ohms) of CD4052 switch is bypassed so
that no error is introduced by its use.
Resistors R1 to R6 used in the circuit
should be of 0.1 per cent tolerance, 50
ppm (parts per million) if you use 3½-
digit DPM, i.e. ±1999 counts (approx. 11
bits). But for 4½-digit DPM (approx. 14
bits), you may need to have trimpots (e.g.
replace 1k-ohm resistor R6 by a fixed 900-
ohm resistor in series with a 200-ohm
trimpot) to replace R3, R4, R5, and R6
C I R C U I T I D E A S
DWIV
EDI
S.C.
gain selection resistors for proper calibra-
tion to required accuracy. However, for
testing or trials, use 1 put of op-amp to ±0.5V, thereby protect-
per cent 100ppm MFR resistors. The
expected errors will be around 1 per cent.
To keep parts count (hence cost) to a
minimum, the common or ground is used
as the positive input terminal and one
end of resistor R1 as the negative. This is
so because the op-amp inverts the polar-
ity as it is used in inverting configura-
tion. This does not matter as the equip-
ment will be isolated by the power supply
transformer and all polarities are rela-
tive. In case you want the common to be
the negative, you will have to add some
stages (IC4 and IC5 circuitry shown in
precision amplifier circuit described later).
The OP07 pinout is based on stan-
dard single op-amp 741. Any other
op-amp like CA3140, TLO71, or LF351
can be used but with offset errors in ex-
cess of 1 per cent, which is not tolerable
in precision instrumentation.
The OP07 has equivalent ICs like
µA714 and LM607 having ultra-low off-
set voltage (<100µV), low input bias
current (<10nA), and high input imped-
ance (>100M), which are the key require-
ments for a good instrumentation op-amp
for use with DC inputs.
ELECTRONICS FOR YOU ❚  JANUARY 2001
The following design considerations
should be kept in mind:
(a) Input: 500V max
Since ¼W resistors can withstand up
to 250V, resistors R1 and R2 in series are
used for 1 meg-ohm with 500V (max) in-
put limit. These resistors additionally
limit the input current as well. Diodes
D1 and D2 clamp the voltage across in-
ing the op-amp.
(b) Output
The output can be connected to a
7107/7135-based DPM or any other ana-
logue-to-digital converter or op-amp stage.
Use a buffer at the output if the output
has to be loaded by a load less than 1
meg-ohm.
Use an inverting buffer if input leads
have to have polarity where ground is the
inverting terminal. (For details, see next
circuit.)
(c) CD4052 CMOS switch
The on-resistance (100-ohm approx.)
comes in series with the op-amp output
source resistance, which produces no er-
ror at output.
Caution. The circuit does not isolate,
it only attenuates. When high voltage is
present at its input, do not touch any
part of the circuit.
(d) Digital control options
(i) A and B can be controlled by I/O
port of a microcontroller like 80C31 so
that the controller can control gain.
(ii) A and B can be given to counters
like 4029/4518 to scroll gain digitally.
(iii) A and B can be connected to DIP
switch.
(iv) A and B can be connected to a
thumbwheel switch.
Notes. 1. Digital input logic 0 is 0V
and logic 1 is 5V.
Truth Table (Control input VS attenuation)
X,Y (ON-switch (2) (1) Gain
Pair) B A (Attenuation)
X0,Y0 0 0 1/1000
X1,Y1 0 1 1/100
X2,Y2 1 0 1/10
X3,Y3 1 1 1
2. All resistors are metal film resis-
tors (MFR) with 1% tolerance, unless
specified otherwise.
3. C2 and C3 are ceramic disk capaci-
tors of 0.1µF = 100n value.

PRECISION AMPLIFIER
WITH DIGITAL CONTROL
ANANTHA NARAYAN
T
his circuit is similar to the pre-
ceding circuit of the attenuator.
Gain of up to 100 can be
achieved in this configuration, which is
useful for signal conditioning of low out-
put of transducers in millivolt range.
The gain selection resistors R3 to
R6 can be selected by the user and
can be anywhere from 1 kilo-ohm to 1
meg-ohm. Trimpots can be used for ob-
taining any value of gain required by
the user. The resistor values shown in
the circuit are for decade gains suitable
for an autoranging DPM.
Resistor R1 and capacitor C1 reduce
ripple in the input and also snub tran-
sients. Zeners Z1 and Z2 limit the input
to ±4.7V, while the input current is lim-
ited by resistor R1. Capacitors C2 and
C3 are the power supply decoupling ca-
pacitors.
Op-amp IC1 is used to increase the
input impedance so that very low in-
C I R C U I T I D E A S
DWIV
EDI
Gains greater than 100 may not be
practical because even at gain value of
S.C. 100 itself, a 100µV offset will work out
to be around 10 mV at the output (100µV
x 100). This can be trimmed using the
offset null option in the OP07, connect-
ing a trimpot between pins 1 and 8, and
connecting wiper to +5V supply rails.
puts are not loaded on measurement. For better performance, use ICL7650
The user can terminate the inputs with (not pin-compatible) in place of OP07
resistance of his choice (such as 10 meg- and use ±7.5V instead of ±5V supply.
ohm or 1 meg-ohm) to avoid floating of Eight steps for gain or attenuation
the inputs when no measurement is be- can be added by using two CD4051 and
ing made. pin 6 inhibit on CD4051/52. More steps
IC5 is used as an inverting buffer to can be added by cascading many
restore polarity of the input while IC4 CD4051, or CD4052, or CD4053 ICs, as
is used as buffer at the output of pin 6 works like a chip select.
CD4052, because loading it by resistance Some extended applications of this
of value less than 1 meg-ohm will cause circuit are given below.
an error. An alternative is to make 1. Error correction in transducer
R7=R8=1 meg-ohm and do away with amplifiers by correcting gain.
IC4, though this may not be an ideal 2. Autoranging in DMM.
method. 3. Sensor selection or input type se-
lection in process control.
Truth Table (Control Input vs Gain) 4. Digitally preset power supplies or
X,Y (On-switch (2) (1) Gain electronic loads.
Pair) B A (Av.) 5. Programmable precision mV or
X0,Y0 0 0 1/10 mA sources.
X1,Y1 0 1 1 6. PC or microcontroller or micro-
X2,Y2 1 0 10 processor based instruments.
X3,Y3 1 1 100
7. Data loggers and scanners.
ELECTRONICS FOR YOU ❚  JANUARY 2001
 C I R C U I T I D E A S

RANDOM NUMBER RUP

ANJA
NA

GENERATOR BASED GAME

(CD4033 decade upcounter cum 7-segment
decoder). In conjunction with three 7-seg-
ment displays (DIS1 to DIS3), these form
a 3-digit clock counter. The clock count-
K. UDHAYA KUMARAN ing speed is dependant upon the clock
pulse frequency of IC4. It is connected to
clock input pin 1 of IC1 while chip enable

T
his electronic game is simulation tor C1 are shorted by switch S1 and pin 2 of IC1 to IC3 are held low. Thus all
of one-arm bandit game. Elec- timer IC4 works as a free-running clock counter ICs advance by 1 for every
tronics hobbyists will find it very astable multivibrator. The operating fre- positive clock transition. Reset pin 15 of
interesting. When toggle switch S1 is quency is in the vicinity of 35 kHz, all counter ICs is held low through resis-
in ‘run’ position, all segments of 7-seg- determined by the value of timing com- tor R25. Thus reset facility is not used in
ment displays (DIS1 through DIS3) will ponents. this circuit.
light up. On turning toggle switch S1 When toggle switch S1 is flipped Due to persistence of vision, one can-
from ‘run’ to ‘stop’ position, displayed from ‘run’ to ‘stop’ position, capacitor not distinguish 0-9 counting in DIS1 to
digits will continue advancing and the C1 is introduced in the discharge path DIS3 when the clock frequency is high.
final display is unpredictable. Thus the of pin No. 7 of IC4 and junction of re- All 7-segment displays appear to show
final number displayed in DIS1 through sistors R22 and R24. At the same time, digit 8, while the red LED1 remains lit
DIS3 is of random nature. The speed capacitor C4 comes in parallel with tim- continuously, indicating clock counter
with which the number in 7-segment ing capacitor C3 to change the operat- is in running condition.
display keeps changing on flipping ing frequency of the astable from On sliding toggle switch S1 from
switch S1 from ‘run’ to ‘stop’ condition around 35 kHz to around 65 Hz. Now ‘run’ to ‘stop’ position, the counting
slowly decays before stopping with a capacitor C1 slowly starts charging as speed of individual digits falls immedi-
random number display. it is connected in the discharge path of ately due to the clock frequency chang-
To play this game, one has to obtain the timing capacitors C3 and C4. The ing to around 65 Hz. Now, the count-
three identical numbers in displays clock frequency of IC4 gradually reduces ing speed will be 65 Hz for DIS3, 6.5
DIS1 through DIS3. The contestant and after 15 seconds, when capacitor Hz for DIS2, and 0.6 Hz for DIS1. This
would score 1 (one) point if he manages C1 is sufficiently charged, the oscillat- speed of individual digit counting slowly
to get a final display of ‘000’, 2 points
for getting ‘111’ display, 3 points for
‘222’,… and so on—up to ten points for
‘999’. He should try to score maximum
possible points in fixed numbers of at-
tempts (say, 20 to 25 attempts).
Apart from using this circuit as
a game for entertainment, one can use
it as random number generator for
any other application as well. The de-
cay time with the given component
values is around 15 seconds before the
display could stop at a final random
number.
The circuit comprises clock oscilla-
tor built around NE555 timer IC4,
three-stage clock pulse counter built us-
ing three CD4033 ICs (IC1 to IC3), and
three 7-segment LED displays (DIS1 to
DIS3).
In clock oscillator circuit, NE555
timer IC4 is used in a similar way as a
free-running astable multivibrator, the
only difference being the additional ca- ing frequency gradually drops and fi- decays, until the counter stops and
pacitor C1 introduced between pin No. nally it stops oscillating. Thus, pin 3 of LED1 stops blinking, and the final count
7 of IC4 and junction of resistors R22 IC4 becomes low. (random numbers) are displayed in
and R24. When toggle switch S1 is in Second part of the circuit comprises DIS1, DIS2, and DIS3.
‘run’ position, both terminals of capaci- three cascaded ICs, IC1 through IC3

ELECTRONICS FOR YOU ❚  JANUARY 2001

Construction

2001
 C O N S T R U C T I O N

BUILD YOUR OWN

til it is required for installation. When
RA
UND it is taken out from the envelope, it
N. K
should be immediately placed on a suit-
able grounded conductive surface. The

PENTIUM III PC PART-I motherboard itself should be held from

edges and the person taking it out
should wear an antistatic wrist strap
that is properly grounded. In the ab-
K.C. BHASIN AND NEERAJ KUNDRA sence of a proper wrist strap, you may
make one on your own using a peeled
off multi-strand copper cable and ground

T
he procedure presented here length of the cable provided for inter- it properly. Similar handling precau-
would enable you to assemble connections to the motherboard or add- tions are also required for DIMMS and
your own multimedia personal on cards has to be taken into account, as cards.
computer. It is assumed that you have there must be some slack after these are • If you are using a motherboard dif-
a fundamental knowledge of how a PC installed and connected.) This will im- ferent from the one mentioned in the
functions and some basics of electron- prove the cooling and re-
ics. By way of tools you only need duce the chances of electro-
Philips-head and flat-blade screwdriv- magnetic interference be-
ers. A simple multimeter is the only tween them.
test equipment that you would ever re- • The motherboard con-
quire during assembly, for AC and DC tains sensitive components,
voltage measurement. which can be easily dam-
All the parts needed to assemble this aged by static electricity.
multimedia PC with processor speed of Therefore the motherboard
700 MHz are listed under Parts List. should remain in its origi-
The cost of parts may vary from dealer nal antistatic envelope un-
to dealer and also with time. The total
cost of the listed parts at current price
level ranges from Rs 33,000 to Rs 37,000.
It is suggested to source these items
from authorised dealers who would meet
their warranty obligations. We have also
mentioned the brand names of the parts
that we used during assembly of the
basic unit. It is, however, not necessary
to use identical makes, except, of course,
the main processor and the
motherboard, based on identical chipset
mentioned later in this article.

Precautions
Before starting the actual assembly of
the PC system, the following precau-
tions would help you to avoid any mis-
hap during the assembly process:
• While the motherboard has to be
fitted at a fixed place inside the PC cabi-
net, the locations of add-on cards (as and
when used) and the drives (hard disk
drive, floppy disk drive, and CD-ROM
drive) within the drives’ bay of the cabi-
net can be changed within certain lim-
its. But it is better to place them far
away from each other. (Of course, the
The authors represent a combined team from
EFY and IT Solutions (India) Pvt Ltd, New Delhi Fig. 1: Block diagram of motherboard employing 810E chipset

ELECTRONICS FOR YOU ❚  JANUARY 2001

 C O N S T R U C T I O N

• Never try to insert a card in PC

Key Features of Motherboard Using Intel 810/810E Chipset slots or try to plug/unplug a connector
Processor with power supply to the PC ‘on’.
• Full support for the Intel Pentium III and Celeron processors using PGA370 socket. • Ensure that the mains 3-pin socket
• Supports 66MHz and 100MHz bus speed including all PGA370.
• Supports 133MHz bus speed (810E chipset version only). or the socket on your stabiliser/UPS
that you would be using for connection
VRM 8.2 (Voltage Regulator Modules) On-board
• Flexible motherboard design with on-board VRM 8.2, easy to upgrade with future processors. to the SMPS of the computer and/or
System Memory the monitor is correctly wired with ‘live’
• A total of two 168-pin DIMM sockets (3.3V SDRAM types). line on your right hand side. To find
• Memory size up to 512MB. out which line is live (phase) and which
• Supports SDRAM at 66/100 (PC100) MHz. one is neutral, use your multimeter in
• Supports symmetrical and asymmetrical DRAM addressing.
• Banks of different DRAM types and depths can be mixed. 250V AC or higher range. The live line
will show full voltage w.r.t. neutral pin
System BIOS
• 4-Mbit Intel Firmware hub (with security feature). and nearly the same voltage w.r.t. the
• PnP, APM, ATAPI, and Windows 95/98. ground pin, while the neutral pin (w.r.t.
• Full support of ACPI & DMI. ground pin) would/should show very
• Auto-detects and supports LBA hard disks with capacities over 8.4 GB. little voltage (less than 10V AC). Else,
• Easily upgradable by end-user.
the mains wiring has a problem that
On-board I/O
• Supports two PCI-enhanced IDEs PIO mode 3, mode 4, and ultra DMA 33/66 channels needs to be set right.
(optional ultra DMA 66 cable). Twin headers for four IDE devices including IDE HDDs and • Don’t drop any screw or other con-
CDROMs. ducting material on your PC’s
• One ECP/EPP parallel port (via a header). motherboard as that might cause short-
• Two 16550A UART parallel port (via a header).
• One floppy port. Supports two FDDs of 360KB, 720KB, 1.2MB, 1.44MB, or 2.88MB (via a
ing of pins/tracks and consequent dam-
header). age when you switch it ‘on’.
• Four USB ports (via a header, optional). • Make sure that you have a large,
• PS/2 mouse port (via a header, optional). flat surface area to work on. That will
• AT keyboard port (factory option for PS/2 type).
reduce the chances of small screws etc
• Infrared (IrDA) support.
falling and getting lost.
Plug-and-play
• Supports plug-and-play specification 1.1. • While screwing components on to
• Plug-and-play for DOS, Windows 3.X, Windows 95, as well as Windows 98. the chassis, do not use excessive force
• Fully steerable PCI interrupts. as that may damage the screws or their
On-board VGA grooves/holes.
• Hardware motion compensation for S/W MPEG2 decode (DVD).
• 3-D hyper pipelined architecture.
• Full 2-D hardware acceleration. Pentium III technology
• 3-D graphics visual enhancements.
• Dynamic display memory (DDM) or optional 4MB display cache (810DC100 or 810E chipset Some points to be noted about the
version only). Pentium III processor being used here
• Resolution up to 1,600x1,200. are:
• Win 95 vxd, Win 98/NT5 mini-port drivers support.
• VGA port (via a header). • Intel’s Pentium III processors sup-
On-board AC97 Sound port various clock speeds from 450MHz
• Integrated AC97 controller with standard AC97 CODEC. to 933 MHz. The one meant for desktop
• Direct Sound and Sound Blaster compatible. version goes up to 1.13 GHz. (We are
• Full-duplex 16-bit record and playback. using here a 700MHz version.)
• PnP and APM 1.2 support.
• Win 95, 98, and NT drivers ready.
• Integrates P6 dynamic execution
• Line-in, line-out, mic-in and MIDI/game port. architecture and a dual independent bus
Power Management (DIB) architecture.
• Supports SMM, APM and ACPI. • Has a multi transaction system bus.
• Break switch for instant suspend/resume on system operations. • Incorporates Intel’s MMX media
• Energy star ‘Green PC’-compliant. enhancement technology.
• WAKE-ON-LAN (WOL) header support.
• External modem ring-in wake-up support. • Supports Internet streaming
Expansion Slots
single-instruction multiple data (SIMD)
• One audio modem riser (AMR). extensions.
• Four PCI bus master slots (ver 2.1 compliant). • Compared to Pentium II, it has
70 new instructions, enabling advanced
parts list, modify the guidelines men- • Start the assembly only after go- 3-D imaging, streaming audio and video,
tioned here as per the directions given in ing through this article at least once. and speech recognition.
the user’s manual (which is supplied with Only when you feel at ease, start the • Has a 32k (16k for instructions and
the motherboard you may be using), since assembly of your machine as per the another 16k for data) as primary (level
there would be some differences between guidelines included in this article and 1) non-blocking cache for rapid access to
any two makes of the motherboard. the applicable user’s manuals. most heavily used data. In addition, it

ELECTRONICS FOR YOU ❚  JANUARY 2001

 C O N S T R U C T I O N

has 512k unified, non-blocking (level 2)

cache or 256k advanced transfer cache
integrated on die, which runs at the core
frequency of the processor with very low
memory access time.

The motherboard
While the processor is the most impor-
tant part of the motherboard, the
motherboard itself is the most impor-
tant part of the computer system. To-
gether with the chipset, it forms the
brain of your computer.
The modern motherboards do away
with the large number of controller chips
and cards that were used in the older XT
and AT versions, such as clock genera-
tor, bus controller, timer/counter, moni-
tor/printer adopter, FDD and HDD con-
trollers, multi-I/O or super IDE control-
ler card, and DMA controller. All the func-
tions performed by these controllers/
cards (and others) are now performed by
just two or three chips and that too at
much higher speed.
The motherboard based on Intel’s
810/810E chipset (being used in the
present system) combines the advantage
of a multimedia (full-screen, full-motion
video with realistic graphics) and en-
hanced Internet performance at a bud-
Fig. 2: PC Partner motherboard layout diagram get price. With this motherboard, one
does not need separate sound, video, or
TABLE I graphics enhancement cards. A block
diagram of a motherboard employing
JP1, JP2—System Bus Frequency
810E chipset is shown in Fig. 1.
JP1 JP2 CPU Clock Speed
Key features. The main features of
1 Open 1 Open 133MHz (100MHz CPU run at 133MHz Front Side Bus)
the PC Partner motherboard used in this
1 Open 1 1-2 100MHz (66MHz CPU run at 100MHz Front Side Bus) project are shown in the accompanying
1 Close* 1 1-2* Auto* box. A layout diagram showing the rela-
tive position of the jumpers, connectors,
JP15 - BIOS (Firm Ware Hub) major components, PCI slots, and DIMM
Boot Block Protect JP4 - CMOS Clear and CPU sockets is shown in Fig. 2.
JP15 Function JP4 Function Jumper settings. Positions of vari-
1 Close* Unlocked* 1 1-2* Normal ous jumpers within the motherboard are
shown in Fig. 3. The jumper settings
1 Open Locked 1 2-3 CMOS Clear
for enabling various functions are shown
in Table I. Default settings are shown
JP34 - On Board Crystal PCI Sound (Optional) JP29 - Keyboard Power On Select with an asterisk mark. (Note. Leave all
JP34 Function JP29 Function these jumpers in their default setting
1 1-2* Powered by +5V* positions for the present project. The pro-
1 1-2* PCI Sound Enable*
1 2-3 Powered by +5V Standby cessor speed setting is to be done through
1 2-3 PCI Sound Disable (Allows Keyboard Power On) CMOS setup as indicated later.)
* Default settings
JP35, JP36 - On Board AC97 Codec Sound Hardware installation and checkout
JP35 JP36 Function # P = Primary AMR,
1 1-2* 1 2-3* (S)# AC97 Sound Enable* S = Secondary AMR Verifying components. First, carry out
a physical check of all the items as per the
1 2-3 1 1-2 (P)# AC97 Sound Disable
parts list to ensure that there are no ap-

ELECTRONICS FOR YOU ❚  JANUARY 2001


Fig. 3: Jumper positions within motherboard
Fig. 4: Power on/off switch wiring
parent deficiencies and no signs of any
physical damage, and the parts are cor-
rect as indicated by the labels on the items/
packages. For example, the Pentium pro-
cessor pack should comprise Pentium III
processor labeled 700MHz/100MHz sys-
tem bus, fan/heat-sink assembly, and in-
stallation manual with 3-year limited war-
ranty. Similarly, ensure that the 64MB
SDRAM DIMM bears the label (such as
PC100) to indicate that it is compatible
with 100MHz system bus speed.
Checking cabinet and its acces-
sories. The AT mini tower PC cabinet
A Checking SMPS. The control con-
(a)
(b) A DPDT switch as per the diagram pro-
Fig. 5: Installation of Pentium III processor in PGA 370 socket
C O N S T R U C T I O N
measures approx.180mm
(width) x 330mm (height)
x 360mm (depth). The
drive bays comprise two
133.35mm (5.25-inch) ex-
posed, one 89mm (3.5-inch)
exposed, and two 89mm
(3.5-inch) internal bays.
It has 200W SMPS of
VESTA make pre-installed
(+5V @16A, +12V @6A, -
5V @0.5A, and – 12V @0.5A). LEDs with
2-pin SIP connectors are provided for
power ‘on’ (green and white twisted
Fig. 6: DIMM installation
(c)
(d)
ELECTRONICS FOR YOU ❚  JANUARY 2001
wires), HDD (orange and white twisted
wires) activity indication, and to reset
push switch (blue and white twisted
wires), which are required to be con-
nected to the appropriate pin pairs
(Berg type) on the motherboard. (Please
refer Fig. 2 to spot the corresponding
connectors near JP34/JP4, but for the
time being, leave them alone.) An 8-
ohm, 0.5W speaker (with black and red
twisted wires and 4-pin connector), to
go into corresponding 4-pin speaker con-
nector on motherboard, also forms part
of the cabinet.
sole on the cabinet also has a DPDT push-
button switch to switch on the mains
(230V AC) to SMPS of the computer and
a parallel-wired 3-pin AC socket on
SMPS for connecting AC power to the
monitor used with the PC. At this stage,
slide the shielded connectors of the four
power supply wires of the SMPS into
the corresponding connectors on the
vided on the SMPS case (top side). The
same is reproduced in Fig. 4. The white
and black wires have a return path via
blue and brown wires, respectively, when
the power supply switch is flipped ‘on’.
Connect the 3-pin power cord provided
with the cabinet to the socket at the back
of SMPS and plug 3-pin plug into the
socket of the mains supply or the UPS,
as appropriate.
Switch on the SMPS. The fan blower
inside the SMPS should start running,
 C O N S T R U C T I O N

PARTS LIST other, this TABLE IV

Item Description Make forms a 12-pin
Parallel-Port Connector CN6
AT power sup-
AT cabinet with SMPS, power cord, Pin Signal Name Pin Signal Name
power switch, reset switch, speaker, ply connector
LEDs, complete with connectors and with orange 1 Strobe- 14 AFD
installation hardware packet. IMIL, Chennai wire (carrying 2 Data bit 0 15 Error
3 Data bit 1 16 INIT
Motherboard with Intel’s 810 power good
chipset PC Partner, USA along with 4 Data bit 2 17 SLCTIN
signal) ema- 5 Data bit 3 18 GND
user’s manual, CD (containing
drivers for onboard devices) and
nating from 6 Data bit 4 19 GND
headers for motherboard connectors. pin 1. 7 Data bit 5 20 GND
* (refer check-list) PC Partner The volt- 8 Data bit 6 21 GND
Pentium PIII-700 Processor Intel ages on vari- 9 Data bit 7 22 GND
64MB (PC 100)SDRAM (168-pin DIMM) Alpha 10 ACK 23 GND
ous pins of
HDD (hard disk drive) Seagate 11 Busy 24 GND
FDD (floppy disk drive) 3.5” Sony this joint 12- 12 PE 25 GND
CD-ROM drive 52X with audio cable Samsung pin connector 13 SLCT 26 GND
Keyboard Logitech with their
Mouse(3-button) Logitech colour codes are also correct.
Colour Monitor 14” LG
USB connector bracket with 2 headers -
are shown in Motherboard fitment. The chassis
Table II. on which motherboard is to be mounted
*list of connectors/brackets forming part of motherboard.
Check the cor- can be easily removed from the PC cabi-
Header (connectors with cables) for HDD (40-pin twin) - one
Header for FDD (34-pin twin) - one
rectness of net. Unscrew it and gently slide it out
Header for PS/2 mouse - one these voltages from the main casing. Lay it flatly on
Port bracket set with headers for: within the the antistatic workbench (properly
(a) VGA (15-pin ‘D’ connector ending into 16-pin FRC and range as given grounded conductive surface). Mark the
parallel port (25-pin ‘D’ ending into 26-pin FRC) - one in Table II. side facing the keyboard connecter cut-
(b) Com1 and Com2 (two 9-pin ‘D’ ending into 10-pin FRC) - two
(c) Onboard AC97 sound codec (line-in, line-out, mic-in and Then switch out on the chassis.
MIDI/game port ending into 26-pin FRC) - one off the power All motherboards have standard
supply and mounting holes. The hardware supplied
take out the 3- comprises plastic and metallic
indicating availability of +12V supply pin plug from the mains socket. If the motherboard retaining fasteners/screw-
to the fan. Now verify all DC outputs of AT power connector voltages are cor- holders. Metal-type screw-holders are
the SMPS as follows. rect, you can safely assume that volt- better as these have better strength and
There are two distinct 6-pin Molex ages in all other power connectors [4- also these ground the motherboard to
female power connectors with projection pin Molex, carrying +12V (yellow wire) the chassis. You may use four metallic
in the middle. If these are held such followed by two black wires (ground) and screw-holders for the four corner holes
that all black wires are adjacent to each +5V (red wire)] meant for various drives in the motherboard, while the plastic
fasteners may be used for the middle
TABLE II holes of the motherboard.
At Power Connector Pin Voltages Before attempting fitment of the
Pin Voltage Range Wire Pin Voltage Range Wire motherboard, align it on the chassis
Colour Colour such that the keyboard connector on the
1 *P. G. 4.5V (min) Orange 7 Ground - Black motherboard is towards the side marked
2 +5V +5%/-4% Red 8 Ground - Black
3 +12V +5%/-4% Yellow 9 -5V +10%/-8% White
earlier for this purpose. Now fit all the
4 -12V +10%/-9% Blue 10 +5V +5%/-4% Red screw-holders/fasteners, as discussed
5 Ground - Black 11 +5V +5%/-4% Red above, on the chassis, opposite the holes
6 Ground - Black 12 +5V +5%/-4% Red on the motherboard, using Philips
*P. G. = Power good signal which is +5V (delayed, 100ms – 500ms). screws provided in the hardware packet.
Align the
TABLE III motherboard above
VGA– VGA Out Connector CN34* the fasteners and
Pin Signal Name Pin Signal Name push it down, so
1 Red signal 9 NC that the self-retain-
2 Green signal 10 GND ing heads of plastic
3 Blue signal 11 NC fasteners pop out
4 NC 12 Display data channel data
from the respective
5 GND 13 Horizontal sync
6 GND 14 Vertical sync holes. For the me-
7 GND 15 Display data channel clock tallic screw-holders,
8 GND use Philips screws
*This connector is for the VGA display port. Connect a to secure the
VGA or higher resolution display monitor to it. motherboard to the

ELECTRONICS FOR YOU ❚  JANUARY 2001

 C O N S T R U C T I O N

TABLE V considerable force to engage it into the TABLE VIII

COM1/COM2– Serial Connectors CN4*, CN5* projection. You may use the flat
IDE Connector Pin Definitions (J18, J19)
Pin Signal Name Pin Signal Name screwdriver tip to do this, but be care-
ful that screwdriver does not slip and Pin Function Pin Function
1 DCD 6 DSR
damage the tracks on the motherboard 1 Reset IDE 2 GND
2 SIN 7 RTS
3 SOUT 8 CTS [refer Fig. 5(d)]. 3 Host data 7 4 Host data 8
4 DTR 9 RI 5 Host data 6 6 Host data 9
6. Connect the 3-pin fan connector 7 Host data 5 8 Host data 10
5 GND 10 NC
to the corresponding connector CN17 9 Host data 4 10 Host data 11
*These connectors are for the serial port marked ‘CPU Fan’ on the motherboard. 11 Host data 3 12 Host data 12
bracket. Both connectors have the same pin-
outs. DIMM installation (Fig. 6). There 13 Host data 2 14 Host data 13
are two 168-pin SDRAM DIMM sockets 15 Host data 1 16 Host data 14
17 Host data 0 18 Host data 15
TABLE VI 19 GND 20 Key
21 DRQ3 22 GND
Audio & Game Port Pin Header CN341*
23 I/O Write- 24 GND
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name 25 I/O Read- 26 GND
1 VCC 8 GND 15 NC 22 MIC-in 27 IOCHRDY 28 BALE
2 VCC 9 XTD 16 VCC 23 NC 29 DACK3- 30 GND
3 SWC 10 GND 17 Line-out 24 GND 31 IRQ14 32 IOCS16-
4 SWA 11 SWB 18 Line-out 25 Line-in 33 Addr 1 34 GND
5 XTC 12 XTB 19 GND 26 Line-in 35 Addr 0 36 Addr 2
6 XTA 13 MSIN 20 GND 37 Chip select 0 38 Chip select 1-
7 MSOUT 14 SWD 21 MIC-in 39 Activity 40 GND
*This header is for the audio port bracket. It connects audio ports-stereo line-out, stereo line-in
DIMM with the corresponding keys in
and microphone—and a game port (for a joystick or MIDI device) to your system.
the socket.
chassis firmly without using excessive on the motherboard with socket 1 3. Push the DIMM vertically down,
force. marked ‘1’ and socket 2 left unmarked. inserting its bottom edge into the
Pentium processor mounting (re- The two sockets can together accept socket.
fer Fig. 5). The processor is to be fitted 512MB SDRAM (i.e. up to 256 MB each). 4. Once seated properly, push DIMM
into the PGA370 (pin grid array with We propose to install a single 64MB down from the top edge until the re-
370-pin recesses) socket, which is a ZIF DIMM, which is
(zero insertion force) socket. Take out quite adequate
the processor and its heat sink fitted for current type
with cooling fan and heat sink retainer of applications. It
clip ‘D’. Now proceed as follows: can be inserted
1. Lift handle ‘A’ to its vertical posi- into any of the
tion [refer Fig. 5(a)]. two sockets and
2. Align the processor pins with the the same will be
socket holes and insert the processor automatically
into its socket [refer Fig. 5(b)]. suitably config-
3. With the processor in its socket, ured during
lower handle ‘A’ and bring it to its closed setup. Remove
(horizontal) position [refer Fig. 5(c)]. the DIMM from
4. Orient the heat sink (with fan on its anti-static en-
top) such that the depression on one velope, holding it
side of the heat sink matches the corre- by its edges. Pro-
sponding projection on PGA370 socket, ceed as follows:
and place it (along with fan) over the 1. Using fin-
processor [refer Fig. 5(c)]. gertips, push the
5. On the PGA370 socket, there are retainer clips on
two small projec- either side of the
TABLE VII tions on opposite DIMM socket
CN7: USB Port sides, in which the slightly away
Pin Assignment heat sink clip has to from the socket.
1 VCC be inserted. While 2. Position
2 GND it is fairly easy to the DIMM to be
3 USBP1-
insert one side, it is installed above
4 USBP0+
5 USBP1+ rather tricky to in- the socket, align-
6 USBP0- sert the left-out ing the two small
7 GND side as it needs to notches at the
8 VCC be pulled down with bottom edge of

ELECTRONICS FOR YOU ❚  JANUARY 2001

 C O N S T R U C T I O N

TABLE IX TABLE X have a notch and the corresponding pro-

Floppy Connector Pin Definitions (JP26) PS/2 Mouse Connector* jection, which serves as a key so that
Pin Function Pin Function
they can go only the correct way. The
Pin Description Pin Description
cables used for the drives have an addi-
1 GND 2 FDHDIN 1 Mouse data 2 NC
3 Ground 4 +5V
tional connector in the middle (for slave
3 GND 4 Reserved
5 Key 6 FDEDIN 5 Mouse clock 6 NC in case of HDD and drive B in case of
7 GND 8 Index- *This connector is for the optional PS/2 mouse FDD, which will be explained later). Us-
9 GND 10 Morot enable port bracket. ing the tips given here, you can install
11 GND 12 Drive select B- the motherboard end of the following
13 GND 14 Drive select A- reset switch, and the speaker), would cables:
15 GND 16 Motor enable be completed after the motherboard • 16-pin VGA connector CN34 (re-
17 GND 18 DIR-
chassis is screwed back into the PC case. fer Table III).
19 GND 20 STEP-
21 GND 22 Write data- The cables to be connected to the • 26-pin parallel-port connector CN6
23 GND 24 Write gate- FRC-type male connectors/headers on (refer Table IV).
25 GND 26 Track 00- the motherboard are listed below, and • 10-pin serial/com ports 1 and 2,
27 GND 28 Write protect- the pin assignments are shown in the CN4 and CN5 (refer Table V).
29 GND 30 Read data- referred tables. On the motherboard, • 26-pin sound cable connector CN31
31 GND 32 Side 1 select-
normally, only start pin 1 is indicated. (refer Table VI).
33 GND 34 Diskette
In an FRC connector, all odd number • 8-pin USB connector CN7 (refer
tainer clips snap into place and the pins are in one row while even number Table VII).
DIMM is firmly held into its position. pins are in the opposite row; pin 2 is • 40-pin IDE-1 connector for HDD/
Cable set installation. While the opposite pin 1, pin 4 is opposite pin 3, CD-ROM drive CN1 (refer Table VIII).
motherboard chassis is still not replaced and so on. • 34-pin FDD connector CN3 (refer
into the case, you could install one of Pin 1 on the mating FRC female con- Table IX).
the ends of all the cables originating nector can be identified by an arrow • 6-pin PS/2 mouse connector CN8
from the motherboard. The installation mark over it. Ribbon cable wire going (refer Table X).
of cables, which originated from SMPS into pin 1 is of red (sometimes blue)
and the control panel of the case (LEDs, colour. Some of the FRC connector pairs Stay tuned for the concluding part in next issue

ELECTRONICS FOR YOU ❚  JANUARY 2001

 CONSTRUCTION

AUTOMATIC ROOM LIGHT

ing resistor that keeps the IR LEDs,
current within the required range.
IR detector modules. The IR detec-

CONTROLLER
tor modules used in the circuit are com-
NA monly available in the market. These
ANJA
I & RUP
ED
DWIV PARTS LIST
S.C.
Semiconductors:
REJO G. PAREKKATTU IC1, IC2, IC3 - NE555, timer
IC4 - 74LS192, up/down decade
counter
IC5 - 74LS85, 4-bit magnitude

U
sually, when we enter our room triggered first and then activates an up/ comparator)
in darkness, we find it difficult down counter accordingly. The BCD out- IC6 - 7447, BCD to 7-segment
decoder/driver
to locate the wall-mounted put of the counter, at any time, repre- IC7 - MCT2E, opto-coupler
switchboard to switch ‘on’ the light. For a sents the number of persons inside the IC8 - 7805, +5V regulator
stranger, it is tougher still as he has no room. The output of the up/down counter IC9(N1-N4) - 74LS00, quad 2-input
knowledge of the correct switch to be is decoded by 7-segment decoder/driver NAND gate
IC10(N5-N10) - 74LS14, hex schmitt
turned on. Here is a reliable circuit that and displayed on 7-sement display. Si- inverter gate
takes over the task of switching ‘on’ and multaneously, the output of counter is T1, T2 - BC548, npn transistor
switching ‘off’ of the light(s) automatically compared by 4-bit magnitude compara- T3 - SL100, npn transistor
when somebody enters or leaves the room tor. D1-D3 - IN4001, rectifier diode
IRLED1, IRLED2 - Infrared LED
during darkness. This circuit has the fol- The output of comparator remains
Resistors (all ¼-watt, ±5% carbon, unless
lowing salient features: high as long as BCD output of counter is stated otherwise):
• It turns on the room light when- greater than zero. A logic gate is used to R1 - 3.3-kilo-ohm
ever a person enters the room, provided initiate energisation of a relay to switch R2 - 10-kilo-ohm
that the room light is insufficient. If more ‘on’ the light when comparator output is R3 - 100-ohm
R4, R5, R21 - 1.2-kilo-ohm
than one person enters the room, say, one high and it is dark outside. R6, R7, R12 - 33-kilo-ohm
after the other, the light remains ‘on’. R8, R9 - 180-kilo-ohm
• The light turns ‘off’ only when the R10, R11 - 1-kilo-ohm
room is vacant, or, in other words, when
The circuit R13-R19 - 470-ohm
R20 - 100-kilo-ohm
all the persons who entered the room have The detailed section-wise description of VR1 - 10-kilo-ohm preset
left. the circuit shown in Fig. 2 is as follows:
Capacitors:
• A 7-segment display shows the num- IR transmitter. The IR transmitter C1 - 0.001µF, ceramic disk
ber of persons currently inside the room. circuit consists of an astable multivibrator C2, C3, C4 - 0.01µF, ceramic disk
• The circuit is resistant to noise and built around NE555 timer IC1. The out- C5, C6 - 4.7µF, 16V electrolytic
errors since the detection is based on in- put of IC1 at pin 3 is a rectangular wave- C7, C8 - 10µF, 16V electrolytic
C9 - 1µF, 16V electrolytic
frared light beams. form of around 36kHz frequency. This out-
Miscellaneous:
• The circuit uses commonly avail- put is used to drive two IR LEDs, which M1, M2 - IR sensor modules
able components and is easy to build and transmit modulated IR light at 36kHz fre- DS1 - LT542 (common anode
test. quency. Modulating frequency of 36 kHz display)
The functional block diagram of the is used because the IR receiver modules RL1 - 12V, 200 ohm, 2 C/O.
LDR1 - LDR (Dark resistance >
circuit is shown in Fig.1. It comprises used in this circuit respond to IR signals 120 kilo-ohm)
36kHz IR transmitter, two IR detector modulated at 36kHz frequency. The L1 - 230V, 100W electric bulb
modules, two monostable multivibrators, multivibrator frequency can be correctly - 12V power supply
up/down-counter, 4-bit magnitude com- adjusted with the help of preset VR1 (10 - Printed circuit board
- IC sockets
parator, 7-segment decoder display, kilo-ohm). Resistor R3 is a current limit-
light sensor, and relay driver.
Two pairs of IR transceivers are
employed in order to detect whether
the person is entering or leaving the
room. When a person enters the room,
IR detector 1 gets triggered, followed
by triggering of IR detector 2. Con-
versely, when a person leaves the
room, IR detector 2 gets triggered, fol-
lowed by triggering of IR detector 1.
A priority detector circuit deter-
mines which of the two detectors is Fig. 1: Block diagram of automatic room light

ELECTRONICS FOR YOU ❚  JANUARY 2001

 CONSTRUCTION

Fig. 3: Timing waveforms

have three terminals for ters or leaves the room, the infrared light
Vcc (+5V, here), ground, beams are interrupted one-by-one and the
and the output signal, output of each IR sensor module, in turn,
respectively. In the nor- goes high, which results in conduction of
mal state, the output associated transistors T1 and T2. Which
pin (pin 3) of this de- transistor will turn ‘on’ first depends on
tector remains at high whether the person is entering or leaving
state, and when an IR the room.
light of correct modulat- In the circuit, two NE555 timer ICs
ing frequency is de- (IC2 and IC3) wired as monostable
tected, its output pin multivibrators are used. The pulse width
goes low. The pin con- of the output waveform (on time) for these
figuration of the IR multivibrators is fixed at about 0.9 sec-
modules may vary from onds by suitably selecting the values for
one manufacturer to the the timing capacitors C5 and C6 in con-
other. (Pin configura- junction with their associated resistors R8
tion of module TSOP and R9. These monostable multivibrators
1136 for 36 kHz used get triggered when their trigger input pins
by EFY is shown in Fig. (pin 2) go low. Thus the multivibrators
Fig. 2: Schematic diagram of automatic room light controller

2.) (Articles based on are triggered only when the IR light

the IR sensor module beams are interrupted. Although the out-
have been published in put pulse width of both the multivibrators
Nov. 2000 and some is approximately the same, there is, how-
other previous issues of ever, a phase difference corresponding to
EFY. Readers may re- the elapsed time between the successive
fer the same for more interruptions of the IR beams. Refer to
information about the the waveforms shown in timing diagram
module.) of Fig. 3.
Since the IR trans- Priority-detector logic circuit. The
mitter in this circuit is priority detector circuit uses three NAND
continuously ‘on’, emit- gates, five inverter gates, and two
ting IR light, in the nor- differentiators. The timing diagram given
mal condition, the out- in Fig. 3 helps in understanding as to
put pins of both IR mod- how the priority-detector circuit detects a
ules will be at low state. person going out of the room.
Therefore transistors T1 At first the outputs from the
and T2 will remain cut- monostable multivibrators are NANDed
off. When a person en- by gate N1 and its polarity is inverted

ELECTRONICS FOR YOU ❚  JANUARY 2001


Fig. 4: Actual-size, single-sided PCB layout for the circuit
again by gate N7. At the same time, the
outputs of monostable IC3 and IC2 get
differentiated by the capacitor-resistor
combinations of C7-R10 and C8-R11, re-
spectively. Each differentiated output is
passed via Schmitt inverter pairs of N5-
N6 and N10-N9 to convert the differenti-
ated pulses into rectangular pulses. The
rectangular pulses obtained at the out-
put of gates N6 and N9 are again
Fig. 5: Component layout for PCB
CONSTRUCTION
NANDed with the output of gate N7 in
NAND gates N2 and N3, respectively.
The rectangular pulse at pin 4 of NAND
gate N2 ends before the output of gate
N7 goes high and hence the output of
NAND gate N2 stays high, while both
inputs to NAND gate N3 are simulta-
neously high for the duration of rectan-
gular output of gate N9. As a result, the
output of gate N3 applied to countdown
ELECTRONICS FOR YOU ❚  JANUARY 2001
clock pin 4 of IC4 causes the counter to
count down on its trailing edge (low-to-
high transition) and the output count goes
down by one count.
Similarly, when a person enters the
room, pin 4 of counter IC4 remains high,
while its pin 5 (count up) gets a low-
going pulse resulting into counter output
advancing by one count. Values of ca-
pacitors C7 and C8 and resistors R10
and R11 can be varied for optimum per-
formance. (Lab note. The component val-
ues have already been optimised and
logic circuit is suitably modified for
highly reliable performance of this part
of the circuit, after considerable effort.)
Up/down counter. Up/down decade
counter 74LS192 (IC4) is used as the
counter. When the power is turned ‘on’,
its outputs Q0 through Q3 are in the low
state. Whenever a person enters the
room, a low-going pulse is applied at its
count-up pin 5, while its count-down pin
4 is held at logic 1 and its output count
advances by one. Similarly, when the per-
son leaves the room, a similar pulse is
applied at its countdown input (pin 4)
while its countup pin 5 is held at logic 1
and its output decreases by one. Thus
the 4-bit output always represents the
number of persons still inside the room.
The output of the decade counter is con-
nected to 7-segment decoder/driver IC6
(7447) that displays the number on com-
mon-anode 7-segment LED display
(LT542).
Magnitude comparator. The output
of the up/down counter is also applied to
4-bit magnitude comparator that acts as
zero detector, i.e. it detects whether the
number of persons inside the room is
greater than zero or not. The 4-bit out-
put of the decade counter is always com-
pared with a reference 4-bit number
(0000), and if a match occurs, the output
at pin 5 (P>Q) of the comparator goes
low to represent an ‘empty room’ condi-
tion. In all other cases (when the num-
ber of persons in the room is greater
than zero), P>Q output will be at high
state. This output is given as one of the
inputs to NAND gate N4 (followed by
inverter gate N8). Thus, as long as the
room is not empty, one of the inputs to
N4 gate will be high.
The second condition for the light to
get switched ‘on’ is yet to be satisfied.
Whether there is sufficient light in the
room or not is checked by the light sen-
sor circuit.

Light sensor. The light sensor is
wired around the opto-coupler MCT2E.
The resistance of the LDR depends upon
the amount of light in the room. An LDR
with resistance below 5 kilo-ohm in nor-
mal light and more than 120k resistance
in darkness is required. When there is
sufficient ambient light, the transistor in-
side the opto-coupler is turned ‘on’ and
the input of NAND gate (pin 3) is driven
to low state. Thus the output of NAND
gate remains at high state and that of
inverter gate N8 at low. However, when
the light is insufficient, the resistance of
the LDR increases, turning off the tran-
sistor inside the opto-coupler. The sensi-
tivity can be controlled by adding a high-
valued variable resistance (about 680k)
across the LDR.
When both conditions are satisfied
(that is one or more persons are inside
the room and the ambient light is insuffi-
cient), the output of NAND gate goes ‘low’
and that of inverter gate N8 goes ‘high’
to turn on transistor T3, thereby
energising relay RL1. A 230V, 100W elec-
tric bulb is connected via the relay to the
CONSTRUCTION
AC mains. Once the relay gets energised,
the LDR is effectively removed from the
circuit (since the LDR is connected to the
N/C contact of the two pole relay) to pre-
vent the flickering of the lamp with chang-
ing resistance of the LDR.
Assembly and testing
The full circuit, with the exception of the
IR transmitter, can be assembled on a
single general-purpose PCB. However, an
actual-size, single-sided PCB for the cir-
cuit in Fig. 2 is shown in Fig. 4. The com-
ponent layout for the PCB is shown in
Fig. 5.
The receiver-transmitter pairs are
placed about a metre apart as shown in
Fig. 6. The distance between the two sen-
sors (receiver modules) is about 40 cm. A
steel pipe of 5mm diameter and 3cm
length can be placed in front of the IR
module in order to improve its directiv-
ity. After assembling the circuit, adjust
preset VR1 (10k) until pin 3 of both the
IR sensor modules go high (5V). If the
circuit still does not function properly, ad-
ELECTRONICS FOR YOU ❚  JANUARY 2001
Fig. 6: Proposed layout of IR transmitter
and receiver pairs
just the distance between the sensors. The
metal cabinets of the IR modules must be
connected to ground.
Note that the circuit works with a
regulated +5V supply, except the power
supply to the relay coil. The circuit has
no off-time memory, and so its working is
interrupted during power failure.
Another disadvantage is that the cir-
cuit can count only up to 9. But it is quite
unusual to have more than nine people
in a normal living room.
Take care about the IR sensor mod-
ule pin connections. It may be damaged if
connected wrongly. ❏
February

2001
Circuit Ideas

2001

9-LINE TELEPHONE SHARER
DHURJATI SINHA
T
his circuit is able to handle nine
independent telephones (using a
single telephone line pair) lo-
cated at nine different locations, say,
up to a distance of 100m from each
other, for receiving and making outgo-
ing calls, while maintaining conversa-
tion secrecy. This circuit is useful when
a single telephone line is to be shared
by more members residing in different
rooms/apartments.
Normally, if one connects nine
phones in parallel, ring signals are
CIRCUIT IDEAS
DWIV
EDI
S.C.
heard in all the nine telephones (it is
also possible that the phones will not
work due to higher load), and out of
nine persons eight will find that the call
is not for them. Further, one can over-
hear others’ conversation, which is not
desirable. To overcome these problems,
the circuit given here proves beneficial,
as the ring is heard only in the desired
extension, say, extension number ‘1’.
For making use of this facility, the
calling subscriber is required to initially
dial the normal phone number of the
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
called subscriber. When the call is estab-
lished, no ring-back tone is heard by the
calling party. The calling subscriber has
then to press the asterik (*) button on
the telephone to activate the tone mode
(if the phone normally works in dial mode)
and dial extension number, say, ‘1’, within
10 seconds. (In case the calling subscriber
fails to dial the required extension num-
ber within 10 seconds, the line will be
disconnected automatically.) Also, if the
dialed extension phone is not lifted within
10 seconds, the ring-back tone will cease.
The ring signal on the main phone
line is detected by opto-coupler MCT-
2E (IC1), which in turn activates the
10-second ‘on timer’, formed by IC2
(555), and energises relay RL10 (6V, 100-
ohm, 2 C/O). One of the ‘N/O’
contacts of the relay has been
used to connect +6V rail to the
processing circuitry and the
other has been used to provide
220-ohm loop resistance to de-
energise the ringer relay in
telephone exchange, to cut off
the ring.
When the caller dials the
extension number (say, ‘1’) in
tone mode, tone receiver
CM8870 (IC3) outputs code
‘0001’, which is fed to the 4-
bit BCD-to-10 line decimal de-
coder IC4 (CD4028). The out-
put of IC4 at its output pin
14 (Q1) goes high and
switches on the SCR (TH-1)
and associated relay RL1. Re-
lay RL1, in turn, connects, via
its N/O contacts, the 50Hz ex-
tension ring signal, derived
from the 230V AC mains, to
the line of telephone ‘1’. This
ring signal is available to tele-
phone ‘1’ only, because half
of the signal is blocked by di-
ode D1 and DIAC1 (which do
not conduct below 35 volts).
As soon as phone ‘1’ is
lifted, the ring current in-
creases and voltage drop
across R28 (220-ohm, 1/2W re-
sistor) increases and operates
opto-coupler IC5 (MCT-2E).
This in turn resets timer IC2
causing:
(a) interruption of the
power supply for processing
circuitry as well as the ring
 CIRCUIT IDEAS

ELECTRONIC CARD RUP

ANJA
NA no.
TABLE I
Appliance LDR2 LDR3 LDR4 LDR5

LOCK SYSTEM
1 - * * *
2 * - * *
3 - - * *
4 * * - *
PRIYANK MUDGAL 5 - * - *
6 * - - *
7 - - - *

T
his circuit of electronic card lock A 40W bulb illuminates LDR1 to 8 * * * -
system is much simpler and LDR5 constantly. This pulls down bases 9 - * * -
cheaper than other similar cir- of transistors T1 through T5 to ground. 10 * - * -
11 - - * -
cuits that have appeared in earlier issues LDR1 ensures that card is properly in- 12 * * - -
of EFY. serted into the card slot. 13 - * - -
The circuit is configured around an When the card is correctly inserted, 14 * - - -
addressable 1 of 16 demultiplexer it covers the hole/opening for LDR1 and 15 - - - -
CD4514B (IC1). Any number in binary thus blocks the light from falling on LDR1. - Blocked hole corresponding to selected bi-
form, when available at input pins 2, 3, As a result, transistor T1 conducts and nary address.
* Punched holes corresponding to LDR po-
21, and 22 (address pins A0 through A3), extends positive supply to the collectors sition on card
makes corresponding output go logic high, of transistors T2 through T5. Then, de-
thus turning on the appliance through re- pending upon the holes blocked/punched
lay contacts. Up to 15 appliances can be in the inserted card, any combination of switch on the corresponding appliance
switched on/off (one at a time). Output emitters of transistors T2 through T5 (one out of 15).
Q0 (pin 11) can be used for visual indica- turns logic ‘high’ (transistors’ output cor- The card used should be of opaque
tion, to show that circuit is active. responding to blocked LDRs only goes plastic. It should be able to withstand
some heat from the bulb, even though
the appliance remains ‘on’ only for the
period for which the card is in the slot.
The card has a triangular notch that
shows correct orientation/direction of in-
sertion of card and prevents false opera-
tion. LDRs can be placed in a line, or
randomly, to increase security.
The order in which holes should be
punched for each appliance is given in
Table I.
Two illus-
trations,
one each
for card-2
and card-5,
are shown
in the ac-
company-
ing figures.
An eleva-
tion and
‘high’). plan/top
These out- view of the
puts con- gadget is
nected to ad- also shown
dress input in the fig-
pins A0 ures.
through A3
of IC1

ELECTRONICS FOR YOU ❚  FEBRUARY 2001


PULSED OPERATION OF A
CW LASER DIODE
DR. ALIKA KHARE
H
ere a simple low-cost technique
for converting a CW laser di-
ode at 670 nm wavelength to
pulsed laser up to a frequency of 500 kHz.
A low-power pulsed radiation source
is very important for any laboratory in-
volved in optical pulsed systems—laser,
pulsed discharges, optical communication,
fibre-optic sensors, image processing,
etc—where one is required to check the
frequency response of the detection sys-
tem or optical simulation of an optical
source or local networking using optical
fibre cable. Fast-speed LED offers the so-
lution for such requirements, but because
of very low power and large divergence,
its use remains limited. On the other
hand, a pulsed diode laser offers a very
good solution for this problem.
Commercial systems are usually ex-
pensive. However, a CW diode laser oper-
ating at 670 nm can easily be pulsed up
to a frequency of 500kHz with low-cost
technique, using a function generator and
CIRCUIT IDEAS
its maximum amplitude). Above 3V, prob-
ably population inversion is developed
much above threshold, before the laser os-
EDI cillations build up into the cavity, and so
.C. DWIV
S we observe the sharp peak in laser output
(for more details, refer Laser Fundamen-
tals book by W. T. Silfvast, published by
Cambridge University Press), exponen-
an inexpensive push-pull amplifier inter- tially decaying to a steadystate value
face circuit. The block diagram of the sys- with a time constant depending on the
tem is shown in Fig. 1. initial peak intensity and the carrier life
A 3mW CW diode laser at 670 nm time in the excited state. After the input
with voltage and current rating of 3V at pulse is over, the oscillations die down
100mA, respectively, is used. The source within 5 µs.
(a function generator) is capable of deliv- Therefore above 3V, up to a frequency
ering square pulses of 3V ampli-
tude, which are amplified by a
complementary symmetry push-
pull circuit shown in Fig. 2.
The output of the amplifier
is connected to the diode laser
for pulsed operation. The laser
is focused onto a
photodiode termi-
nated with 50-
ohm resistor (Fig.
1). The output of
photodiode is dis-
played on digital
storage oscillo-
scope
and it is
also connected to the
PC for getting a hard
copy.
Up to a frequency
of around 20 kHz, the
threshold voltage for
laser oscillations is
around 2.4V. For fre-
quencies greater than
20 kHz, the threshold
for laser oscillations
depends on the operat-
ing frequency and is
higher than 2.4V. The
behaviour of laser pulses up to 10 kHz is of 10 kHz, the laser is operated in quasi
nearly similar. Laser output at a typical CW mode. In the frequency range of 10
frequency of 2 kHz is shown in Fig. 3, at kHz to 50 kHz, the laser output keeps on
various voltages (2.6V, 3.4V, and 4V). The increasing, even during the flat portion of
input waveform ‘A’ is shown at the bot- the input current pulse, and falls down to
tom of the figure. zero during the off period of the driving
For a driving pulse of about 3V (which pulse. Fig. 4 shows the laser waveforms
is the normal operating voltage for CW at 50 kHz, 100 kHz, 200 kHz, 300 kHz,
operation), the laser pulse becomes flat and 500 kHz, respectively.
after a delay of approximately 40 µs (time All these pulses were recorded at
taken to build up the laser oscillations to around 4V. In this range of frequencies,
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
 CIRCUIT IDEAS

the duration for which voltage is on/off is
of the order of less than 5 µs, and so the
driving pulses switch off before the ter-
mination of laser oscillations. Therefore
the laser output shows a modulation with
the DC component in it. Beyond 500 kHz,
it is difficult to observe laser oscillations
even at voltages higher than 4V.
Lab note. Tests conducted at EFY
using laser diode of laser torch (rated
for <5mW) with identical inputs at 2 kHz
did not show any marked departure of
output waveform (square wave) from the
input square wave.

ELECTRONICS FOR YOU ❚  FEBRUARY 2001


GENERATION OF 1-SEC. PULSES
SPACED 5-SEC. APART
PRAVEEN SHANKER
T
his circuit using a dual-timer
NE556 can produce 1Hz pulses
spaced 5 seconds apart, either
manually or automatically. IC NE556
comprises two independent NE555 tim-
ers in a single package. It is used to
produce two separate pulses of differ-
ent pulse widths, where one pulse
initiates the activation of the second
pulse.
The first half of the NE556 is wired
for 5-second pulse output. When slide
switch S2 is in position ‘a’, the first timer
is set for manual operation, i.e. by press-
CIRCUIT IDEAS
RUP
ANJA
NA
ing switch S1 momentarily
you can generate a single pulse of 5-
second duration. When switch S2 is
kept in ‘b’ position, i.e. pins 6 and 2 are
shorted, timer 1 in NE556 triggers by
itself.
The output of the first timer is con-
nected to trigger pin 8 of second timer,
which, in turn, is connected to a poten-
tial divider comprising resistors R4 and
R5. Resistor R1, preset VR1, resistor R2,
preset VR2, and capacitors C2 and C5
are the components determining time pe-
riod. Presets VR1 and VR2 permit trim-
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
ming of the 5-second and 1-second pulse
width of respective sections.
When switch S2 is in position ‘a’ and
switch S1 is pressed momentarily, the out-
put at pin 5 goes high for about 5 sec-
onds. The trailing (falling) edge of this 5-
second pulse is used to trigger the second
timer via 0.1µF capacitor C6. This action
results in momentarily pulling down of
pin 8 towards the ground potential, i.e.
‘low’. (Otherwise pin 8 is at 1/2 Vcc and
triggers at/below 1/3 Vcc level.) When the
second timer is triggered at the trailing
edge of 5-second pulse, it generates a 1-
second wide pulse.
When switch S2 is on position ‘b’,
switch S1 is disconnected, while pin 6 is
connected to pin 2. When capacitor C is
charged, it is discharged through pin 2
until it reaches 1/3Vcc potential, at which
it is retriggered since trigger pin 6 is
also connected here. Thus timer 1 is
retriggered after every 5-second period
(corresponding to 0.2Hz frequency). The
second timer is triggered as before to
produce a 1-second pulse in synchro-
nism with the trailing edge of 5-sec-
ond pulse.
This circuit is important wherever
a pulse is needed at regular intervals;
for instance, in ‘Versatile Digital Fre-
quency Counter Cum Clock’ construc-
tion project published in EFY Oct. ’97,
one may use this circuit in place of
CD4060-based circuit. For the digital
clock function, however, pin 8 and 12
are to be shorted after removal of
0.1µF capacitor and 10-kilo-ohm resis-
tors R4 and R5.

HIGH-/LOW-VOLTAGE
CUTOUT WITH TIMER
DR D.K. KAUSHIK
T
his inexpensive circuit can be
connected to an air-conditioner/
fridge or to any other sophisti-
cated electrical appliance for its protec-
tion. Generally, costly voltage stabilisers
are used with such appliances for main-
taining constant AC voltage. However,
due to fluctuations in AC mains supply,
a regular ‘click’ sound in the relays is
heard. The frequent energisation/de-
energisation of the relays leads to elec-
trical noise and shortening of the life of
electrical appliances and the relay/
stabiliser itself. The costly yet fault-
prone stabiliser may be replaced by this
inexpensive high-low cutout circuit with
timer.
The circuit is so designed that relay
RL1 gets energised when the mains volt-
age is above 270V. This causes resistor
R8 to be inserted in series with the load
and thereby dropping most of the volt-
age across it and limiting the current
through the appliance to a very low
value.
If the input AC mains is less than 180
volts or so, the low-voltage cut-off circuit
interrupts the supply to the electrical
appliance due to energisation of relay
CIRCUIT IDEAS
EDI
.C. DWIV
S off when the input supply is less than
RL2. After a preset time delay of one
minute (adjustable), it automatically tries
again. If the input AC mains supply is
still low, the power to the appliance is
again interrupted for another one minute,
and so on, until the mains supply comes
within limits (>180V AC). The AC mains
supply is resumed to appliance only when
it is above the lower limit.
When the input AC mains increases
beyond 270 volts, preset VR1 is adjusted
such that transistor T1 conducts and
relay RL1 energises and resistance R8
gets connected in series with the elec-
trical appliance. This 10-kilo-ohm, 20W
resistor produces a voltage drop of ap-
proximately 200V, with the fridge as
load.
The value and wattage of resistor
R8 may be suitably chosen according to
the electrical appliance to be used. It is
practically observed that after continu-
ous use, the value of resistor R8 changes
with time, due to heating. So adjust-
ment of preset VR1 is needed two to
three times in the beginning. But once
it attains a constant value, no further
adjustment is required. This is the only
adjustment required in the beginning,
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
which is done using a variac.
Further, the base voltage of transis-
tor T2 is adjusted with the help of pre-
set VR2 so that it conducts up to the
lower limit of the input supply and cuts
this limit (say, 180V). As a result, tran-
sistor T3 remains cut off (with its col-
lector remaining high) until the mains
supply falls below the lower limit, caus-
ing its collector voltage to fall. The col-
lector of transistor T3 is connected to
the trigger point (pin 2) of IC1.
When the input is more than the
lower limit, pin 2 of IC1 is nearly at
+Vcc. In this condition the output of
IC1 is low, relay RL2 is de-energised
and power is supplied to the appliance
through the N/C terminals of relay RL2.
If the mains supply is less than the
lower limit, pin 2 of IC1 becomes mo-
mentarily low (nearly ground potential)
and thus the output of IC1 changes state
from ‘low’ to ‘high’, resulting in
energisation of relay RL2. As a result,
power to the load/appliance is cut off.
Now, capacitor
C2 starts charg-
ing through re-
sistor R6 and
preset VR3.
When the ca-
pacitor charges
to (2/3)Vcc, IC1
changes state
from ‘high’ to
‘low’. The value
of preset VR3
may be so ad-
justed that it
takes about one minute (or as desired)
to charge capacitor C1 to (2/3)Vcc. Re-
lay is now de-energised and the power
is supplied to the appliance if the mains
supply voltage has risen above the lower
cut-off limit, otherwise the next cycle
repeats automatically.
One additional advantage of this cir-
cuit is that both relays are de-energised
when the input AC mains voltage lies
within the specified limit and the nor-
mal supply is extended to the appliance
via the N/C contacts of both relays.
Construction

2001
 CONSTRUCTION

BUILD YOUR OWN

RA The HDD can now be installed at
UND
N. K the lowest closed (without any cutout
in front) position in the drive bay. Se-

PENTIUM III PC PART-II

cure it like the other drives using four
Philips screws.
• Completing the hardware in-
stallation. After having completed the
installation of drives and the cable set
K.C. BHASIN AND NEERAJ KUNDRA of the motherboard, install back the as-
sembled motherboard chassis (complete
with its cable/connector set)
• Installation of drives in drive’s into the PC cabinet and
bay. Before proceeding with the physi- then complete the cabling
cal installation of CD-ROM drive, hard as follows.
disk drive, and floppy drive in the You may start with AT
drive’s bay, you have to plan their con- power supply connectors.
figuration. We propose to use only one By now you are familiar
floppy drive. This drive will be config- with two 6-pin Molex con-
ured as floppy drive ‘A’. The 34-pin nectors from SMPS used
floppy drive cable end with twisted Fig. 7: Floppy drive cable for connecting up to two FDDs for powering the
wires, emanating from CN3 on the motherboard (refer paragraph under
motherboard, needs to be connected to heading ‘Checking SMPS’ in Part I).
floppy drive (DS1 in Fig.7). Take connecter with orange wire (PG
Let us configure the HDD as pri- signal) first and align it over pin 1 of
mary master and CD-ROM drive as pri- PW1 connector on motherboard. Pro-
mary slave using a single cable ema- jections on Molex connector of SMPS
nating from CN1 (IDE-1 header) on the would engage into corresponding holes
motherboard (refer Fig. 8). (We could in PW1 connector. Once you have en-
alternatively configure CD-ROM drive gaged the connector in this fashion,
as secondary master and connect it di- make it vertical and then simply slide
rectly to CN2 (IDE-2 connector) in it down. It will snap into its position.
motherboard, using another 40-pin (Be careful not to bend the pins and
cable/connector.) ensure that you have not engaged the
The jumper on HDD should be used wrong pins.) Similarly, insert the other
Fig. 8: Connection of HDD and CD-ROM drive
to short pins 7 and 8 on the jumper using IDE-1 header 6-pin Molex connector in the adjacent
block at the rear of HDD (refer Fig. 9). pins of AT power connector. On in-
Similarly, there is a jumper block at not be allowed to go more than 3.5 mm stallation, all black coloured wires will
the rear of CD-ROM drive with the pairs into the threaded holes. be adjacent to each other.
of pins marked as CS (cable select), SL Suitable cutout also exists in the Some of the connectors originating
(slave), and MA (master). Ensure that drive bay for installing the 8.9cm (3.5- from the motherboard (e.g. COM1,
jumper is used in the middle to select inch) floppy drive. Before fitting, ensure COM2, and VGA connectors) can be se-
the slave mode for CD-ROM. The cable that drive door in the front opens down- cured into the cutouts provided on the
connection arrangement for HDD and ward (hinged towards top). For install- case below the SMPS. Thus secure the
CD-ROM is shown in Fig. 8. ing floppy drive follow the same proce- ‘D’ connectors for COM1, COM2, and
Before installation of drives, note dure as used for fixing CD-ROM drive. VGA into the respective cutouts using
down pin-1 orientation/position of the Philips screws. This saves the
34-/40-pin interface cable connectors on precious space inside the PC
the drives. case and gives it an ethical look.
The CD-ROM drive may be installed For accommodating the
in the topmost position for 13.33cm panel/bracket for 25-pin ‘D’ con-
(5.25-inch) drive, after pushing out the nector of parallel port and PS/2
plastic piece (used for protection) cov- mouse as well as audio panel/
ering the cutout in this drive’s bay. Align bracket, remove two of the cut-
it from the front side of the case to en- outs from the rear of the case
sure that it is flush with the cabinet’s by just forcing them out with
external surface. Using four Philips hands, and secure these brack-
screws (6-32 UNC) secure it in proper ets in the vacant positions us-
horizontal position. The screws should ing Philips screws.

ELECTRONICS FOR YOU ❚  FEBRUARY 2001


Fig. 9: Back-panel connector details of HDD
and CD-ROM drives
Now you may terminate the connec-
tors originating from control panel on
the cabinet at the motherboard. Con-
nect the loudspeaker connector to CN14,
SCREENSHOTS CMOS SETUP MENUS
Πto analogue audio output connector on
 nana-type stereo jack into the line-out
CONSTRUCTION
power-on LED connector to CN12,
HDD LED connector to CN13, and re-
set switch connector to CN11. (Cor-
rect orientation can be ensured by
matching the pin connected to
coloured (not white) wire to go into
pin 1 of the connectors in
motherboard.)
Now connect the 40-pin middle
connector (in the ribbon cable) origi-
nating from CN1 in the motherboard
to CD-ROM drive and its end connec-
tor to HDD, ensuring that pin 1 of
connector pairs correctly match. (Pro-
jection/slot in the middle of connectors
will help you in proper orientation of
the connectors, unless you try to force
it in with wrong orientation.)
Follow it up by connecting the
34-pin floppy drive end-connec-
tor (at the end of twisted cable)
to the interface connector of
floppy drive. This header origi-
nates from CN3 on the
motherboard.
The 4-pin Molex-type power
supply connectors now remain
to be connected to the drives.
Ensure that rounded shoulder
on the female connectors mate
Continued
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
TABLE XI
Pin Assignment Internal Audio
Connector Internal Audio Connector
CN25 : AUX-IN
Pin Assignment
1 AUX-L
2 GND
3 GND
4 AUX-R
CN24 : CD-IN
Pin Assignment
1 CD-L
2 GND
3 GND
4 CD-R
CN33 : CD-IN
Pin Assignment
1 CD-R
2 GND
3 CD-L
4 GND
CN32 : CD-IN
Pin Assignment
1 GND
2 CD-L
3 GND
4 CD-R
correctly with the corresponding male
power connectors on CD-ROM drive and
HDD. In all cases you will observe that
yellow wire (+12V) pin faces the PC case
cover.
For FDD, use the 4-pin mini power
supply connector. This connector, if in-
serted properly, will lock itself into po-
sition. To take out this connector, you
should press the retaining lever with
your fingertip. Connect one of the 4-pin
connectors— CN24 or CN33 or CN32—
CD-ROM drive, after correctly match-
ing the ground pin ‘G’ marked over the
analogue audio connector on CD-ROM
drive (refer Fig. 10) and those of CN24
or CN33 or CN32 as given in Table XI.
If you have followed all the tips re-
ligiously, your hardware assembly is
complete on closing the cover of the cabi-
net using four to six Philips screws. But
before you do that, have a look again to
ensure that no loose wires are hanging
around. After closing the cover, you may
connect the keyboard cable to the key-
board connector, mouse cable to COM1
connector, and amplified speakers’ ba-
plug on the audio bracket.
Now that hardware assembly part
of the basic unit is over, installation of
other cards, such as LAN card (for net-
working), internal modem card (for
Internet access), and TV tuner card, into

Ž button seen on monitor’s screen.
 performs power-on-self-test (POST).
 keyboard. On the right, it shows cer-
the PCI slots, using the software driv-
ers supplied with them, can be at-
tempted subsequently.
Creating a startup disk
Eventually you will be using Windows
operating system (say, Windows 98), and
for that you should be having Microsoft
Windows 98 installation CD. Use some
other PC having Windows 98 operating
system to create a ‘startup disk’. The
idea is to have all important files, in-
cluding system files, Fdisk.exe, and
Format.com files, in hand, so that you
may proceed with hardware partition-
CONSTRUCTION
Continued
ing and formatting of hard disk once
you switch on your newly assembled PC
for the first time.
To make a startup disk, get a new
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
formatted 8.9cm (3.5-inch) floppy. On
the working computer, click ‘start but-
ton’, select settings, double click on icon
‘add/remove programs’, select ‘startup
disk’, insert formatted floppy in floppy
drive, and click over the ‘create disk’
The program would prompt you for
insertion of original Windows 98 CD in
CD-ROM drive. Insert the same and
click on ‘OK’ button. Even if you do not
have the original CD, but have all pro-
grams in Win98 directory in ‘C:’ drive,
you can give the proper path and the
appropriate programs will be copied to
the startup floppy disk.
CMOS setup
Switch on the newly assembled PC. It
During POST you will find ‘Num Lock’,
‘Caps Lock’, and ‘Scroll Lock’ LEDs
flashing. A single short beep during
POST indicates that motherboard is
‘OK’.
Certain messages will keep appear-
ing on the screen of your monitor, in-
cluding “ Press Del to enter CMOS
setup” . When this message appears,
press ‘Del’ key to enter setup. The
CMOS Setup Utility screen appears on
monitor screen (refer screenshot 1).
There are seven items on the left, which
can be selected using arrow keys on your
tain options that are quite obvious and
can be interactively executed when re-
quired.
Select the first item on the left,
“ Standard CMOS Features” , and press
enter to see its screen (refer screenshot
2). Use arrow keys to move between
the items and ‘Page Up’ or ‘Page Down’
key to edit or select the options. You
may correct the date, including year and
century, and the time to their current
values.
You would notice from
screenshot 2 that during power up,
the BIOS has identified the pri-
mary master (Seagate’s 10GB hard
disk ST310211A), 52X Samsung’s
CD-ROM Drive SC-15, floppy
drives, video, and RAM address
range (including its breakdown).
This latest Award BIOS 1984-2000
does not contain ‘Auto Detect Hard
Disk’ as a separate utility in the
CMOS setup options.

‘ inserting Windows CD in CD-ROM drive
’ Press Esc to exit FDISK
“ we propose to create two DOS parti-
To select any other screen/setup util-
ity option, press ‘Esc’, select the next
item from setup utility menu, and press
‘Enter’. The next screenshot (screen shot
3) pertains to ‘Advanced BIOS Features’.
Here you may edit and change the first,
second, and third boot devices to read
CD-ROM, HDD-0, and floppy, respec-
tively. This will enable you to boot/run
the computer from CD-ROM (if you have
a Windows installation), CD, HDD (af-
ter formatting and transferring the sys-
tem files), or floppy drive (using the
startup floppy created earlier), in that
priority.
Press ‘Esc’ to come back to the open-
CONSTRUCTION
ing screen. For the time being, skip utili-
ties/screens 4 through 7 with their de-
fault values. Select the last “Frequency/
Voltage Control” menu item. Edit ‘CPU
clock/spread spectrum’ item to read
‘100MHz/On’. Thereafter press ‘Esc’ and
select ‘Save and Exit Setup’ or F10 key,
and then ‘Y’ and ‘Enter’ for saving the
edited BIOS selections.
HDD partitioning and formatting
Assuming that you have Windows 98
installation CD in CD-ROM drive, the
PC will boot from the CD and start the
Windows 98 setup program. Press func-
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
tion key ‘F3’ to come out of the setup
program and come to the prompt
‘D:\Win98>’. Type ‘Fdisk’ and press ‘En-
ter’ for starting with the partitioning of
HDD. (Note. We could have used the
‘start up’ floppy in Drive ‘A’ instead of
and come to ‘A:\>’ prompt for running
the ‘Fdisk’ program from ‘A’ drive, if
desired.)
On pressing ‘Enter’ key, the follow-
ing FDISK main menu appears:
Current fixed disk drive: 1
Choose one of the following:
1. Create DOS partition or logical
DOS drive
2. Set active partition
3. Delete partition or logical DOS
drive
4. Display partition information
Enter choice: [ ]
Enter choice 1 above and press ‘En-
ter’ key. The next menu on page 2 ap-
pears as follows:
1. Create primary DOS partition?
2. Create extended DOS partition?
3. Create logical DOS partition?
Type ‘1’ and press ‘Enter’ key. The
program verifies integrity of the disk
and then displays.
Do you wish to use max. size for a
primary DOS partition and make it ac-
tive. Y/N?
Type ‘N’ and press ‘Enter’. (Because,
tions of equal size.) Once again the pro-
gram verifies integrity of the disk and
prompts you to enter/specify partition
in megabytes or percentage of disk
space. Type 50% and press ‘Enter’. The
program complies. Now press ‘Esc’ key
to return to the main FDISK menu.
Now enter choice 2. (The primary
DOS partition created earlier becomes
active.) The program will ask you to
enter the number of partitions. As it is
currently ‘1’ on ‘C’ drive, therefore type
‘1’ and press ‘Enter’.
Again press ‘Esc’. (Do not press ‘Esc’
key more than once, else it will come
out of FDISK.) Again you are led to
main FDISK menu.
Enter choice 1. You will come to
menu on page 2. Now enter choice 2 to
create extended DOS partition. The pro-
gram will again verify the integrity of
the disk and show availability of 50% of
the disk space for extended DOS parti-
tion. Type 50% for extended DOS parti-

tion and press ‘Enter’.
Again press ‘Esc’ (only once). The
program will ask you to specify the disk
space for logical drive. Simply press ‘En-
ter’ and then press ‘Esc’ to come back
to the main FDISK menu. Choose op-
tion 4 to display the information. After
looking at the partition information that
it has been correctly done, press ‘Esc’
to come out. Press keys
CTRL+ALT+DEL or RESET button for
settings to take effect. The PC will boot
from CD-ROM drive as per settings
done in the CMOS setup. On booting
you will again come to the setup part of
Windows 98 program. Hence to come
out of it, press F3. Now your drives are
designated as under:
C: First partition on hard disk
D: Extended partition on hard disk
E: CD-ROM drive
Now you will be able to access CD-
ROM drive by typing ‘E:’. After the
prompt ‘E:\>’, type ‘Format C:/S/U/V’
and press ‘Enter’. (Here ‘C:’ refers to
drive to be formatted, ‘S’ to system
(transfer of system files to ‘C’ drive dur-
ing formatting), ‘U’ to unconditional, and
‘V’ to verification.) After formatting ‘C’
drive, you will come back to the prompt
‘E:\Win98>’. Type ‘setup’ and press ‘En-
ter’ to install Windows 98 on ‘C’ drive.
As the program is interactive, keep
answering the questions logically.
Choose ‘typical’ while selecting the Win-
CONSTRUCTION
dows version. Various messages
like ‘enter computer name’,
workgroup, etc keep appearing,
which you may reply suitably.
Against ‘date/time zone’ selec-
tion, choose India.
Computer will show the
Agreement format that you are
bound to accept. Hence click on
the appropriate button.
Before proceeding with the
Windows installation, the pro-
gram prompts you for entering
the key number of Windows 98
product, which accompanies
each original copy. You must
type the key number accu-
rately. It will then copy the
Windows 98 files to ‘C’ drive in
Win98 directory. This will ob-
viate use of Windows CD for
creating a startup file, when-
ever required.
To format drive ‘D’, double
click on My Computer icon,
click the right button on drive D:, choose
‘Format’, and in ‘Format D:’ menu box,
choose full and click on ‘Start’ button.
After completion of the formatting of
‘D’ drive, it is accessible for read/write
operations. This completes partitioning
and formatting of the hard disk.
Loading motherboard drivers
• On-board VGA display driver.
When the PC is running, insert the
motherboard driver CD that came with
the motherboard (PCPartner driver’s
CD, in our case) into CD-ROM drive.
Select drive ‘E’, select ‘Intel Chipset
Products’, 810, VGA , Win9X, and
Graphics, in that order, and double click
on its ‘Setup.exe’ icon and follow the
instructions on screen. After finishing,
shut down the PC as per Windows shut-
down procedure and restart to allow the
drivers to take effect.
• On-board AC97 Codec sound
driver. Click on ‘Start’ button, select
settings, select control panel, double
click on ‘System’ icon, click on ‘Device
Manager’, go to ‘Other Devices’, double
click on ‘PCI multimedia’, select ‘PCI
Audio’, click on ‘Remove button’ (since
compatible software drivers have not yet
been installed to avoid conflicts), and
then click on ‘refresh’ button.
Go back to control panel and, click
on ‘Add new H/W’. A wizard guides you
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
through rest of the process, and in due
course, a message “Found new hardware
– PCI multimedia audio, display, sound
video” appears. The program asks if you
have disk (drivers). Click the ‘Browse’
button, select E:, ‘Intel Chipset Prod-
ucts’, 810 , AC97 Sound, CS4299, Win98,
in that order, and run ‘Setup’.
During the setup, when the program
prompts you for selection of device,
choose ‘Crystal Audio Codec’ and click
‘OK’. Again during the course of driver
installation for Crystal Audio Codec, the
program will prompt you for location of
Windows 98 files, which you may browse
and point towards C:\Win98 directory
or towards Windows CD as E:\Win98
and click ‘OK’ button. After finishing,
you may verify, via ‘Device Manager’
(refer preceding para) by clicking on
‘Sound, Video and Game controller’ icon,
that ‘Crystal Audio Codec’ as also ‘Crys-
tal Audio Codec with Game Device’ ap-
pear under it. (A sound icon will con-
currently appear on the bottom line of
your desktop.)
• Intel Firmware Hub configu-
ration. In ‘Device Manager’ under
‘Other Devices’, an ‘Unknown Device’
would still appear. This concerns ‘Intel’s
Firmware Hub’. To correct this prob-
lem, again go to 810 subdirectory on
the CD, double click on ‘INF_install’,
and then on ‘Setup.exe’ within that
subdirectory. A message “ Found New
Device – Intel Firmware Hub” appears
on the screen. This device will be auto-
matically configured when you follow
the instructions appearing on the screen
properly. To confirm that there are no
unknown devices now, open ‘Device
Manager’ and check all the items under
‘Other Devices’.
With installation of drivers for on-
board devices, hardware and software
configuration of your multimedia PC is
complete. Other secondary functions
such as power management functions—
APM (advanced power management) or
ACPI (advanced configuration and
power management interface)— can be
incorporated later through CMOS
‘Power Management Setup’ facility.
Similarly, you can install Ethernet card
for LAN and modem card for the
Internet, fax, and e-mail accessibility via
telecom lines. A brief information on
these additional functions is given be-
low.
• APM. APM caters to the PC to

enter an energy-saving standby mode.
BIOS enables APM by default. It can be
initiated in the following ways:
1. By specifying time-out period in
BIOS setup program.
2. By connecting a hardware sus-
pend/resume switch to CN10 on the
motherboard.
3. From ‘Suspend’ menu item in Win-
dows.
• ACPI. ACPI provides direct con-
trol to the operating system over the
power management as well as plug-‘n’-
play functions. Features include:
1. Power management control of in-
dividual devices, add-on cards, video dis-
play, and HDD.
2. Methods for achieving less than
30W operation in ‘Power-on Suspend
Sleeping State’ and less than 5W in ‘Sus-
pend to Disk Sleeping State’.
3. A soft-off feature to power off the
PC.
4. Support for multiple wake-up
events for the PC to resume normal op-
eration.
5. Support for front-panel power and
‘sleep’ mode switch.
CONSTRUCTION
• Ethernet
card for LAN.
Ethernet cards
capable of run-
ning at 10Mbps to
100Mbps, of dif-
ferent makes such
as Intel, Real Tek,
Mercury and Dax,
as Ethernet PCI
adapter are avail-
able in the mar-
ket.
Each card
comes with a bracket, driver diskette,
and user manual. The bracket would
have an LED and RJ-45 jack. This jack
is used for running a twisted-pair
unshielded cable (max. length 100
metres) between the card and the hub/
concentrator (10Base-T or 100Base-Tx)
to which other computer’s LAN cards
are similarly connected. Once the cable
is connected to the hub, the LED on
Ethernet card would light up. Before
installing, remove a cutout opposite the
PCI slot to make space for the bracket
of Ethernet card. When you install the
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
card, the power to the PC should be
‘off’.
When you switch ‘on’ the computer,
it automatically detects its presence and
‘New Hardware Wizard’ appears on the
screen to guide you through the instal-
lation process. It asks for location of
the drivers. The driver’s floppy can be
inserted in ‘A’ drive and path can be
indicated. You can then proceed fur-
ther, as per instructions appearing
on the screen, to complete its installa-
tion.
• Modem. 56kbps PnP (plug-‘n’-play
compatible) and Windows 95/98 compat-
ible internal modem cards are available
from different manufacturers for instal-
lation in any of the PCI slots. The mo-
dem card will have a telephone line jack
for connection of telephone line from
wall socket, a parallel phone jack for
connecting a telephone set, and Mic and
speaker jacks for external mic and
speakers for use with voicemail and
speakerphone facilities, respectively.
For installing the drivers, the pro-
cedure would be similar to that used
for installation of the Ethernet card. ❏

INTELLIGENT WATER LEVEL
CONTROLLER
SADHAN CHANDRA DAS
I
n coming years, the drinking water
is going to be one of the scarce com-
modities. This would partly be at-
tributable to our mismanagement of wa-
ter supply and its wastage. In normal
households, where pumps are used to
fill the overhead tanks (OHT), it is usu-
ally observed that people switch on the
pump and forget to switch it off even
Fig. 1: Circuit diagram of water level controller
CONSTRUCTION
EDI
DWIV
S.C.
when the tank has become full. As a
result, water keeps overflowing until the
household people notice the overflow
and switch the pump off. As the OHT,
in general, is kept on the topmost floor,
it is not quite convenient to go up fre-
quently and see the water level in the
OHT.
This problem can be solved by using
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
the intelligent digital liquid level con-
troller circuit presented here. It has the
following features:
• It can automatically switch on the
pump when the tank is empty and
switch it off when the tank becomes full.
• It can check the ground tank
(sump tank) water level from which the
water is pumped into the overhead tank
(OHT). If the sump tank water level is
below the predetermined level, the unit
switches off the pump to protect the
pump from dry-run, even though the
overhead tank may be completely
empty.
• It includes under- and over-volt-
age cutout to switch off the pump if the
voltage is not within specified low
(200V) and high (250V) limits.
• It includes a circuit for digital dis-
 CONSTRUCTION

have been used for passive pull-down.

Controller circuit. The controller
circuit is built around three quad 2-in-
put NOR ICs (IC3 through IC5) to
switch the pump motor on or off when
certain conditions are fulfilled. The con-
ditions to be met for switching-on/run-
ning of the pump are:
1. The mains supply should be
within certain ‘low’ and ‘high’ cut-off lim-
its (say between 200V AC and 250V AC).
2. The water level in the sump
(ground tank) is above certain optimum
level (2' in Fig. 1).
3. Water in the overhead tank (OHT)
Fig. 2: Power supply is below the minimum level.
Once all the above-mentioned three
(cathode) No. 1 is in conditions are satisfied, the pump mo-
touch with the water, tor would start running. The corre-
the voltage at pin 3 of sponding logic level at point A will be
IC1 becomes logic high low (point B will also be low automati-
(i.e. +5V), and hence cally – not being in touch with the liq-
voltage at line No. 1 uid), point C will also be low and point
(L-1) also becomes D will be high.
high. Now due to con- Once running, the pump will con-
duction of diode D3, tinue to run even when the water rises
the BCD code 0001 (Q3 above the minimum level in the OHT
Fig. 3: Construction details of probes for mineral water
Q2 Q1 Q0) is gener- (i.e. when point A subsequently goes
ated and con- high), provided the first condition is still
verted to fully satisfied and the water level in
equivalent 7- the sump has not fallen below that of
segment code sensor 1'. It will stop only when either
by IC2 the maximum specified level in the OHT
(74LS47) to has been reached or the water level in
display the the sump has fallen below sensor 1' po-
decimal digit sition.
‘1’. Here the NOR gate pairs of N2 and
Similarly, N3, and N6 and N7, form NOR-latches.
when the tips When the ground tank (sump) water
of the both sen- level is above the defined level 2', the
sors 1 and 2 voltage at pin 11 of gate N6 is low. So
are in touch diode D12 cannot conduct. Also, if the
with water, the mains voltage is within acceptable lim-
voltage at pin 3 its of 200-250V, the voltage at output
Fig. 4: Construction details of probes for non-conducting liquids
becomes logic pin 3 of gate N12 is high and the volt-
play of the overhead tank level to indi- low (0V) while the voltages at pin 4 and age at collector of transistor T2 is low.
cate water levels 0 through 4 as per line 2 (L-2) become logic high (i.e. +5V). Diodes D8 and D11 are thus cut off. So
positions of the tips of the sensors in- Now due to conduction of diode D6, the the voltage at input pin 8 of gate N4 is
side the overhead tank. corresponding BCD code 0010 is gener- pulled down to logic low level by pas-
• The sensors used in this project ated and decimal digit 2 is displayed on sive pull-down resistor R18 (56 kilo-
have a lifetime of more than five years. the 7-segment display. ohm).
Digital display circuit (refer When the tank is completely empty, Now if overhead tank is empty, i.e.
Fig. 1.) This circuit comprises a quad the outputs of all XOR gates of IC1 are water level is below level 1, voltage
2-input XOR gate IC1 (CD4030) for sum low and the display shows decimal digit states at input pins 1 of gate N2, and
outputs, decimal to BCD code converter 0. In this way the display circuit works pins 12 and 13 of gate N1, are pulled
using diode matrix of diodes D3 through to show decimal digits 0 through 4, cor- down to logic low by passive pull-down
D7, a BCD to 7-segment decoder/driver responding to the level of the water, as resistors R13 and R14 respectively.
IC2 (74LS47), and common-anode type defined by the position of the sensors Hence voltages at output pin 11 of gate
7-segment display LTS 542R. at different heights. Here the resistors N1 and input pin 5 of gate N3 become
When only the tip of sensor probe R9 through R12 and R19 through R21 logic high to force the output at pin 4 of

ELECTRONICS FOR YOU ❚  FEBRUARY 2001

 CONSTRUCTION

PARTS LIST1
Semiconductors:
IC1 - CD4030 quad 2-input XOR
gate
IC2 - 74LS47 BCD to 7-segment
decoder/driver
IC3-IC5 - CD4001 quad 2-input NOR
gate
IC6 - LM7812 regulator 12-volt
IC7 - LM7805 regulator 5-volt
T1-T2 - SL100 npn transistor
D1-D15,
D17-D20 - 1N4001 rectifier diode
D16 - Red LED
DIS1 - LTS542R 7-segment com-
mon anode display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1-R8 - 33-kilo-ohm
R9-R18 - 56-kilo-ohm
R19-R21 - 1.5-kilo-ohm
R22, R24 - 2.2-kilo-ohm
R23 - 1.2-kilo-ohm
R25 - 1-kilo-ohm
Fig. 5: Actual-size, single-sided PCB for water level controller R26, R27 - 220-kilo-ohm
R28-R34 - 330-ohm
VR1, VR2 - 100-kilo-ohm preset
Capacitors:
C1-C4, C7 - 0.01µF ceramic disc
C5 - 470µF, 35V DC electrolytic
C6 - 2200µF, 35V DC electrolytic
C8,C9 - 10µF, 25V DC electrolytic
Miscellaneous:
RL1 - 12V, 200-ohm 2 C/O relay
X1 - 230V AC primary to
(a) 0-15V, 750 mA, and
(b) 0-12V, 100 mA secondary
transformer
S1 - Push-to-on button
S2 - On/Off switch
- IC sockets
- Heat sinks for regulator ICs
- SS304, 5mm dia. stainless
steel rod for anode and 3mm
dia. for all cathodes - of ap-
propriate length
- Multi-core feed wire

N4 becomes logic high to make its out-

Fig. 6: Component layout for the PCB
gate N3 to be latched low. This logic
level will not change until voltages at
input pins 5 and 6 of gate N3 become
low (0V) and voltage at pin 1 of gate N2
goes high (+5V). Since both inputs of
gate N4 are low, hence its output at pin
10 goes logic high to drive transistor T1
into conduction. Relay RL1 is thus
energised and the pump motor is
switched ‘on’.
The water level of the overhead tank
starts rising. When the water level
reaches the tip of the topmost sensor 5,
voltage at pin 1 of gate N2 goes high.
Already, the voltage levels at pin 11 of
gate N1 and input pin 5 of gate N3 are
low. So the voltages at output pin 4 of
gate N3 and input pin 9 of gate N4 be-
come logic high to turn the output pin
10 of gate 4 to logic low level. Thus
relay RL1 is de-energised, to switch the
pump off.
When line voltage is within the
specified limits and ground water level
goes below the defined level 1', the volt-
age at output pin 11 of gate N6 becomes
logic high to make diode D12 conduct.
As a result, the voltage at pin 8 of gate
put pin 10 go low. Transistor T1 is cut
off and the relay is kept disabled, even
though the overhead tank is fully empty.
The relay will be enabled only when the
water level in the sump tank is above
level 2'.
When the ground tank water level
is above level 2' but the line voltage is
out of range, gate N12 output pin 3 goes
low to cut off transistor T2, making di-
ode D11 conduct. In this state the out-
put of gate N6 and the output of gate
N2 become logic low. Although diode
D12 does not conduct, diode D11 con-
ducts and the output of gate N4 goes
low to cut off transistor T1. This dis-
ables relay RL1 and the pump remains

ELECTRONICS FOR YOU ❚  FEBRUARY 2001

 CONSTRUCTION

off, even though the overhead tank is
completely empty.
Here two cathode sensors for sens-
ing ground tank water level have been
used instead of one, to provide some
hysteresis in the system. When ground
water level is below level 1', the output
of gate N6 becomes logic high (5V).
When water level is above level 2', the
output of gate N6 is logic low (0V). If
the water level is in between levels 1'
and 2', there is no change of state at
output of gate N6, i.e. output remains
at the last/previous state.
Power supply (Fig. 2). The power
supply circuit consists of step-down
transformer X1 (having two secondar-
ies with ratings of 12V, 100 mA and
15V, 750 mA), a bridge rectifier (using
four 1N4001 diodes), a capacitor of 2200
µF for filtering purpose, regulator IC
7812 for feeding the anode probes as
well as relay RL1, and regulator IC 7805
for feeding regulated +5V supply to all
digital ICs, LEDs, and 7-segment dis-
play. The 12V secondary is used for sam-
pling the mains. One of its terminals is
grounded while its other terminal,
marked ‘G’, is connected to point ‘G’ of
high/low cutout circuit in Fig. 1. The
other secondary rated at 15V, 750 mA
is used for deriving the regulated DC
supplies required for operation of the
circuit.
Construction of sensors (Fig. 3).
The highlight of the circuit are its elec-
trodes (Fig. 3) used for mineral/conduc-
tive water, which are made of stainless
steel (grade SS-304) rods. These elec-
trodes have a life span of more than five
years. Anode is a rod of 5 mm diameter
and each of the cathodes is of 3 mm
diameter, as shown in the figure.
The cathodes and the anode should
be long enough so that their soldered
terminals are not in contact with water,
even when the tank is full. The joints
should be covered with insulation in such
a way that rain water does not come in
contact with the soldered joints. One
has to use orthophosphoric acid or zinc-
chloride to make a soldered joint be-
tween stainless steel and conducting part
of the flexible feed wire.
The distance between the anode and
the cathodes should not be more than 60
cm. Arrangement should be made in such
a way that no electrode touches the
other.
The circuit can also be used for non-
conductive liquids such as pure distilled
water by using floats in conjunction with
micro switches, as shown in Fig. 4. This
arrangement can be used for distilled
water plants, research laboratories, and
for other nonconductive liquid level sens-
ing applications.
An actual-size, single-sided PCB for
the circuits in Figs 1 and 2 is shown in
Fig. 5, and the component layout is
shown in Fig. 6.

A UNIQUE LIQUID PARTS LIST2

Semiconductors:
IC1-IC3 - CD 4030 quad 2-input X-OR

LEVEL INDICATOR
NA
ANJA gate
RUP IC4 - 74LS47 BCD to 7-segment
decoder/driver
IC5 - UM66 melody generator
DIS1-DIS3 - LTS 542 common anode
7-segment display
SADHAN CHANDRA DAS T1, T3, T4 - SL100 npn transistor
T2 - BC 108 npn transistor
D1-D16,
D21, D22 - 1N4001 rectifier diode

A
separate alternative circuit of a warned when water reaches 100% and ZD1 - 3.1 volt zener diode
unique liquid level indicator also when its level drops to 10% so that LED1-LED4 - Red LED
to provide a display in terms of you may manually switch the pump mo- Resistors (all ¼-watt, ±5% carbon, unless
the percentage of full-scale level in OHT tor on or off, as the case may be. stated otherwise):
is shown in Fig. 7. It can either be used This level indicator can show the dis- R1 - 3.3-kilo-ohm
R2-R5 - 1.5-kilo-ohm
to replace the digital display circuit in- crete levels in percentage from 0 to R6-R24 - 330-ohm
cluded in Fig. 1 (by simply connecting 100% with 10% resolution. An audio R25-R34 - 56-kilo-ohm
the 10% and 100% sensor probes of Fig. alarm circuit has been incorporated to R35-R44 - 33-kilo-ohm
7, additionally, to points marked ‘A’ and generate audio alarm when the tank R45 - 100-kilo-ohm
‘B’ respectively in Fig. 1, apart from con- level reaches 100% and also when the R46 - 2.7-kilo-ohm
R47, R48 - 680-ohm
nection of +5V and +12V supplies and level drops to 10%. The input to the
Capacitor:
ground points) or it can be used in con- audio alarm circuit (Fig. 8) is tapped
C1 - 100µF, 25V electrolytic
junction with an audio alarm unit shown from line-1 and line-10 representing
Miscellaneous:
in Fig. 8 and the power supply circuit 10% and 100% levels respectively in
LS - 8-ohms speaker 7.5 cm dia
in Fig. 2 independantly. Fig. 7. - SS 304, 5 mm dia and 3mm
The latter configuration can be used If, in place of displaying the liquid dia stainless steel rods of ap-
when you do not desire to have auto- level in percentage, one wants to dis- propriate length for anode
matic control for switching the pump play only the digits 0 through 10, then and cathodes respectively.
- Multi-core feed wire
motor on and off but need only to be 7-segment display DIS1 and LEDs

ELECTRONICS FOR YOU ❚  FEBRUARY 2001


Fig. 7: Unique liquid level indicator
Fig. 8: Audio alarm unit
(LED1 through LED4) for ‘%’ symbol can
be removed. This circuit can be used
for premises which have overhead tanks
and the water supply is provided by mu-
nicipalities or corporations etc.
Display circuit. The basic elements
of the circuit, as shown in Fig. 7, com-
prise three quad 2-input XOR gates (IC1
through IC3) to get only the sum out-
puts, a hardwired decimal-to-BCD con-
verter (using diodes D1 through D16),
and a 74LS47 BCD-to-7-segment de-
CONSTRUCTION
coder/driver 10. If line L-1 is at logic 1, BCD code
(IC4). When 0001 is generated due to conduction of
the tip of diode D9 only. Similarly, if line L-3 is
sensor-1 is in at logic 1, BCD code 0011 is generated
touch with due to conduction of diodes D6 and
the water, D16.
the line (L-1) The voltages, corresponding to their
connected to BCD codes, are fed to the inputs of IC
pin 3 of IC1 74LS47 (7-segment decoder/driver) to
(CD 4030) drive 7-segment display DIS2. When line
goes to logic L-10 is high, display DIS3 is driven by
1 state transistor T1 (SL100) for decimal num-
(+5V). ber 1.
W h e n Since all the time the unit place digit
the tips of sensors 1 and 2 both touch of the percentage display is 0, the cath-
the water, pin 3 of IC1 goes to logic 0 odes of corresponding segments of DIS1
(0V), while line L-2 connected to pin 4 have been permanently connected to
of IC1 becomes high (+5V). Thus which 0V (ground) through current-limiting
one of the lines (L-1 through L-10) will resistors of 330 ohms each. In this way
be at logic 1 would depend on which the circuit displays 0 to 100 per cent
last sensor (counted from bottom of the of liquid level with 10 per cent resolu-
tank) is in touch with the water. If the tion.
tank is totally empty, all the lines, L-1 One may or may not use diode D1.
through L-10, would be at logic 0. In this circuit the resistors of 56-kilo-
These lines (L-1 through L-10) rep- ohm are connected across the inputs of
resent the decimal numbers 1 through XOR gates and ground, while resistors
ELECTRONICS FOR YOU ❚  FEBRUARY 2001
 CONSTRUCTION

from R2 to R5 have been

used for passive pull-
down action.
Audio alarm unit.
Fig. 8 shows the circuit
for audio alarm. The
base of transistor T2
(BC108) is connected to
the terminals of lines L-
10 and L-1 via diodes
D21 and D22 respec-
tively and a common re-
sistor of 100-kilo-ohm.
When water touches
the topmost sensor
probe, transistor T2 con-
ducts and transistor T3
is cut off. As a result
3.1V developed across
zener ZD1 becomes
available across pins 1
and 2 of melody genera-
tor IC7 (UM66). The
Fig. 9: Actual-size, single-sided PCB for the unique liquid level indicator
amplified musical alarm
is heard from the
speaker.
When the tank is nei-
ther 100% full nor it is
above 10% (but less than
20%), transistor T2 cuts
off while transistor T3
is saturated to make
the voltage across pins 1
and 2 of IC7 at almost
0V, and hence no sound
is produced by the unit.
A separate parts list
and actual-size PCB lay-
out as well as component
layout (Figs 9 and 10 re-
spectively) are included
after integrating the
power supply of Fig. 2
with liquid level indica-
tor circuit of Fig. 7 and
audio alarm unit of
Fig. 8. ❏
Fig. 10: Component layout for the above PCB

ELECTRONICS FOR YOU ❚  FEBRUARY 2001

March

2001
Circuit Ideas

2001
 CIRCUIT IDEAS

AUTOMATIC HEAT DETECTOR IVEDI

lay is in energised state. LED1, con-
nected in series with 68-ohm resistor
R1 across resistor R4, glows when the
DW
SUKANT KUMAR BEHARA S.C. siren is on.
To test the working of the cir-

T
his circuit uses a complementary Pin Designation Sound Effect cuit, bring a burning matchstick
pair comprising npn metallic SEL1 SEL2 close to transistor T1 (BC109),
transistor T1 (BC109) and pnp No Connection No Connection Police Siren which causes the resistance of its
germanium transistor T2 (AC188) to de- +3V No Connection Fire Engine Siren emitter-collector junction to go low
tect heat (due to outbreak of fire, etc) Ground No Connection Ambulance Siren due to a rise in temperature and it
in the vicinity and energise a siren. The Do not care +3V Machine Gun starts conducting. Simultaneously,
collector of transistor T1 is connected transistor T2
to the base of transistor T2, while the also conducts be-
collector of transistor T2 is connected cause its base is
to relay RL1. connected to the
The second part of the circuit com- collector of tran-
prises popular IC UM3561 (a siren and sistor T1. As a
machine-gun sound generator IC), which result, relay RL1
can produce the sound of a fire-brigade energises and
siren. Pin numbers 5 and 6 of the IC switches on the
are connected to the +3V supply when siren circuit to
the relay is in energised state, whereas produce loud
pin 2 is grounded. A resistor (R2) con- sound of a fire-
nected across pins 7 and 8 is used to fix brigade siren.
the frequency of the inbuilt oscillator. Lab note.
The output is available from pin 3. We have added a
Two transistors BC147 (T3) and sound from UM3561. Resistor R4 in se- table to enable readers to obtain all pos-
BEL187 (T4) are connected in ries with a 3V zener is used to provide sible sound effects by returning pins 1
Darlington configuration to amplify the the 3V supply to UM3561 when the re- and 2 as suggested in the table.

ELECTRONICS FOR YOU ❚  MARCH 2001

 CIRCUIT IDEAS

MUSICAL ‘TOUCH’ BELL S.C.

DWIV
EDI
ing. Simultaneously, the emitter-baser
junction of transistor BC558 also starts
conducting. As a result, the collector of
SUKANT KUMAR BEHARA transistor BC558 is pulled towards the
positive rail, which thus activates melody

H
ere is a musical call bell that The collector of BC558 is connected to generator IC1 (UM66). The output of
can be operated by just bridg- pin 2 of musical IC UM66, and pin 3 of IC1 is amplified by transistor BEL187
ing the gap between the touch- IC UM66 is shorted to the ground. The and fed to the speaker. So we hear a
plates with one’s fingertips. Thus there output from pin 1 is connected to a tran- musical note just by touching the touch
is no need for a mechanical ‘on’/‘off’ sistor amplifier comprising BEL187 points.
switch because the touch-plates act as transistor for feeding the loudspeaker. The washer’s inner diameter should
a switch. Other features include low cost One end of 2.2-mega-ohm resistor R1 be 1 to 2 mm greater than that of the
and low power consumption. The bell is connected to the positive rail and the screwhead. The washer could be fixed in
can work on 1.5V or 3V, using one or
two pencil cells, and can be used in
homes and offices.
Two transistors are used for sens-
ing the finger touch and switching
on a melody IC. Transistor BC148 is
npn type while transistor BC558 is pnp
type.
The emitter of transistor BC148 is
shorted to the ground, while that of other to a screw (as shown in the fig- the position by using an adhesive, while
transistor BC558 is connected to the ure). The complete circuit is connected the screw can be easily driven in a
positive terminal. The collector of tran- to a single pencil cell of 1.5V. wooden piece used for mounting the
sistor BC148 is connected to the base of When the touch-plate gap is bridged touch-plate. The use of brass washer and
BC558. The base of BC148 is connected with a finger, the emitter-collector junc- screw is recommended for easy solder-
to the washer (as shown in the figure). tion of transistor BC148 starts conduct- ability.

ELECTRONICS FOR YOU ❚  MARCH 2001


NON-CONTACT LIQUID-LEVEL
CONTROLLER
R.G. THIAGARAJ KUMAR
E
FY readers are quite familiar
with liquid-level controllers. But
the one presented here is dif-
ferent. Usually, transducers using elec-
tric conduction, or variation in resis-
tance or capacitance principle, are em-
ployed for level sensing.
In conduction type of sensors, the
electric current passes through the liq-
uid. The corrosion of contacts is a ma-
jor problem while using DC excitation.
The cost and the size are the two re-
strictive factors in using AC excitation.
Further, passing current through the
liquid in combustive environments is not
CIRCUIT IDEAS
stable multivibrator wired around the
common 555 timer IC. It can be set or
reset by the closure of reed switches.
S.C.
DWIV
EDI
The output of the multivibrator drives
the relay, which controls the AC mains
supply to the pump motor or any other
controller (such as a solenoid-operated
valve).
The reed switches are connected as
permissible. shown in the figure. These are put in a
In resistance type sensors, the re- closed (non-conductive) tube, which is
sistance is altered through some me- then placed in the tank. The ferrite ring
chanical arrangement, which means a magnet is put inside the float, and it
moves up and down along the
tube depending upon the
level of the liquid in the tank.
When the level of the liq-
uid in the tank is low, the
magnet comes closer to reed
switch S2. As a result, switch
S2 is closed and the bistable
multivibrator sets. This ac-
tuates the relay, thereby
starting the pump to fill the
tank. The level of the liquid
in the tank starts increasing.
When the level of the liq-
uid in the tank is high
enough, the ring magnet
comes close to reed switch
large operating S1, and it closes. The bistable
force is re- multivibrator now resets and the pump
quired, which is switched off. This process is repeated
may be a prob- and the tank gets filled automatically.
lem in small Switches S1’ and S2’ are used for
tanks. In ca- testing the circuit or when the reed
pacitive trans- switches are non-functional. A neon bulb
ducer type, the is used to indicate the presence of the
construction AC supply in the plug. An optional
cost is high. piezobuzzer is used to raise an audible
In the
present project,
an easy but ef-
fective liquid-
level controller
is presented us-
ing the mag-
netic principle. It is non-contact type
and hence can be used in almost all ap-
plications, irrespective of whether the
liquid is conductive or not. Two reed
switches (with glass enclosure) and a
ring magnet (normally used in loud-
speakers) form the sensor unit. The reed
switches used are normally-open type
and they close when placed (and ori-
ented properly) in a magnetic field.
The electronic circuit is a simple bi-
ELECTRONICS FOR YOU ❚  MARCH 2001

alarm when the relay energises.
If you desire to display the level of
the liquid in the tank, additional reed
switches would need to be placed inside
the tube at different levels (say, 1/4th, 1/
2, 3/4th, and near-overflow level). They
CIRCUIT IDEAS
can be connected between the LEDs and
the supply via current-limiting resistors
for level indication. The LEDs can be
arranged in a model tank diagram
printed on the front panel of the con-
troller. The LED corresponding to the
ELECTRONICS FOR YOU ❚  MARCH 2001
level of the liquid in the tank would glow
in this arrangement.
The selection of float material is to be
done carefully to avoid chemical reac-
tion and/or pollution of the liquid. Teflon
floats are suitable for most applications.
 CIRCUIT IDEAS

the second part of the circuit.

AC MAINS PHASE-SEQUENCE
The three phases (R, Y, and B) are
brought to an artificial neutral at the junc-
tions of resistors R17 through R19 (each
22 kilo-ohm, 2-watt) to serve as the com-

INDICATOR S.C.
DWIV
EDI
mon reference. As stated earlier, for a
given phase sequence, when phase R is
at its negative-going zero, phase B is nega-
M.K. CHANDRA MOULEESWARAN tive. So data-input pin 5 of the flip-flop
(IC2) is logic ‘high’ (due to non-conduc-

A
mains phase-sequence indicator
serves as a hand-tool in check
ing electrical wiring, especially the
wiring of three-phase AC motors.
The basic idea of the circuit is that
specified fashion, as shown in the figure.
The second part comprises the phase-se-
quence detector followed by phase-se-
quence sensor operated flip-flop and LED
switching transistors.
tion of transistor T5). Meanwhile, clock-
input pin 3 of the flip-flop goes from low
to high due to phase R (refer waveforms
for condition 1, as observed by EFY Lab).
The ‘high’ at data pin appears at the Q

when any (say, Y) of the three phases
(RYB), taken as a reference phase, is at
negative-going zero voltage, its leading
phase (say, R) is positive while its lag-
ging phase (B) is negative, and these
states can be easily verified.
The circuit comprises two main parts.
The first part comprises transistorised
multivibrator, decade counter-cum-LED
driver, and LED arrays arranged in a
The astable
multivibrator
section provides
clock pulses in
the 10 to
1000Hz range to
the decade
counter and the
LED array sec-
tion. The LEDs
are grouped into
two parts to
form two dis-
tinctive indicators. These
two groups are successively
driven by Q0 to Q4 and Q5 to Q9 outputs output (pin 1) while Q output remains
of IC1. Only one of the two groups’ LEDs ‘low’ as long as the phase sequence is
will turn on sequentially, depending on clockwise. Therefore the Q output drives
which of the two transistors (transistor transistor T3 to extend the ground path
T3 or transistor T4) is on, which, in turn, for green LEDs D1 through D10 to show
is dependent upon the phase sequence of a clockwise-rotating LED ring.
the three-phase supply. This becomes When any of the two phases gets in-
clear from the following explanation of terchanged (say, after a maintenance

ELECTRONICS FOR YOU ❚  MARCH 2001


work at the power-house or repair/replace-
ment of a 3-phase transformer), the con-
ditions are reversed (refer waveform for
CIRCUIT IDEAS
condition 2, as observed by
EFY Lab), and Q become
‘high’ and red LEDs D11
through D20 are switched
on (sequentially) by tran-
sistor T4 to show an
anticlockwise-rotating ring.
While testing for the
phase sequence, there is no
need to keep the device on
for a long time. A push-to-
on read switch can be used
during the phase-sequence
testing. If the device is to
be used for long periods, use a high-capac-
ity battery in place of PP3 battery. Also
replace 2W resistors R17 to R19 with 5W
ELECTRONICS FOR YOU ❚  MARCH 2001
fusible-type resistors.
The frequency of the astable
multivibrator is unimportant, except that
the speed of the LED ring must be easily
visible. Zener diodes ZD1 and ZD2 are
used for protection of transistors T5 and
T6, respectively.
Precautions. 1. Never use an AC
mains adaptor-type power supply in place
of the battery.
2. Correctly position LEDs D1
through D20 in the ring for its proper
viewing.
3. Assemble resistors R11 to R19 on
the PCB at a slightly elevated level using
ceramic beads for proper dissipation of
heat.
 CIRCUIT IDEAS

HIGH-POWER BICYCLE HORN EDI

disk to pin 5 of IC1 and the other end
to pin 8 of IC1 through a 1/4W, 1-kilo-
ohm resistor.
DWIV
T.K. HAREENDRAN S.C. IC1 KA2411 is also available in COB
style, with the same pin configuration.

A
n interesting circuit of a bicycle
horn based on a popular, low-
cost telecom ringer chip is de-
scribed here. This circuit can be pow-
ered using the bicycle dynamo supply
and does not require batteries, which
need to be replaced frequently.
The section comprising diodes (D1
and D2) and capacitors (C1 and C2)
forms a half-wave voltage-doubler cir-
cuit. The output of the voltage doubler
is fed to capacitor C3 via resistor R1.
The maximum DC supply that can be Both packages work equally well. How-
applied to the input terminals of IC1 is ever, to get the best results with the
28V. Therefore zener diode ZD1 is added COB package, change values of resis-
to the circuit for protection and voltage tors R2 through R4 to 330-kilo-ohm, ca-
regulation. pacitor C4 to 0.47µF, 63V electrolytic
The remainder of the circuit is the (positive end to pin 3 of IC1), and C5 to
tone generator based on IC1 (KA2411). 0.005µF, 63V.
The dual-tone output signal from pin 8 This bicycle horn project can also be
of IC1 is fed to the primary of transfor- used as a telephone extra ringer by just
mer X1 (same as used in transistor ra- necting a piezoceramic element in place removing all components on the left side
dios) via capacitor C6. The secondary of of the loudspeaker, remove capacitor C6, of capacitor C3 and connecting the cir-
X1 is connected to a loudspeaker directly. transformer X1, and the loudspeaker. cuit shown in Fig. 2 to the terminals of
In case you are interested in con- Connect one end of the piezoceramic capacitor C3.

ELECTRONICS FOR YOU ❚  MARCH 2001


LUXURIOUS TOILET/
BATHROOM FACILITY
A.R. GIDWANI
A
ged persons in the house and
guests often fumble while
searching for the toilet and
bathroom switches at night. Also, very
few of us take care to switch off the
lights of toilets/bathrooms after using
them. The circuit given here helps to
overcome both the problems.
The figure shows two symmetrical
circuits (one each for toilet and bath-
room) sharing common power supply
and a melody generator-cum-audio
warning unit. The reed switches S1 and
S2 are of normally-open type, operated
by permanent magnets appropriately
fixed to the doors of bathroom and toi-
let, respectively. When the doors of
bathroom and toilet are closed, the reed
switches are also closed, and vice versa.
(Door is assumed in closed condition
with nobody inside bathroom/toilet, i.e.
reed switch is activated.)
The operational features of the cir-
cuit are:
CIRCUIT IDEAS
EDI
DWIV
S.C.
• Lamp and exhaust fan are
switched on when the door is opened.
• Soft music is played continuously
until the door is closed from inside/out-
side.
• With a person inside the room,
lamp and fan remain on, until the door
is reopened. They go off when the door
is reopened.
• Visual indication of whether the
toilet/bathroom is occupied/vacant is
given by two bicolour LEDs fixed on a
panel, which may be fitted near the door
with corresponding ‘toilet’/’bathroom’ la-
bels on them. Here the LED colour turns
from ‘green’ to ‘red’ if the room gets
occupied, and vice-versa.
• If the door is opened once, and
not closed back within 10 seconds, the
lamp and fan are automatically switched
off, thus conserving electricity. But the
music remains on as a reminder that
the door is not closed.
• For cleaning of bathroom/toilet
ELECTRONICS FOR YOU ❚  MARCH 2001
with doors kept open, a parallel on/off
switch is included on the switchboard
to bypass the relay contacts and manu-
ally control the switching on/off of the
light and exhaust fan. (This is the ser-
vice mode.) In this case, the music re-
mains on as long as the door remains
open. In case of failure of the unit, the
same on/off switch can be used as usual
until the circuit is repaired.
• Due to battery backup facility,
even with power failure, when a person
is inside, the door status is maintained.
However, the lamp and fan will be on
only on mains resumption.
• Also, when a person leaves the
room during power failure, with door
closed, the lamp and fan are kept off on
resumption of power. (Intelligent-mode!)
• However, the circuit can be fooled
by opening and closing the door within
10 seconds, without entering inside. In
this case, the lamp and fan will con-
tinue to be on and would require re-
opening and closing of the door to bring
the circuit to order.
This problem can be prevented to
some extent by using a hydraulic door
opener, which would approximately take
10 seconds to close the opened door. A
delay period of 10 seconds is deliber-
ately chosen for letting the person in-
side the toilet/bathroom in normal case!
IC1 is a dual positive edge-triggered
‘D’ type flip-flop. IC1(a) gets triggered
Fig. 1

Fig. 2
when bathroom door (and switch S1) is
opened and hence IC1(b) toggles, as Q
output of IC1(a) is connected to clock
input pin of IC1(b). As a result, relay
RL1 energises through transistor T3,
thereby switching on the lamp and ex-
haust fan. (Please refer to Fig. 2, the
separate wiring diagram of lamp and
exhaust fan via the N/O contacts of the
relay.) Simultaneously, pin 2 (Q) of
IC1(a) goes low, switching transistor T5
‘on’, which switches on melody genera-
tor IC4, letting out a sweet audio tune
via transistor T6 and loudspeaker.
In normal condition, when someone
opens the bathroom door and gets inside
within preset time of IC3(a) (10 seconds
here), and closes the door from inside,
the music stops with lamp and fan ‘on’.
Now, in case someone opens the door
before or after use, and forgets to shut
it, the lamp and exhaust fan are switched
off after 10 seconds but the music re-
mains ‘on’ as a reminder that the door is
to be closed. This happens due to mono
multivibrator (MMV) IC3(a), which re-
sets pin 10 of IC1(b) through transistor
T1 after 10 seconds. (This period can be
adjusted by varying the values of resis-
tor R11 and/or capacitor C7.)
It should be noted here that al-
CIRCUIT IDEAS
though IC3 is used as ‘MMV’, it is trig-
gered here with a positive pulse through
its pin 4 (reset pin) rather than its pin
6 (trigger pin). This arrangement makes
it unique for setting and resetting IC3
through pin 4, and resetting IC1(a)
through pin 5 of IC3 and transistor T1.
Battery backup facility ensures
memory backup during power failure.
Power supply uses a normal 2-diode full-
wave rectifier circuit, which needs no
further explanation. The purpose of us-
ing bi-colour LED1 and LED2 is that,
initially when the door is closed these
emit green light— as the green LED part
gets the supply via resistor R15— to in-
dicate that bathroom/toilet is vacant.
When bathroom/toilet is occupied, tran-
sistor T3/T4 conduct to light up the red
LED part as well.
Melody generator IC4 (UM66) is
switched on through diodes D3/D4 and
transistor T5, which conducts when
IC1(a) pin 2 or IC2(a) pin 2 goes low.
When transistor T5 conducts, zener ZD1
breaks down and supplies regulated
3.9V to IC4, to produce a melodious tune
via transistor T6 and the speaker.
As most toilets and bathrooms are
‘attached’ nowadays, only a single cir-
cuit is required, and the circuit can be
wired on a general-purpose veroboard.
A small modification of the circuit,
by adding additional SPST switch S3,
as shown in Fig. 2, needs to be done
inside the wooden switchboard box. This
permits the user to operate the lamp
and fan during cleaning of the toilet or
for bypassing the circuit, when bath-
room or toilet undergo repair work.
ELECTRONICS FOR YOU ❚  MARCH 2001
Construction

2001
 CONSTRUCTION

INTERFACE YOUR PRINTER WITH be printed and stores them in an inter-

nal buffer. When the printer detects a

8085 MICROPROCESSOR
carriage return (0dH), it prints out the
first row of characters from the printer
NA buffer. When the printer detects a sec-
ANJA
RUP ond carriage return, it prints out the
second row of characters. The process
SHAILA GHANTI continues until the desired characters
are printed.
Transfer of ASCII

I
t is very convenient to interface a codes from the micro-
printer to print 8085 programs. processor to a printer
Here a simple hardware interface needs to be done on
circuit with its driver software is de- a handshake basis be-
scribed that would enable students to cause the micropro-
take printout of the 8085 programs in cessor can send char-
hexadecimal codes along with their acters much faster
memory locations in the format: Fig. 2: System’s block diagram than the printer can
XXXX DD, print them.
where XXXX is the 4-bit hexadecimal The printer
address and DD is 2-bit hexadecimal must in some
data. way let the mi-
For most types of printers, the data croprocessor
to be printed is sent to the printer as know that its
ASCII characters on eight parallel lines. buffer is full,
The printer receives the characters to and it cannot
accept any
more charac-
ters until it
prints out
some of the al-
ready stored
characters. A
common stan-
dard for inter-
Fig. 1: Timing diagram facing with
parallel print-
TABLE I ers is the
Pin Assignments of Centronics Centronics in-
Interface Connector terface.
Pin no. Signal Direction
2 Data bit 0 (D0) In
3 Data bit 1 (D1) In Centronics
4 Data bit 2 (D2) In
5 Data bit 3 (D3) In interface
6 Data bit 4 (D4) In Centronics
7 Data bit 5 (D5) In
8 Data bit 6 (D6) In printers usu-
9 Data bit 7 (D0) In ally have a 36-
1 Strobe (STR) In pin interface
14 Auto Feed (AF) In connector. The
36 Device Select (DSL) In pin assign-
31 Initialise (INIT) In ments of the
11 Busy (BSY) Out significant
13 Select (SEL) Out pins of
32 Error (ERR) Out
Centronics in-
12 Paper end (PE) Out
19 to terface connec-
30, 33 Ground — tor, used in
Fig. 3: Schematic diagram of the printer interface circuit
this project,
ELECTRONICS FOR YOU ❚  MARCH 2001
 CONSTRUCTION

8085 ASSEMBLY LANGUAGE LISTING

Memory Instructions Code Comments Memory Instructions Code Comments
location location
7112 XCHG 1B Exchange DE with HL pair so that 7157 71
HL is initialised to starting memory 7158 MVI B,04 06 Else counter of 4 is initialised in B
location of the program to be printed. 7159 04 register to print 4 digits of memory
7113 LXI D 2A20 11 Initialise memory locations to store 715A CALL 7220 CD address (use subroutine to transfer
7114 20 ASCII codes of the program. 715B 20 data to printer in polling mode).
7115 2A 715C 72
7116 MOV A,H 7C To get the ASCII codes of addresses 715D INX H 23 Get next memory location
7117 CALL 70FC CD of memory location of the program to 715E DCR B 05 Check whether 4 characters are
7118 FC be printed using the subroutine. 715F JNZ 715A C2 transferred.
7119 71 7160 5A
711A MOV A,H 7C 7161 71
711B CALL7100 CD 7162 MVI A, 20 3E Send the (20) blank space to printer
711C 00 7163 20
711D 71 7164 OUT 08 D3
711E MOV A,L 7D 7165 08
711F CALL 70FC CD 7166 MVI A,09 3E To generate STROBE pulse to printer
7120 FC 7167 09
7121 70 7168 OUT 0B D3
7122 MOV A,L 7D 7169 0B
7123 CALL 7100 CD 716A MVI A,08 3E
7124 00 716B 08
7125 71 716C OUT 0B D3
7126 MOV A,M 7E To get the ASCII codes of the 716D 0B
7127 CALL 70FC CD contents of the program to be 716E MVI C,02 0E Counter of 2 is initialised in C register
7128 FC printed using the subroutine. 716F 02 to print 2 codes.
7129 70 7170 CALL 7220 CD Use subroutine to transfer data.
712A MOV A,M 7E 7171 20 in polling mode.
712B CALL 7100 CD 7172 72
712C 00 7173 INX H 23 Get next memory location
712D 71 7174 DCR C 0D Check whether 4 characters are
712E INX H 23 Increment pointer to mem. location. 7175 JNZ 7170 C2 transferred.
712F MOV A,M 7E Move contents of mem. into acc. 7176 70
7130 CPI CF FE Whether it is end of the program. 7177 71
7131 CF 7178 MVI A, 0A 3E Send LF code to printer.
7132 JNZ 7116 C2 If not, start executing from 7116. 7179 0A
7133 16 717A OUT 08 D3
7134 71 717B 08
7135 MVI A,43 3E If it is end of the program, 717C MVI A,0D 3E Send CR code to printer.
7136 43 transfer the code for CF. 717D 0D
7137 STAX D 12 717E OUT 08 D3
7138 INX D 13 717F 08
7139 MVI A, 46 3E 7180 MVI A,09 3E
713A 46 7181 09
713B STAX D 12 7182 OUT 0B D3
713C DCX D 1B 7183 0B
713D LXI H 2A20 21 Initialise mem. pointer to block 7184 MVI A,08 3E
713E 20 (2A20) where ASCII codes of charac- 7185 08
713F 2A ters to be printed are stored. 7186 OUT 0B D3
7140 MVI A, 82 3E Initialise 8255. 7187 MOV A,E 7B Check wheter the full program
7141 82 7188 XRA L Ad codes are transferred to printer
7142 OUT 0B D3 Write control word in control register 7189 JNZ 7158 C2 If not, continue to transfer next
7143 0B of 8255. 718A 58 codes.
7144 MVI A, 0B 3E Reset printer. 718B 71
7145 0B 718C MOV A,D 7A
7146 OUT 0B D3 718D XRA H AC
7147 0B 718E JNZ 7158 C2 Else, stop executing the program.
7148 CALL 7200 CD Delay for a few microseconds. 718F 58
7149 00 7190 71
714A 72 7191 RST 1 CF
714B MVI A,05 3E Send SELECT signal.
714C 05 Subroutine for converting hexadecimal to ASCII codes
714D OUT 0B D3 70FC RRC 0F Rotate right 4 times to get 4 MSB.
714E 0B 70FD RRC 0F
714F IN 09 DB Read the status of printer to find 70FE RRC 0F
7150 09 out whether the printer is selected. 70FF RRC 0F
7151 ANI 02 E6 7100 ANI 0F E6 Mask 4 LSBs
7152 02 7101 0F
7153 CPI 02 FE 7102 CPI 0A FE Compare with 0A
7154 02 7103 0A
7155 JNZ 714F C2 If printer is not selected, again read 7104 JC 7109 DA If it is less than 0A,
7156 4F the status of printer 7105 C6

ELECTRONICS FOR YOU ❚  MARCH 2001

 CONSTRUCTION

Memory Instructions Code Comments Memory Instructions Code Comments

location location
7106 70 722E OUT 08 D3 location, send the data to printer to
7107 ADI 07 C6 Add 07 to data 722F 08 print.
7108 07 7230 MVI A,08 3E Send the strobe pulse with min
7109 ADI 30 C6 Else add 30H to data to convert data 7231 08 0.5µs duration.
710A 30 into ASCII code. 7232 OUT 0B D3
710B STAX D 12 7233 0B
710C INX D 13 7234 MVI A,09 3E
710D RET C9 7235 09
7236 OUT 0B D3
Subroutine to transfer data in polling mode: 7237 0B
7220 MVI A 09 3E To generate the STROBE signal 7238 MVI A,08 3E
7221 09 7239 08
7222 OUT 0B D3 723A OUT 0B D3
7223 0B 723B 0B
7224 IN 09 DB Find whether the printer is not BUSY 723C RET C9
7225 09
7226 ANI 01 E6 Subroutine for delay:
7227 01 7200 MVI C, FF 0E Load C register with data FF.
7228 CPI 00 FE 7201 FF
7229 00 7202 DCR C 0D Decrement the contents of C reg.
722A JNZ 7224 C2 7203 JNZ 7202 C2 If the contents of C is not zero, go to
722B 24 7204 02 7202.
722C 72 7205 72
722D MOV A,M 7E Get the ASCII code from memory 7206 RET C9

MODIFIED PROGRAM USED BY EFY

Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks
9000 310095 LXI SP,9500H ;Initialise stack pointer 9049 D308 OUT 08H
9003 11209D LXI D,9D20H ;Store location where 904B CD5092 CALL 9250H ;Call status
9006 EB XCHG ;data to be printed starts 904E CD7092 CALL 9270H ;Call strobe
;into register pair DE 9051 0604 X4: MVI B,04H ;Counter of 4 for printing
9007 11209A LXI D,9A20H ;Location where ASCII 9053 CD2492 X2: CALL 9224H ;four digits of addresses
900A 7C X1: MOV A,H ;conversion of data is 9056 23 INX H ;of memory location
;stored 9057 05 DCR B
900B CDFC90 CALL 90FCH ;Convert addresses of 9058 C25390 JNZ X2
900E 7C MOV A,H ;mem. locations of data 905B 3E20 MVI A,20H ;Send blank space to
900F CD0091 CALL 9100H ;to be printed into ASCII ;printer
9012 7D MOV A,L 905D D308 OUT 08H
9013 CDFC90 CALL 90FCH 905F CD5092 CALL 9250H ;Call status
9016 7D MOV A,L 9062 CD7092 CALL 9270H ;Call strobe
9017 CD0091 CALL 9100H 9065 0602 MVI B,02H ;Counter of 2 for printing
901A 7E MOV A,M ;Convert data to be 9067 CD2492 X3: CALL 9224H ;two digits of data
901B CDFC90 CALL 90FCH ;printed into ASCII 906A 23 INX H
901E 7E MOV A,M 906B 05 DCR B
901F CD0091 CALL 9100H 906C C26790 JNZ X3
9022 23 INX H 906F CD9092 CALL 9290H ;Call LFCR
9023 7E MOV A,M 9072 7B MOV A,E ;Check whether all data
9024 FECF CPI CFH ;End of data? 9073 AD XRA L ;has been transfered for
9026 C20A90 JNZ X1 ;printing
9029 3E43 MVI A,43H ;ASCII code of C 9074 C25190 JNZ X4
902B 12 STAX D 9077 7A MOV A,D
902C 13 INX D 9078 AC XRA H
902D 3E46 MVI A,46H ;ASCII code of F 9079 C25190 JNZ X4
902F 12 STAX D 907C 3E03 MVI A,03H ;ASCII code for end of
9030 1B DCX D ;text
9031 21209A LXI H,9A20H ;Initialise mem. pointer 907E D308 OUT 08H
;to start of ASCII codes 9080 CD5092 CALL 9250H ;Call status
9034 3E82 MVI A,82H ;Initialise 8255 9083 CD7092 CALL 9270H ;Call strobe
9036 D30B OUT 0BH 9086 3E04 MVI A,04H ;ASCII code for end of
9038 3E30 MVI A,30H ;Initialise Printer 9088 D308 OUT 08H ;transmission
903A D30A OUT 0AH 908A CD5092 CALL 9250H ;Call status
903C 3E10 MVI A,10H 908D CD7092 CALL 9270H ;Call strobe
903E D30A OUT 0AH 9090 76 HLT
9040 CD0092 CALL 9200H ;Call delay
9043 3E30 MVI A,30H ;Subroutine for converting hex to ASCII
9045 D30A OUT 0AH 90FC 0F RRC ;Rotate four times to get
9047 3E02 MVI A,02H ;ASCII code for start of ;MSB
;text 90FD 0F RRC

ELECTRONICS FOR YOU ❚  MARCH 2001

 CONSTRUCTION

Addr. Hex code Label Mnemonics Remarks Addr. Hex code Label Mnemonics Remarks
90FE 0F RRC 925B CA6692 JZ X11
90FF 0F RRC 925E 0D DCR C
9100 E60F ANI 0FH ;Mask four bits of LSB 925F C25392 JNZ X8
9102 FE0A CPI 0AH 9262 05 DCR B
9104 DA0991 JC X5 9263 C25192 JNZ X9
9107 C607 ADI 07H 9266 C1 X11: POP B
9109 C630 X5: ADI 30H 9267 C9 RET
910B 12 STAX D
910C 13 INX D ;Strobe subroutine
910D C9 RET 9270 3E20 MVI A,20H
9272 D30A OUT 0AH
;Output Subroutine 9274 C5 PUSH B
9224 7E MOV A,M ;Output one byte of data 9275 0EFF MVI C,FFH
9225 D308 OUT 08H 9277 0D X10: DCR C
9227 CD5092 CALL 9250H ;Call status 9278 C27792 JNZ X10
922A CD7092 CALL 9270H ;Call strobe 927B C1 POP B
922D C9 RET 927C 3E30 MVI A,30H
927E D30A OUT 0AH
;Delay Subroutine 9280 C9 RET
9200 C5 PUSH B
9201 06FF MVI B,FFH ;Line feed and Carriage return Subroutine
9203 0EFF X7: MVI C,FFH 9290 3E20 MVI A,20H ;ASCII code for Space
9205 0D X6: DCR C 9292 D308 OUT 08H
9206 C20592 JNZ X6 9294 CD5092 CALL 9250H ;Call status
9209 05 DCR B 9297 CD7092 CALL 9270H ;Call strobe
920A C20392 JNZ X7 929A 3E0A MVI A,0AH ;ASCII code for Line feed
920D C1 POP B 929C D308 OUT 08H
920E C9 RET 929E CD5092 CALL 9250H ;Call status
92A1 CD7092 CALL 9270H ;Call strobe
;Status Subroutine 92A4 3E0D MVI A,0DH ;ASCII code for Carriage
9250 C5 PUSH B ;Return
9251 06FF X9: MVI B,FFH 92A6 D308 OUT 08H
9253 0EFF X8: MVI C,FFH 92A8 CD5092 CALL 9250H ;Call status
9255 DB09 IN 09H ;In port B 92AB CD7092 CALL 9270H ;Call strobe
9257 E60F ANI 0FH ;Compare with 06H 92AE C9 RET
9259 FE06 CPI 06H

(not busy), send anto receive the next character, the BUSY
TABLE II ASCII code on the signal will be low. The process contin-
Port B of 8255—(Input) Status Signals eight parallel dataues.
Cent. pin no. 12 32 13 11 lines. After at least 0.5The 8085 microprocessor is inter-
Signal PE ERR SEL BSY Comments µs, assert the STROBE
faced to the printer through 8255 pro-
Data B3 B2 B1 B0
signal low to tell the
grammable peripheral interface device
0 1 1 0 =06H (status OK)
printer that a charac-
as shown in the block diagram (Fig. 2)
and the detailed interface dia-
TABLE III gram (Fig. 3). One end of the
Port C of 8255—(Output) Control Signals cable, which is used for connect-
Cent. pin no. NU 14 31 1 NU 36 NU NU ing 8255 to the printer, should
Signal AF INIT STR DSL Comments normally have a 26-pin FRC con-
Data C7 C6 C5 C4 C3 C2 C1 C0
nector to meet with the corre-

}
X 0 1 1 X 0 X X =30H printer
X 0 0 1 X 0 X X =10H initiali- sponding connector on the kit,
long delay sation and the other end should have a
X 0 1 1 X 0 X X =30H 36-pin male Centronics connec-

}
X 0 1 0 X 0 X X =20H tor to go into the corresponding
Short delay strobe
X 0 1 1 X 0 X X connector on the printer.
=30H
NU=Not Used
Port A of 8255 is used for
transferring the data to the
are given in Table I. ter has been sent. The strobe signal printer. Port B is used for checking the
Fig. 1 shows the timing waveforms going low causes the printer to assert status signals coming from the printer.
for transferring data characters to the its BUSY signal high. After a minimum Port C is used for sending the control
printer using the basic handshake sig- time of 0.5 µs, the strobe signal can be signals required to activate the printer.
nals. Assuming that the printer has raised high again. Note that the data The interface signals between 8255 and
been initialised, first check the busy must be held valid on the data lines for the printer should be connected as
signal pin to see if the printer is ready at least 0.5 µs after the strobe signal is shown in Table I.
to receive data. If this signal is low made high. When the printer is ready (EFY Lab note. The maximum cur-

ELECTRONICS FOR YOU ❚  MARCH 2001


Fig. 4: Actual-size, single-sided PCB for
the printer interface circuit
Fig. 5: Component layout for the PCB
rent that an 8255 output pin can source
and sink is limited to 400 µA and 2.5
mA, respectively. To enhance this capa-
bility, open-collector hex buffers/drivers
7407 shown in Fig. 3 were used for all
output port pins. For input port pins,
there is no danger of overloading, and
hence these pins were connected directly
from the printer to the kit.)
Printer driver program overview
During initialisation, some memory lo-
cations are kept aside to store the ASCII
equivalent of the characters that are to
be printed. This is followed by configu-
ration (initialisation) of 8255 by send-
ing the mode control word to its control
register. To initialise the printer, first
CONSTRUCTION
PARTS LIST
Semiconductors:
IC1, IC2 - 7407 hex buffer/driver (open-
collector type)
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1-R12 - 1-kilo-ohm (or use one-/two-
resistor networks)
Miscellaneous:
- Centronics connector and
cable
send initialisation (INIT*) pulse for a
few microseconds. Then send the select
signal (DSL*) to select the printer. Read
the status to find out whether the
printer is selected and the BUSY signal
is low. Now send the ASCII character
to print the character, followed by the
STROBE* pulse for 0.5 µs. The process
continues till the end of the program.
The end of the program is indicated us-
ing RST1 (CFH).
The starting location of the program
to be printed should be stored in D and
E registers. The eight MSBs and eight
LSBs of memory location should be
stored in D register and E register, re-
spectively. The complete software pro-
gram is given (page 46) with comments
as necessary.
(EFY Lab note. The original pro-
gram was tried many times, but we did
not succeed. Finally, the program was
extensively modified and successfully
run using Epson 9-pin printer. The pro-
gram, along with Tables II and III show-
ing the status and control signals that
have been used in program implemen-
tation, is included (page 47) for the ben-
efit of readers, who may try both the
programs, if desired.)
Address map of devices used:
RAM locations used: 9000H to 92AEH (70FCH
onwards used by author)
PORT A (output) : 08H
PORT B (input) : 09H
PORT C (output) : 0AH
Control word register : 0BH
Important memory locations :
Stack pointer initialised : 9500H
Data to be printed is stored at : 9D20H onward
ASCII conversion of data to be printed starts
at: 9A20H. Data to end with CFH as the last
byte.
The actual-size, single-sided PCB
layout of the printer interface circuit
and the component layout are shown in
Figs 4 and 5, respectively. ❏
ELECTRONICS FOR YOU ❚  MARCH 2001
 C O N S T R U C T I O N

MORSE PROCESSOR RUP

ANJA
NA Hardware
The circuit is configured around the ba-
sic 8085 microprocessor. For simplify-
JUNOMON ABRAHAM ing the overall design, a programmable
keyboard/display interface 8279 chip has
been used, which relieves the micropro-

M
orse code, introduced by mission and reception of Morse code. It
Samuel Morse, is still used can find application in ham radio, te- cessor from scanning the keyboard and
universally even though bet- legraphy, etc. display. Here, 25 keys, including SHIFT
ter modes of communication are now and CNTL keys, and six 7-segment com-
available. Following are the main rea- TABLE III
sons for its preference over other means
DATA FORMAT IN SCAN KEY BOARD MODE
of communication: (FOR ANALYSING RETURNED HEX CODE)
1. It enables communication with
distant stations, using low-power trans-
mitters.
2. It avoids the problems of regional
accents and pronunciation.
3. It has the ability to override noise
as it occupies only a fraction of the band-
width required for a radio telephony
signal.
The circuit presented here converts
text into
TABLE I the corre-
7-segment Display sponding
M o r s e
code, and
vice versa.
The high-
light of
this circuit
is that it
can inter-
pret Morse
signals
TABLE IV
available
in the form Lookup Table
of sound Chr/ Address Hexcode Ch/ Address Hexcode Ch/ Address Hexcode
word word word
from ham
0 0300 3F AA 0E 00 J 034C 1E A9 03 00 . 03B4 80 99 39 00
radio or 1 0304 06 A9 0E 00 K 0350 70 E6 00 00 , 03B8 04 5A 3A 00
any other 2 0308 5B A5 0E 00 L 0354 38 59 03 00 ; 03BC 84 66 36 00
source. It 3 030C 4F 95 0E 00 M 0358 55 3A 00 00 ? 03C0 D3 A5 35 00
is very 4 0310 66 55 0E 00 035C 46 – 03C4 08 56 39 00
5 0314 6D 55 0D 00 03C8 00 3F 00 00
useful for 6 0318 7D 56 0D 00 N 0380 54 36 00 00 EOM* 03CC 0F 99 0D 00
not only 7 031C 07 5A 0D 00 O 0384 5C EA 00 00 WAIT* 03D0 7E 59 0D 00
learning 8 0320 7F 6A 0D 00 P 0388 73 69 03 00 BT* 03D4 49 56 0E 00
9 0324 6F AA 0D 00 Q 038C 67 9A 03 00 SK* 03D8 4F 95 39 00
but also A 0328 77 39 00 00 R 0390 50 D9 00 00 SELECt 03DC 6D 79 38 79
for trans- B 032C 7C 56 03 00 S 0394 6D D5 00 00 03E0 39 78 78 50
C 0330 39 66 03 00 T 0398 78 0E 00 00 trAnSt 03E4 77 54 6D 78
D 0334 5E D6 00 00 U 039C 3E E5 00 00 M oVEr 03E8 55 00 5C 2A
TABLE II E 0338 79 0D 00 00 V 03A0 2A 95 03 00 rECEIE 03EC 79 50 50 79
Address Distribution F 033C 71 65 03 00 W 03A4 6A E9 00 00 03F0 39 79 30 79
G 0340 3D DA 00 00 X 03A8 52 96 03 00 SEtUP 03F4 6D 79 78 3E
Device Address H 0344 76 55 03 00 Y 03AC 6E A6 03 00 03F8 73 00 00 00
EPROM 0000 to 03FF I 0348 30 35 00 00 Z 03B0 4B 5A 03 00 03FC 00 00 00 00
RAM 1000 to 17FF
8279: *Notes: 1. EOM=End of message= 2. WAIT=
Command Port 21 3. BT=Sentence separation= 4. SK=End of work=
Data Port 20

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

mon-cathode
character dis-
plays are used.
Though 7-seg-
ment displays
are not suitable
for alphanu-
meric charac-
ters, these have
been used here
with some com-
promise for re-
ducing the over-
all cost. (Note.
The use of dot-
matrix LCD dis-
play avoids the
difficulty in dis-
playing charac-
ters in 7-seg-
ment format.
One can go for
a microcont-
roller design, if
needed.) The 7-
segment display
pattern em-
ployed for dif-
ferent charac-
ters is shown in
Table I.
Fig. 1: Schematic circuit of Morse processor

Two hard-
ware inter-
rupts, RST5.5
and RST6.5, are
used for reading
the key entries.
These are
driven by the
IRQ line from
the keyboard/
display inter-
face IC 8279.
A buffer
(IC8) is con-
nected at the
display output
of 8279 to drive
the 7-segment
displays. The
encoded scan
lines (SL2 -
SL0) are de-
coded by an oc-
tal decoder
74LS138 (IC9),
whose outputs
drive the com-
mon cathode of
displays via

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

PARTS LIST
Semiconductors:
IC1 - 8085A microprocessor
IC2 - 74LS373 octal D-type latches
IC3 - 6116 RAM (2 kB)
IC4 - 27C32 EPROM (4 kB)
IC5 - 8279 keyboard/display
decoder
IC6, IC9 - 74LS138 3-bit binary decoder
IC7 - 74LS123 retriggerable
monostable multivibrator
IC8 - 74LS244 octal bus driver
IC10 - 7805 +5 volt regulator
T1 - BC548 npn transistor
T2 - BC549 npn transistor
T3-T8 - BC558 pnp transistor
D1 - 1N4148 switching diode
LED1 - LED
DIS1-DIS6 - LTS543 common-cathode
display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1 - 68-kilo-ohm
R2 - 3.3-kilo-ohm
R3 - 2.2-kilo-ohm
R4 - 5.6-kilo-ohm
R5 - 1-mega-ohm
R6 - 15-kilo-ohm
R7, R8 - 1-kilo-ohm
R9-R16 - 68-ohm
R17-R22 - 220-ohm
R23 - 180-ohm
VR1 - 2.2-kilo-ohm preset
VR2 - 100-ohm preset
Capacitors:
C1 - 2.2µF, 16V electrolytic
C2, C4, C6 - 0.1µF ceramic disc
C3 - 10µF, 16V electrolytic
C5 - 0.001µF ceramic disc
C7 - 10pF ceramic disc
Miscellaneous:
PZ1 - Piezo buzzer
MIC - Condenser microphone
S1-S26 - Tactile switches for keyboard
XTAL - 6.144 MHz crystal

transistor switches. The keys are wired

in such a way that these can be repre-
sented by the seven higher order bits of
the keyboard data.
Morse signals in the form of sound
are converted to microprocessor-compat-
ible signals. The arrangement comprises
condenser microphone, preamplifier,
and retriggerable monostable
multivibrator 74LS123 (IC7). The out-
put of IC7 drives SID pin of 8085 and it
is in ‘high’ logic state when a sound is
detected by the microphone. The sensi-
tivity of the amplifier can be adjusted
by preset VR2.
The converted Morse code drives a
piezo buzzer via a transistor connected
at the SOD line of 8085 microprocessor.
Intensity of the sound can be controlled
by potentiometer VR1.
The firmware is stored in 27C32 (4k
Fig. 2: Actual-size, single-sided PCB for the Morse processor EPROM— only 1 kB is needed for the

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

program). RAM 6116 stores the key-

board entries and also acts as a stack.
One can enter/store a maximum of ap-
proximately 1,750 characters in the
RAM. This is adequate for normal ap-
plications. In case one needs to store
lengthy text, one should use a larger-
capacity RAM. Battery backup may be
used for avoiding loss of data due to
power failure. The low-level address/
data lines of 8085 are demultiplexed
using an octal transparent latch IC
74LS373.
The address bits A12 and A13 are
decoded by IC6 to generate chip select
(CS) signals for various ICs. The ad-
dress map of devices is indicated in
Table II.

Firmware
The software driver routines for the cir-
cuit, along with their Assembly language
code, are listed in Appendix A. Basi-
cally, the following functions are per-
formed by the software program:
(a) Initialisation of the peripherals.
(b) Reading the depressed key data
and its storage in RAM.
(c) Writing data into the display
RAM in 8279.
(d) Generation of Morse code.
(e) Recognition of Morse code from
its sound.
(f) Giving proper messages at ap-
propriate time.
Since Morse code is a time-depen-
dent code, the program contains many
jump instructions. The program has
been made interactive and user-friendly.
The firmware is divided into the follow-
ing modules: (a) booting, (b) keyboard,
(c) transmit, (d) receive, (e) play, and
(f) lookup table.
The logic of the program can be gen-
erally understood from the Assembly
language listing given in Appendix A. A
brief description of each module is, how-
ever, given below:
(a) Booting. This section initialises
stack pointer 8279 and the interrupts.
It also fixes default speed for Morse
code. It is the first module executed
when you switch on the power supply.
(b) Keyboard. When a key is
pressed, IRQ pin of 8279 interrupts
8085. The ISR (interrupt service rou-
tine) reads the keyboard data and, if
needed, does some manipulations. It also
Fig. 3: Component layout for the PCB displays the entered characters in the

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

APPENDIX ‘A’: 8085 ASSEMBLY LANGUAGE PROGRAM LISTING

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments
Booting 0081 FE92 CPI 92H Checking CNTL+ßkey
0000 31FF17 LXI SP,17FFH Initialise stack pointer 0083 C28900 JNZ 0089H
0003 3E10 MVI A,10H Initialise 8279 0086 2B DCX H Shifting the characters
0005 D321 OUT 21H 0087 2B DCX H right by one place
0007 3E40 MVI A,40H 0088 C9 RET
0009 D321 OUT 21H 0089 FE90 CPI 90H Checking CNTL+àkey
000B 3E0D MVI A,0DH 008B C8 RZ Shifting the characters
000D 30 SIM Activating RST6.5 by one place
000E 325017 STA 1750H Updating mode and 008C FE80 CPI 80H Checking CNTL+TABR
position data key
0011 211D00 LXI H,001DH 008E C29600 JNZ 0096H
0014 225117 SHLD 1751H 0091 110500 LXI D,0005H Shifting the characters
0017 21246C LXI H,6C24H Fixing default setup left by six places
001A 227017 SHLD 1770H 0094 19 DAD D
001D 11DC03 LXI D,03DCH 0095 C9 RET
0020 CDE000 CALL DISPLAY Display ‘SELECt’ 0096 FE82 CPI 82H Checking CNTL+TABL
0023 FB EI key
0024 76 HLT Halt 0098 C2A000 JNZ 00A0H
009B 11F9FF LXI D,FFF9H Shifting the characters
RST 5.5 right by six places
002C C3F700 JMP 00F7H Go to ISR of RST5.5 009E 19 DAD D
009F C9 RET
RST 6.5 00A0 FE88 CPI 88H Checking CNTL+
0034 DB20 IN 20H Reading keyboard data START key
from IC 8279 00A2 CA1001 JZ TRANSMIT
0036 F5 PUSH PSW Store it in the stack 00A5 FE96 CPI 96H Checking CNTL+DEL
0037 FE8A CPI 8AH Checking CNTL+ key
RECEIVE key 00A7 C2BA00 JNZ 00BAH
0039 CA0002 JZ RECEIVE 00AA E5 PUSH H
003C FE8C CPI 8CH Checking CNTL+ 00AB 46 MOV B,M Delete one character in
TRANSMIT key the left most position of
003E CA8001 JZ KEYBOARD the display
0041 FE84 CPI 84H Checking CNTL+PLAY 00AC 2B DCX H
key 00AD 70 MOV M,B
0043 CAD001 JZ PLAY 00AE 23 INX H
0046 FE86 CPI 86H Checking CNTL+ 00AF 23 INX H
CONTINUE key 00B0 7C MOV A,H
0048 CAD501 JZ 01D5H 00B1 FE17 CPI 17H
004B FE98 CPI 98H Checking CNTL+ 00B3 DAAB00 JC 00ABH
CLEAR key 00B6 E1 POP H
004D C26000 JNZ 0060H 00B7 2B DCX H
0050 210010 LXI H,1000H Clearing the RAM 00B8 2B DCX H
0053 36C8 MVI M,C8H 00B9 C9 RET
0055 23 INX H 00BA FE94 CPI 94H Checking CNTL+INS
0056 7C MOV A,H key
0057 FE17 CPI 17H 00BC C2D100 JNZ 00D1H
0059 DA5300 JC 0053H 00BF 2B DCX H Inserting a space for
005C 2A5117 LHLD 1751H Return to mode from adding character
005F E9 PCHL where clearing action 00C0 E5 PUSH H
is called 00C1 46 MOV B,M
0060 FE8E CPI 8EH Checking CNTL+ 00C2 36C8 MVI M,C8H
SETUP key 00C4 23 INX H
0062 C27700 JNZ 0077H 00C5 7E MOV A,M
0065 3E0E MVI A,0EH Activating RST5.5 00C6 70 MOV M,B
0067 30 SIM 00C7 47 MOV B,A
0068 11F403 LXI D,03F4H 00C8 7C MOV A,H
006B CDE000 CALL DISPLAY Display the message 00C9 FE17 CPI 17H
‘SEtUP’ 00CB DAC400 JC 00C4H
006E FB EI 00CE E1 POP H
006F 76 HLT 00CF 2B DCX H
0070 3E0D MVI A,0DH Activating RST6.5 00D0 C9 RET
0072 30 SIM 00D1 FE7F CPI 7FH Checking whether key
0073 2A5117 LHLD 1751H data is valid character
0076 E9 PCHL Return to mode from 00D3 D2CF00 JNC 00CFH
where setup action is 00D6 07 RLC
called 00D7 77 MOV M,A Enter it into the RAM
0077 3A5017 LDA 1750H The following CNTL 00D8 C9 RET Return
007A B7 ORA A key functions are only
for TRANSMIT mode DISPLAY SUBROUTINE:
007B CA8000 JZ 0080H Checking whether we 00E0 0E06 DISPLAY: MVI C,06H Display six characters
were in the TRANSMIT taken from lookup table
mode 00E2 1A LDAX D Lookup table is pointed
007E FB EI to by DE -reg pair
007F 76 HLT 00E3 D320 OUT 20H
0080 F1 POP PSW Getting key closure 00E5 13 INX D
data 00E6 0D DCR C
which is stored in stack 00E7 C2E200 JNZ 00E2H

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments
00EA CDC001 CALL DELAY2 Wait for some time 017A E1 POP H
00ED CDC001 CALL DELAY2 017B C9 RET
00F0 C9 RET Return
KEYBOARD SUBROUTINE:
VECTOR RST 5.5 0180 AF KEYBOARD:XRA A Updating mode and
00F7 DB20 IN 20H Reading key closure positing data
data from 8279 0181 325017 STA 1750H
00F9 E63F ANI 3FH 0184 218001 LXI H,0180H
00FB 07 RLC 0187 225117 SHLD 1751H
00FC 327017 STA 1770H Storing dot value 018A 11E203 LXI D,03E2H Displaying message
00FF 47 MOV B,A 018D CDE000 CALL DISPLAY ‘trAnSt’ for indicating
0100 80 ADD B the TRANSMIT mode
0101 80 ADD B 0190 31FF17 LXI SP,17FFH
0102 327117 STA 1771H Storing dash value 0193 210610 LXI H,1006H Entering keyboard data
0105 C9 RET Return to the RAM
0196 11FBFF LXI D,FFFBH
TRANSMIT SUBROUTINE: 0199 19 DAD D
0110 31FF17 TRANSMIT: LXI SP,17FFH 019A 0E06 MVI C,06H
0113 7C MOV A,H 019C 1603 MVI D,03H
0114 FE17 CPI 17H Checking end of mem. 019E 5E MOV E,M
0116 D2B301 JNC 01B3H 019F 1A LDAX D
0119 1603 MVI D,03H 01A0 D320 OUT 20H
011B 5E MOV E,M 01A2 23 INX H
011C 1A LDAX D 01A3 0D DCR C
011D D320 OUT 20H Display character in 01A4 C29E01 JNZ 019EH
the RAM 01A7 7C MOV A,H
011F F3 DI 01A8 FE17 CPI 17H Checking end of mem.
0120 E5 PUSH H 01AA DAB301 JC 01B3H
0121 0E04 MVI C,04H Morse code generation 01AD 11E803 LXI D,03E8H
0123 13 INX D 01B0 CDE000 CALL DISPLAY If mem. is over display
0124 1A LDAX D ‘MoVEr’
0125 F5 PUSH PSW 01B3 FB EI
0126 217017 LXI H,1770H 01B4 76 HLT
0129 E603 ANI 03H 01B5 C39601 JMP 0196H
012B FE01 CPI 01H
012D CA4801 JZ 0148H DELAY2 SUBROUTINE:
0130 23 INX H 01C0 0E9F DELAY2: MVI C,9FH Wait approximately
0131 FE02 CPI 02H 400 msec
0133 CA4801 JZ 0148H 01C2 CD7001 CALL DELAY1
0136 FE03 CPI 03H 01C5 0D DCR C
0138 CA5901 JZ 0159H 01C6 C2C201 JNZ 01C2H
013B F1 POP PSW 01C9 C9 RET
013C E1 POP H
013D FB EI PLAY SUBROUTINE:
013E 7E MOV A,M 01D0 1603 PLAY: MVI D,03H
013F 23 INX H 01D2 210510 LXI H,1005H
0140 FECC CPI CCH Checking end of 01D5 F3 DI
message character ‘]’ 01D6 23 INX H
0142 C21001 JNZ 0110H 01D7 7C MOV A,H
0145 C3B301 JMP 01B3H 01D8 FE17 CPI 17H Checking end of mem.
0148 3ECD MVI A,CDH Setting SOD line 01DA D2EB01 JNC 01EBH
014A 30 SIM 01DD 5E MOV E,M
014B 46 MOV B,M 01DE 1A LDAX D
014C CD7001 CALL DELAY1 Waiting 01DF D320 OUT 20H Displaying data in RAM
014F 05 DCR B 01E1 CDC001 CALL DELAY2 Wait for some time
0150 C24C01 JNZ 014CH 01E4 FB EI
0153 3E4D MVI A,4DH Resetting SOD line 01E5 7E MOV A,M
0155 30 SIM 01E6 FECC CPI CCH Checking end of mem.
0156 217017 LXI H,1770H symbol ‘]’
0159 46 MOV B,M 01E8 C2D501 JNZ 01D5H
015A CD7001 CALL DELAY1 Waiting 01EB C3B301 JMP 01B3H Go to keyboard module
015D 05 DCR B
015E C25A01 JNZ 015AH RECEIVE SUBROUTINE:
0161 F1 POP PSW 0200 3EFF RECEIVE: MVI A,FFH Updating mode and
0162 0F RRC position data
0163 0F RRC 0202 325017 STA 1750H
0164 0D DCR C 0205 210002 LXI H,0200H
0165 C22501 JNZ 0125H 0208 225117 SHLD 1751H
0168 C32101 JMP 0121H 020B 11EE03 LXI D,03EEH
020E CDE000 CALL DISPLAY Display message
DELAY1 SUBROUTINE: ‘rECEIE’
0170 E5 DELAY1: PUSH H Executing these 0211 11FA03 LXI D,03FAH
instructions require 0214 CDE000 CALL DISPLAY Clear the display
approximately 0217 FB EI
0171 21CF01 LXI H,01CFH 3 msec 0218 110510 LXI D,1005H Morse code aquisition
0174 2B DCX H 021B 13 INX D
0175 7C MOV A,H 021C D5 PUSH D
0176 B5 ORA L 021D 218117 LXI H,1781H
0177 C27401 JNZ 0174H 0220 3600 MVI M,00H

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

Addr. Opcode Label Mnemonics Comments Addr. Opcode Label Mnemonics Comments
0222 2B DCX H 0276 0638 MVI B,38H Comparing obtained
0223 E5 PUSH H 0278 21FD02 LXI H,02FDH morse code data with
0224 0E00 MVI C,00H lookup data
0226 1E04 MVI E,04H 027B 3A8017 LDA 1780H
0228 61 MOV H,C 027E 23 INX H
0229 0600 MVI B,00H 027F 23 INX H
022B CD7001 CALL DELAY1 0280 23 INX H
022E 04 INR B 0281 23 INX H
022F 20 RIM Reading the SID pin 0282 05 DCR B
0230 07 RLC 0283 C29102 JNZ 0291H If given morse code is
0231 DA2B02 JC 022BH invalid, display ‘y’
0234 24 INR H 0286 FE04 CPI 04H
0235 3A7117 LDA 1771H 0288 DA1D02 JC 021DH
0238 BC CMP H Checking for the space 028B 215C03 LXI H,035CH
between characters 028E C39F02 JMP 029FH
0239 DA6602 JC 0266H 0291 BE CMP M
023C 78 MOV A,B 0292 C27B02 JNZ 027BH
023D FE02 CPI 02H 0295 3A8117 LDA 1781H
023F DA2902 JC 0229H 0298 23 INX H
0242 2600 MVI H,00H 0299 BE CMP M
0244 1640 MVI D,40H 029A 2B DCX H
0246 3A7117 LDA 1771H 029B C27B02 JNZ 027BH
0249 0F RRC 029E 2B DCX H
024A B8 CMP B Checking for dot and 029F D1 POP D
dash 02A0 7A MOV A,D
024B D25702 JNC 0257H 02A1 FE17 CPI 17H Checking end of mem.
024E 7A MOV A,D 02A3 D2D102 JNC 02D1H
024F 07 RLC 02A6 7E MOV A,M
0250 57 MOV D,A 02A7 D320 OUT 20H Display the character
0251 00 NOP 02A9 7D MOV A,L Store data, correspond-
0252 00 NOP 02AA 12 STAX D ing to displayed charac-
0253 00 NOP ter, in the RAM
0254 00 NOP 02AB 0600 MVI B,00H
0255 00 NOP 02AD 217017 LXI H,1770H
0256 00 NOP 02B0 7E MOV A,M
0257 79 MOV A,C Constructing morse 02B1 07 RLC
code data 02B2 23 INX H
0258 0F RRC 02B3 86 ADD M
0259 0F RRC 02B4 D2B802 JNC 02B8H
025A B2 ORA D 02B7 04 INR B
025B 4F MOV C,A 02B8 4F MOV C,A
025C 1D DCR E 02B9 0B DCX B
025D C22902 JNZ 0229H 02BA CD7001 CALL DELAY1
0260 E1 POP H 02BD 20 RIM
0261 71 MOV M,C 02BE 07 RLC
0262 23 INX H 02BF DA1B02 JC 021BH Check for space between
0263 C32302 JMP 0223H 02C2 78 MOV A,B words
0266 79 MOV A,C 02C3 B1 ORA C
0267 0F RRC 02C4 C2B902 JNZ 02B9H
0268 0F RRC 02C7 AF XRA A
0269 F6C0 ORI C0H 02C8 D320 OUT 20H Giving space in display
026B 1D DCR E 02CA 13 INX D
026C CA7402 JZ 0274H 02CB 3EC8 MVI A,C8H
026F 0F RRC 02CD 12 STAX D Store the space data
0270 0F RRC in the RAM
0271 C36B02 JMP 026BH 02CE C31B02 JMP 021BH Repeat the process
0274 E1 POP H 02D1 76 HLT Halt
0275 77 MOV M,A

7-segment display. (Table III has been
included by EFY for ready reference by
the readers to know the hex data gener-
ated by 8279 when any key is either
pressed alone or in combination with
SHIFT or CNTL key.)
(c) Transmit. This module converts
each character in the RAM to its corre-
sponding Morse code signals which are
output through the SOD line. The speed
of transmission or words per minute de-
pends on the value entered in the setup
menu.
(d) Receive. The acquisition of
Morse code is done by checking the pres-
ence of sound with time. This module
continuously monitors the SID pin of
8085 microprocessor, where the sound-
converted logic level (depending on
whether the sound is present or not) is
available. It compares this logic level
with a prefixed time value and accord-
ingly decides whether the sound was
due to dot or dash. Moreover, it dis-
plays characters corresponding to the
entered Morse code.
(e) Display. This module displays
characters in the moving display for-
mat as per the entered message. The
speed of movement is fixed to approxi-
mately three characters per second.
(f) Lookup table (Table IV). This
is a block of data, which contains the 7-
segment data for every character and
the data needed for Morse code genera-
tion or reception. Each character takes
four EPROM locations. The first loca-
tion indicates the 7-segment data, while
the second and third locations hold the
Morse code data. The fourth location is
unused. (EFY note. We have included
Table IV showing the hex data gener-
ated by depression of any key alone or
in combination with SHIFT or CNTL
keys, for ready reference by the readers.

ELECTRONICS FOR YOU ❚  MARCH 2001

 C O N S T R U C T I O N

Control-key functions
Before going to the operating procedure,
we have to know the functions of keys
associated with CNTL key.
CNTL+SETUP (8EH). The default
speed is initialised for approximately 5
words/minute. If you want to change
this setting, you can do so by using this
control key combination. When you
press this combination, the message
‘SEtUP’ is displayed. Here you can en-
ter any one of the characters ranging
from ‘1’ through ‘9’ and ‘A’ through ‘K’
to change the speed. Note that the mini-
mum speed is associated with ‘K’ and
the maximum with ‘1’.
CNTL+CLEAR (98H). It clears the
RAM content.
CNTL+PLAY (84). CNTL+PLAY is
used for displaying the RAM content in
moving format. You can interrupt any
process by pressing any control key that
has no function.
CNTL+CONT (86). It is used for
continuing the play operation if it were
interrupted.
5. Press CNTL+START keys for get-
ting Morse code of the message.
6. You can go to any other mode by
selecting the corresponding mode before
finishing the transmission or later.
7. For entering into the receive
mode, press the CNTL+RECEIVE keys.
You will see the ‘rECEIE’ message for
one second.
8. Generate Morse code using a
buzzer, voice, or some other source (such
as ham radio and recorded tape).
9. The acceptance of sound will be
indicated by LED1 for duration of ‘Dit’/
’Dash’. If LED does not light, adjust the
position of microphone or change the
gain of the amplifier using potmeter
VR2.
10. The converted data can be re-
played by pressing the CNTL+PLAY
keys.
Note 1. The clear and setup control
keys can be used, at any time, if needed.
Construction
PCB designed particularly for this cir-
cuit (as given in Fig. 2, with component
layout shown in Fig. 3) is needed for
making this circuit. IC bases are pre-
ferred for fixing the ICs. For continu-
ous operation, provide a heat sink for
the regulator IC. Since this circuit is
based on time comparison, it is neces-
sary to use the correct frequency crys-
tal (6.144 MHz).
EFY Note. Although the circuit has
been fully tested using the given firm-
ware, elaboration of certain software in-
structions, requested from the author,
is still awaited. These clarification,
when received, will be suitably published
in a coming issue.

Operating procedure
1. Switch on the power supply. A mes-
sage ‘SELECt’ will be displayed. By de-
pressing the appropriate key, you can
select any one of the following modes:
(a) transmit, (b) receive, (c) setup, (d)
play, (e) continue, and (f) clear.
2. Press CNTL+TRANSMIT keys for
entering into the transmit mode. A mes-
sage ‘trAnSt’ appears for a second, af-
ter which you can enter your message.
3. At the end of the message you
have to enter ‘]’ symbol (by pressing
SHIFT+] keys, i.e. 66H) for invoking the
microprocessor.
4. By the use of arrow keys (à or ß)
or by TAB (TAB R or TAB L) keys, set
the location in the message at which the
transmission is to start. If you want to
transmit the message from beginning,
depress CNTL+TRANSMIT keys again
for getting into the first character.

ELECTRONICS FOR YOU ❚  MARCH 2001

April

2001
Circuit Ideas

2001

EEPROM W27C512
(WINBOND) ERASER
J.P. SHARMA
E
PROMs (electrically erasable
PROMs) are generally erased by
ultraviolet rays, and it takes half
an hour or so to erase the data in an
ERPOM. Nowadays a special EEPROM
from Winbond is available in the market,
which is being used in telecommunica-
tion due to its low cost.
The simple, low-cost circuit presented
here takes only 100 ms to erase old pro-
grams electrically. The programming volt-
age VPP for the mentioned IC is 12.7V,
unlike the 28xxxx series EEPROMs that
can be written to or read like a RAM, in
situ. Multiple ICs connected in parallel
can be erased simultaneously using the
given circuit.
The circuit requires 15V to 20V DC.
Timer IC3 (LM555) is used for genera-
tion of clock pulses of 200 millisecond time
period with an ‘on’ time of 100 millisec-
onds. Pulse time is achieved by using pre-
CIRCUIT IDEAS
EDI
DWIV
S.C.
sets VR1 and VR2 and capacitor C1. The
‘on’/‘off’ time of pulse may be set with the
help of an oscilloscope or by taking ap-
propriate values of presets VR1 and VR2
(in-circuit resistances) and capacitor C1
using the following relationship:
On time=0.69VR1xC1=Off Time=
0.69VR2xC1=100 milliseconds
IC1 (7812) and IC2 (7805) are voltage
regulator ICs that are used to obtain regu-
lated 14V DC and 5V DC, respectively,
required for operation of the circuit. The
clock with time period of 200 milliseconds
is fed to IC4 (CD4017). In this IC, the
output is available successively only at
one of the output pins with a delay of 200
milliseconds when reset pin 15 is low. The
14V DC is made available via transistors
T1 and T2 to pins 22 and 24 of IC5
(27C512, which is the IC under erasure).
As soon as push-to-on switch S1 is
pressed momentarily, it resets IC4 by ap-
ELECTRONICS FOR YOU ❚  APRIL 2001
plication of 5V DC to reset pin 15, and
the output at pin 3 (Q0) goes high. This
high output is shifted to the next output
pin with the successive clock pulse re-
ceived at pin 14.
Q5 output from pin 1 of IC4 is in-
verted using transistor T3 and is given to
chip-enable pin 20 of IC5, when 14V DC
is already available at pins 22 and 24 of
IC5. All address pins, except pin 24 (A9),
are set low and all data pins (11 through
13 and 15 through 19) are at high level
(+5V). Then pins 22 and 24 are pulsed
low for 100 milliseconds. Immediately all
data (cells) are set high. (Data output is
high only in erased condition.)
At the end when Q9 output of IC4
goes high, transistor T4 conducts, pulling
its collector low. LED1 glows to indicate
completion of erasure. Simultaneously, pin
4 of timer IC3 is taken low to stop gen-
eration of further clock pulses until IC4
is reset.
Insert the next IC to be erased in IC5
socket (preferably use a ZIF socket) and
reset IC4 by pushing switch S1 momen-
tarily. It takes only 100 milliseconds to
erase the EEPROM IC.

INTELLIGENT
ELECTRONIC LOCK
K. UDHAYA KUMARAN
T
his intelligent electronic lock cir-
cuit is built using transistors
only. To open this electronic lock,
one has to press tactile switches S1
through S4 sequentially. For deception
you may annotate these switches with
different numbers on the control panel/
keypad.
For example, if you want to use ten
switches on the keypad marked ‘0’
through ‘9’, use any four arbitrary num-
bers out of these for switches S1 through
S4, and the remaining six numbers may
be annotated on the leftover six switches,
which may be wired in parallel to disable
switch S6 (shown in the figure). When
four password digits in ‘0’ through ‘9’ are
mixed with the remaining six digits con-
nected across disable switch terminals,
energisation of relay RL1 by unauthorised
person is prevented. For authorised per-
sons, a 4-digit password number is easy
to remember.
To energise relay RL1, one has to
press switches S1 through S4 sequentially
within six seconds, making sure that each
of the switch is kept depressed for a du-
CIRCUIT IDEAS
S.C.
DWIV
EDI
ration of 0.75 second to 1.25 seconds. The
relay will not operate if ‘on’ time dura-
tion of each tactile switch (S1 through
S4) is less than 0.75 second or more than
1.25 seconds. This would amount to re-
jection of the code.
A special feature of this circuit is that
pressing of any switch wired across dis-
able switch (S6) will lead to disabling of
the whole electronic lock circuit for about
one minute. Even if one enters the cor-
rect 4-digit password number within one
minute after a ‘disable’ operation, relay
RL1 won’t get energised. So if any
unauthorised person keeps trying differ-
ent permutations of numbers in quick
successions for energisation of relay RL1,
he is not likely to succeed. To that ex-
tent, this electronic lock circuit is fool-
proof.
This electronic lock circuit comprises
disabling, sequential switching, and relay
latch-up sections.
The disabling section comprises zener
diode ZD5 and transistors T1 and T2. Its
function is to cut off positive supply to
sequential switching and relay latch-up
ELECTRONICS FOR YOU ❚  APRIL 2001
sections for one minute when disable
switch S6 (or any other switch shunted
across its terminal) is momentarily
pressed.
During idle state, capacitor C1 is in
discharged condition and the voltage
across it is less than 4.7 volts. Thus ze-
ner diode ZD5 and transistor T1 are in
non-conduction state. As a result, the col-
lector voltage of transistor T1 is suffi-
ciently high to forward bias transistor T2.
Consequently, +12V is extended to se-
quential switching and relay latch-up sec-
tions.
When disable switch is momentarily
depressed, capacitor C1 charges up
through resistor R1 and the voltage avail-
able across C1 becomes greater than 4.7
volts. Thus zener diode ZD5 and transis-
tor T1 start conducting and the
collector voltage of transistor T1
is pulled low. As a result, tran-
sistor T2 stops conducting and
thus cuts off positive supply volt-
age to sequential switching and
relay latch-up sections.
Thereafter, capacitor C1
starts discharging slowly
through zener diode D1 and
transistor T1. It takes approxi-
mately one minute to discharge
to a sufficiently low level to cut-
off transistor T1, and switch on
transistor T2, for resuming sup-
ply to sequential switching and
relay latch-up sections; and un-
til then the circuit does not ac-
cept any code.
The sequential switching
section comprises transistors T3
through T5, zener diodes ZD1
through ZD3, tactile switches S1 through
S4, and timing capacitors C2 through C4.
In this three-stage electronic switch, the
three transistors are connected in series
to extend positive voltage available at the
emitter of transistor T2 to the relay latch-
up circuit for energising relay RL1.
When tactile switches S1 through S3
are activated, timing capacitors C2, C3,
and C4 are charged through resistors R3,
R5, and R7, respectively. Timing capaci-
tor C2 is discharged through resistor R4,
zener diode ZD1, and transistor T3; tim-
ing capacitor C3 through resistor R6, ze-
ner diode ZD2, and transistor T4; and
timing capacitor C4 through zener diode
ZD3 and transistor T5 only. The indi-

vidual timing capacitors are chosen in
such a way that the time taken to dis-
charge capacitor C2 below 4.7 volts is 6
seconds, 3 seconds for C3, and 1.5 sec-
onds for C4.
Thus while activating tactile switches
S1 through S3 sequentially, transistor T3
will be in conduction for 6 seconds, tran-
sistor T4 for 3 seconds, and transistor T5
for 1.5 seconds.
The positive voltage from the emitter
of transistor T2 is extended to tactile
switch S4 only for 1.5 seconds. Thus one
has to activate S4 tactile switch within
1.5 seconds to energise relay RL1. The
minimum time required to keep switch
S4 depressed is around 1 second.
For sequential switching transistors
T3 through T5, the minimum time for
which the corresponding switches (S1
through S3) are to be kept depressed is
0.75 seconds to 1.25 seconds. If one oper-
ates these switches for less than 0.75 sec-
CIRCUIT IDEAS
onds, timing capacitors C2 through C4
may not get charged sufficiently. As a con-
sequence, these capacitors will discharge
earlier and any one of transistors T3
through T5 may fail to conduct before ac-
tivating tactile switch S4. Thus sequen-
tial switching of the three transistors will
not be achieved and hence it will not be
possible to energise relay RL1 in such a
situation.
A similar situation arises if one keeps
each of the mentioned tactile switches de-
pressed for more than 1.5 seconds. When
the total time taken to activate switches
S1 through S4 is greater than six sec-
onds, transistor T3 stops conducting due
to time lapse. Sequential switching is thus
not achieved and it is not possible to
energise relay RL1.
The latch-up relay circuit is built
around transistors T6 through T8, zener
diode ZD4, and capacitor C5.
In idle state, with relay RL1 in de-
ELECTRONICS FOR YOU ❚  APRIL 2001
energised condition, capacitor C5 is in dis-
charged condition and zener diode ZD4
and transistors T7, T8, and T6 in non-
conduction state.
However, on correct operation of se-
quential switches S1 through S4, capaci-
tor C5 is charged through resistor R9 and
the voltage across it rises above 4.7 volts.
Now zener diode ZD4 as well as transis-
tors T7, T8, and T6 start conducting and
relay RL1 is energised. Due to conduc-
tion of transistor T6, capacitor C5 remains
in charged condition and the relay is in
continuously energised condition.
Now if you activate reset switch S5
momentarily, capacitor C5 is immediately
discharged through resistor R8 and the
voltage across it falls below 4.7 volts. Thus
zener diode ZD4 and transistors T7, T8,
and T6 stop conducting again and relay
RL1 de-energises.

STABLE 455KHz BFO
FOR SSB RECEPTION
D. PRABAHARAN
M
ost Indian amateur radio op-
erators prefer to operate on
SSB (single sideband) and CW
because these carry the signal over a long
distance for a given transmitter power.
Broadcast receivers are not meant to di-
CIRCUIT IDEAS
MAR
IL KU
SUN
rectly receive Morse code transmission on
SSB and CW. Short-wave listeners require
some arrangement to receive the same.
One such arrangement comprises a simple
IF BFO (beat frequency oscillator), which
is an RF oscillator of conventional type.
The output of BFO is heterodyned
to beat with another frequency to
obtain a resultant frequency (dif-
ference of the two frequencies) ly-
ing in the audio range (about 1
kHz).
BFO can be used to get an au-
dio note from CW reception and
also to resolve SSB signals. An SSB
signal is transmitted without car-
rier signal. In ordinary receivers,
it does not produce speech with suf-
ficient clarity. When BFO signal is
heterodyned with SSB signal, this
ELECTRONICS FOR YOU ❚  APRIL 2001
RF acts like a carrier and the signal is
well resolved.
The BFO circuit comprises transistors
T1 and T2, which are connected in a
straightforward two-stage, direct-coupled,
common-emitter configuration. The input
and output are in phase and positive feed-
back between the two is provided by ce-
ramic filter CF1. A significant amount of
feedback is provided only at the operat-
ing frequency of the filter, which is 455
kHz. So the circuit oscillates at this fre-
quency. The ceramic filter gives good fre-
quency stability and requires no adjust-
ment in order to produce the correct fre-
quency. This BFO is meant for single-
sideband reception only.
There is no need to connect BFO to
receiver. Tune your BC receiver to any
SSB signal, and then on keeping BFO just
close to it, you may notice some hissing
noise in your receiver. Match BFO fre-
quency to your receiver’s IF, which may
be between 452 and 460 kHz, until you
get clear sound. If the BFO signal is too
strong, increase the distance between
BFO and receiver.
 CIRCUIT IDEAS

AUTO SHUT-OFF FOR CASSETTE tween the noise and the signal. Resistor
R4 offers feedback resistance to control
the gain of the opamp. By increasing or

PLAYERS AND AMPLIFIERS

decreasing the value of resistor R4, the
MAR gain can be increased or decreased, re-
IL KU
SUN spectively. The preset time delay of timer
NE555 (which is about one minute) can
ARTHUR LOUIS be increased by increasing the value
of C4.

H
ere are two simple, low-cost cir- interrupt the power supply. Initial energisation of relay RL2 and
cuits that can be used to shut The other circuit, shown in Fig. 2, charging of capacitor C4 take place on
off the mains supply to any au- functions on the basis of the signal re- depression of switch S3 in the same man-
dio or video equipment (such as tape re- ceived from preamp of the appliance used. ner as charging of capacitor C1 (refer Fig.
corder, CD player, and amplifier). These In this circuit, opamp µA741 is wired in 1) on depression of switch S1. As a re-
circuits are helpful to those in the habit inverting opamp configuration. It ampli- sult, pins 2 and 6 of NE555 go high and
of falling asleep with their music system fies the signal received from the preamp. the output of timer goes low to switch off
on. Timer NE555 is used to provide the nec- mains supply from the relay to step-down
The circuits will also protect the equip- essary time delay of about one minute. transformer X2 of the appliance. Bleeder
ment from getting damaged due to high- Preset VR1 is used to control the sen- resistor R6 is used to discharge capacitor
voltage spikes whenever there is a re- sitivity of the circuit to differentiate be- C4. Now if signals are received from the
sumption of power after a break. This is
possible because the equipment will get
switched off automatically under such con-
ditions but will not get switched on auto-
matically on resumption of mains supply.
The circuit in Fig. 1 can be used to
shut off any cassette player that has a
reliable auto-stop mechanism. Whenever
switch S1 is pressed momentarily, it ex-
tends the supply to the step-down trans-
former of the tape recorder and charges
capacitor C1 through diode D1. This, in
turn, makes transistor T1 conduct and
energise relay RL1 to provide a parallel
path to switch S1, so that supply to the
step-down transformer continues even
when switch S1 is released.
When any button on the cassette
player is pressed, the capacitor charges
through diode D2. This ensures conduc-
tion of transistor T1 and thus the conti-
nuity of operation of cassette player. How-
ever, whenever the auto-stop mechanism
functions at the end of a tape, the leaf
switch gets opened. This cuts the charg-
ing path for the capacitor and it starts
discharging slowly. After about one
minute, the relay opens and interrupts
main power to the transformer. The time
delay can be increased by increasing the
value of capacitor C1.
If the appliance used is a two-in-one
type (e.g. cassette player-cum-radio), just
connect another diode in parallel with di-
odes D1 and D2 to provide an additional
path for charging capacitor C1 via the
tape-to-radio changeover switch, so that
when radio is played the relay does not

ELECTRONICS FOR YOU ❚  APRIL 2001


preamplifier, these are amplified by 741
and fed to the base of transistor T2, which
keeps capacitor C4 charged through re-
sistor R5. When there is no signal, T2
will not conduct and the capacitor slowly
discharges through R6. The output of 555
goes high to switch off the relay and thus
CIRCUIT IDEAS
the mains supply to transformer X2.
Switch S2 can be depressed momentarily
if the device needs to be manually
switched off.
Note. The 12V supply should be pro-
vided to the circuit from the equipment’s
power supply. Opamp 741 should be
ELECTRONICS FOR YOU ❚  APRIL 2001
driven from the preamplifier of the gad-
get used, and not from its power ampli-
fier output. Switches S1 and S2 are 2-
pole push-to-on switches. These can also
be fabricated from 2-pole on-off switches,
which are widely used in cassette play-
ers, by removing the latch pin from them.

HOUSE SECURITY SYSTEM
MALAY BANERJEE
H
ere is a low-cost, invisible laser
circuit to protect your house
from thieves or trespassers. A
laser pointer torch, which is easily avail-
able in the market, can be used to oper-
ate this device.
The block diagram of the unit shown
in Fig. 1 depicts the overall arrangement
for providing security to a house. A laser
torch powered by 3V power-supply is used
CIRCUIT IDEAS
IL KU
MAR nected at the output.
SUN The receiver unit comprises two iden-
tical step-down transformers (X1 and X2),
two 6V relays (RL1 and RL2), an LDR, a
transistor, and a few other passive com-
for generating a laser beam.
A combination of plain mir-
rors M1 through M6 is used
to direct the laser beam
around the house to form a
net. The laser beam is di-
rected to finally fall on an
LDR that forms part of the
receiver unit as shown in Fig.
2. Any interruption of the
beam by a thief/ ponents. When switches S1 and S2 are
trespasser will re- activated, transformer X1, followed by a
sult into full-wave rectifier and smoothing capaci-
energisation of tor C1, drives relay RL1 through the la-
the alarm. The ser switch.
3V power-supply The laser beam should be aimed con-
circuit is a con- tinuously on LDR. As long as the laser
ventional full- beam falls on LDR, transistor T1 remains
wave rectifier-fil- forward biased and relay RL1 is thus in
ter circuit. Any energised condition. When a person
alarm unit that crosses the line of laser beam, relay RL1
operates on 230V turns off and transformer X2 gets
AC can be con- energised to provide a parallel path across
N/C contact and the pole of relay RL1.
In this condition, the laser beam will have
no effect on LDR and the alarm will con-
tinue to operate as long as switch S2 is
on.
When the torch is switched on, the
pointed laser beam is reflected from a defi-
nite point/place on the periphery of the
house. Making use of a set of properly
oriented mirrors one can form an invis-
ible net of laser rays as shown in the
block diagram. The final ray should fall
on LDR of the circuit.
Note. LDR should be kept in a long
pipe to protect it from other sources of
light, and its total distance from the
source may be kept limited to 500 metres.
The total cost of the circuit, including the
laser torch, is Rs 400 or less.
ELECTRONICS FOR YOU ❚  APRIL 2001
 CIRCUIT IDEAS

SIMPLE
WATER-LEVEL
INDICATOR-
CUM-ALARM
PRADEEP G.

EDI
DWIV
S.C.

T
his water-level indicator-cum-
alarm circuit is configured around
the well-known CMOS input-com-
patible, 7-channel IC ULN2004
Darlington array.
As the water level rises in the tank,
it comes in contact with probes P1 through
P7 and thereby makes pins 7 through 1
high, sequentially. As a result, the corre-
sponding output pins 10 through 16 go
low one after the other, and LED1
through LED7 light up in that order. final probe P7, it results in sounding of 16 along with LED7.
When water comes in contact with the the piezo-buzzer connected to output pin

ELECTRONICS FOR YOU ❚  APRIL 2001

Construction

2001
 CONSTRUCTION

ACCESS-CONTROL SYSTEM Data latches. There are six data

latches formed from three CD4508 ICs
(IC2 through IC4). Each CD4508 contains
NA
ANJA two completely independent 4-bit data
RUP
latches having a common power supply.
BHASKAR BANERJEE The 6-digit code is stored in these latches.
The 4-bit data bus originating from
the output of IC1 is connected to data

T
he easy-to-construct access control DIP switch. input pins of all the six latches in paral-
(code lock) circuit presented here If any one or more of the six consecu- lel. For example, pin 17 (QA) of IC1 is
incorporates the following unique tive keyboard-entered digits do not con- connected to the corresponding pins 4 and
features: form to the predetermined code, an alarm 16 of all the latches as the LSB of 4-bit
(a) Many people can use the same sys- generator sounds the alarm to indicate binary output from IC1. Initially, pin 3 of
tem with their own unique 6-digit code. wrong code. If the result of final compari-
PARTS LIST
(b) A single-digit system code has been son of all the six digits is correct, a mono
included, which is common to all users of multivibrator, serving as lock driver for Semiconductors:
IC1 - 74C922 16-key encoder
the system. It can be easily changed with opening/closing a lock, gets activated for IC2-IC4 - CD4508 dual 4-bit latch
the help of DIP switches. a fixed preset duration. IC5 - CD4017 decade counter
The detailed description of individual IC6 - 27C32 EPROM
units, as shown in Fig. 2, is as follows: IC7-IC9 - CD4063 4-bit magnitude
Description Keyboard and keyboard encoder.
comparator
IC10 - CD4528 dual retriggerable
The block diagram of the system shown The keyboard consists of 16 push-to-on monostable
in Fig. 1 provides an overall view of its type keys in a 4x4 matrix format. It can IC11 - NE555 timer
composition and working. A 16-digit key- be made using data switches or one can IC12 - CD4069 Hex inverter
pad is used for sequentially entering six use membrane-type keyboard at some ex- T1-T4 - BC547 npn transistor
T5 - SL100 npn transistor
Hex numbers, which are decoded by the tra cost. The keys should be numbered in T6 - 2P4M SCR
keyboard encoder into their equivalent bi- Hex as shown in the figure. D1, D2, D4 - 1N4148 switching diode
nary numbers and stored in separate data The encoder is built around 74C922 D3 - 1N4007 rectifier diode
latches in binary form. (IC1), which is a 16-key keyboard encoder. LED1-LED3 - Red LED
LED4 - Green LED
The first three Hex numbers are used It generates a 4-bit binary number corre-
Resistors (¼-watt ±5% carbon, unless stated
as an address for an EPROM, which stores sponding to the key pressed; for example,
otherwise)
a predetermined code at prefixed addresses shorting pin 1 (R1) with pin 11 (C1) gen- R1, R3, R4,
allocated to separate users or used for erates the binary equivalent of digit ‘0’. R15, - 10-kilo-ohm
separate purposes. The code data output Whenever a key is pressed, the signal R2, R5, R8,
from EPROM (one byte/two nibbles) at a generated by this encoder IC is available R21, R22 - 4.7-kilo-ohm
R6 - 18-kilo-ohm
specified address is compared with the as logic ‘high’ output at pin 12 and is R7 - 10-mega-ohm
next two keyboard entries in two 4-bit used to activate a piezo-buzzer (PZ1) via R9 - 2.2-mega-ohm
comparators that are cascaded together. transistor T1 (BC547). The continuous R10, R11,
The resultant outputs of these two tone of PZ1 indicates that a key is pressed. R17-R20 - 1-kilo-ohm
R12-R14 - 470-ohm
comparators are connected to the next The key-pressed signal is also used to
R16 - 47-kilo-ohm
comparator stage, in which the last key- store data in the latches. R23 - 47-ohm
board digit (i.e. sixth Hex digit) is com- The output from pin 12 is connected Capacitors:
pared with the system code selected by to pin 13 of IC5 (CD4017 counter) for C1, C7, C8,
clocking at its C12 - 0.1µF ceramic disc
trailing edge. C2 - 2.2µF, 25V electrolytic
C3, C5, C6,
On each clock-
C9, C10 - 22µF, 25V electrolytic
ing, counter IC5 C4, C13 - 47µF, 25V electrolytic
advances by one C11 - 470µF, 25V electrolytic
count and Miscellaneous:
thereby stores S1 - Push-to-on switch
data in separate S2 - Push-to-off switch
- 4x4 keyboard matrix
data latches one
PZ1 - Continuous tone-type piezo-
after the other. buzzer
IC1 also holds RL1 - 9V, 200-ohm, 1 C/O relay
the last number S3 - 4-way DIP switch
at its output - Regulated 5V power supply
etc
Fig. 1: Block diagram of the access-control system pins.

ELECTRONICS FOR YOU ❚  APRIL 2001

 CONSTRUCTION

IC5 provides
a high output
to ‘clear’ and
‘store’ pins 1
and 2 of IC2A,
thereby clear-
ing its 4-bit
register.
When a
key is
pressed, the
equivalent bi-
nary code is
present at
data input
pins of all the
latches. On
releasing the
key, pin 12 of
IC1 changes
its state from
‘high’ to ‘low’,
thereby gen-
erating the
required clock
pulse for IC5.
This clocking
makes pins 3
and 2 of IC5
low and high,
respectively,
causing the
binary data
corresponding
to the first
Hex digit key-
board entry to
be stored and
available at
the output of
IC2A.
Similarly,
when the sec-
Fig. 2: Schematic diagram of access-control system

ond key is
pressed, new
data is stored
in IC2B with-
out affecting
the previously
stored data in
IC2A. The
outputs from
first three
data latches
are connected
to address
pins of
E P R O M
27C32 (IC6).
The outputs

ELECTRONICS FOR YOU ❚  APRIL 2001


Fig. 3: Actual-size, single-sided PCB layout for access-control system
from fourth and fifth data latches are con-
nected to two 4-bit magnitude compara-
tors IC7 and IC8 (CD4063), and the out-
put from sixth data latch is connected to
a similar 4-bit magnitude comparator IC9
for further processing.
The memory. All 8-bit codes, except
the 4-bit system code, are stored at dif-
ferent locations (addresses) in the EPROM
(IC6). Out of the six Hex digits, first five
digits are used as personalised code, and
out of these five digits, the first three are
used to form an address for EPROM.
The leftmost digit of the code is the
MSD (most significant digit) and the third
digit from left is the LSD (least signifi-
CONSTRUCTION
cant digit) of the 12-bit wide address for
IC6. The fourth and fifth digits from left
are to be the same as the data stored in
IC6 (beforehand) at that particular ad-
dress. Thus, when a code is entered via
the keyboard, the fourth and fifth digits
are compared with the data stored at the
address formed by the first three digits.
(The EPROM can be programmed with
the help of ‘Manual EPROM Programmer’,
and may be replaced by an EEPROM for
better reliability.)
Code comparator. There are three
4-bit comparators (IC7 through IC9) used
in the circuit, which are cascaded together
to form a 12-bit comparator. Comparators
ELECTRONICS FOR YOU ❚  APRIL 2001

Fig. 4: Component layout for the PCB
IC7 and IC8 compare the 8-bit data out-
put of EPROM with the corresponding
fourth and fifth digits entered via the key-
board and stored in latches IC3B and IC4A.
While IC7 compares the upper 4-bit
output of IC6 with the contents of IC3B
(i.e. the fourth digit from left), IC8 com-
pares the lower 4-bit output of IC6 with
the contents of IC4A (i.e. the fifth digit
from left). Similarly, IC9 compares the
last digit (i.e. the contents of IC4B) with
the code entered/formed by 4-way DIP
switch S3 (marked A through D), which
is referred to here as the system code.
This system code digit can be changed
from time to time.
CONSTRUCTION
The result of the comparison by the
three comparators is finally available from
IC9. If the entered code matches with the
stored data, pin 6 of IC9 goes high, indi-
cating a correct code. Otherwise, either
of pins 5 and 7 goes high depending upon
the magnitude of the data. Pins 5 and 7
are connected together via diodes D1 and
D2 and used as the trigger for alarm cir-
cuit. The outputs from IC9 are available
only after entering the last digit.
Alarm generator. The alarm genera-
tor is built around a 555 timer (IC11).
The logic ‘high’ output from pin 5 or pin 7
of IC9 triggers the SCR and applies Vcc
supply to IC 555 to make it oscillate. The
ELECTRONICS FOR YOU ❚  APRIL 2001
output from pin 3 of IC11 is used to drive
transistor T2 (BC547) to generate a long-
duration alarm tone from PZ1.
A common buzzer is used for key-press
audio indicator and alarm generator to
keep the cost low. The output from pin 3
of timer also drives LED2, which flashes
at the output frequency of the astable os-
cillator.
MMV and lock driver. When a valid
code is entered, pin 6 of IC9 becomes high
and triggers monostable multivibrator
CD4528 (IC10) via transistor T3. On trig-
gering, pin 6 of IC10 becomes high and
remains in that state for a predetermined
time period. The output at pin 6 of IC10
drives transistor T5 (SL100) to operate
relay RL1. When the system is locked,
red LED1 glows, and when it is unlocked,
green LED4 glows.
The other half of IC10 is used to keep
the keyboard activated for a predeter-
mined time. The keyboard is activated by
pressing switch S1. This feature improves
the security of the system.
Construction
Data input/output pins are to be connected
with utmost care because improper con-
nection will force the system to work un-
predictably. Also, care should be taken
while using IC1, as it is quite costly. The
points marked Vcc should be connected
to the power supply directly.
The system can be built on a general-
purpose PCB or a veroboard. A single-
sided PCB layout for the circuit is, how-
ever, shown in Fig. 3, with its component
layout shown in Fig. 4.
Operation
Initially, when IC1 is disabled by IC10,
no code can be entered. To activate the
keyboard, press switch S1 momentarily.
This will activate the keyboard for
a predetermined time. The code should
be entered within this time. Using the
4-way DIP switch S3, the system code
can be changed at any time for extra se-
curity.
If wrong code is entered, the buzzer
sounds alarm and the red LED starts
flashing. In this case, you can reset the
circuit by a momentary depression of
switch S2. It is to be noted that no dis-
play unit is used, to keep the code secret.
But if you still prefer to have one, the
same could be included. ❏

TELEPHONE LINE-INTERFACED
GENERIC SWITCHING SYSTEM
PART I
AJAY SUBRAMANIAN AND NAYANTARA BHATNAGAR
Q uite a few projects using DTMF-
to-BCD decoder ASIC MT 8870/
KT 3170 have appeared in EFY
during the past few years. The project
presented here also uses the same ASIC,
but it is used here as part of a circuit in
which a fairly advanced switching logic
with adequate foolproofing and authenti-
cation is implemented. The major features
of this circuit are:
• Programmable password protection
over a public network
• Foolproof mechanisms for events
such as time-out delays, incorrect pass-
word, and power-on initialisation
• Expandable design
The primary objective of this circuit
is to make a fairly low-cost device for con-
trolling up to a hundred household
switches remotely over any public/private
telephone network.
Description
The block diagram of the system is shown
in Fig. 1. It consists of the following three
units:
1. The interface and control unit
2. The authentication unit
3. The main device selection and
switching circuit
Fig. 1: Block diagram of telephone line-interfaced generic switching system
C O N S T R U C T I O N
DWIV
EDI
S.C.
The interface and control unit pro-
vides control signals and BCD data to the
other two units. It handles interfacing
with the telephone line and also gener-
ates control signals for hanging up (HUP)
and a universal reset pulse, which is used
by the authentication circuit for its op-
eration. Its design may be altered to
achieve connectivity to another network,
which is capable of providing certain con-
trol and data signal sequences.
The authentication unit stores four
presettable digits of code data and
compares the same against the 4-digit
DTMF code sent via the telephone lines
before the time-out occurs. If the 4-digit
code is found valid, the authentication
unit issues an authorisation signal to
the main device selection and switching
unit. However if an incorrect password
is entered, the device terminates the
call by returning to the off-hook condi-
tion.
The fifth DTMF digit determines the
address of the group to be selected, while
the sixth digit determines the device num-
ber that is to be selected within that
group. The selected device can be switched
on or switched off by a momentary de-
pression of the telephone keypad switches
marked * (code1011 binary) and # (code
ELECTRONICS FOR YOU ❚  APRIL 2001
1100 binary), respectively. Thus you can
select any one of the hundred devices,
divided into ten groups, to be switched
on/off, as desired—one at a time.
The interface and control unit
(Fig. 2). This unit performs the following
functions:
• Detects an incoming call. Counts up
to a programmable number of rings and
then simulates handset off-cradle condi-
tion.
• Once off-hook, it must decode DTMF
signals on the telephone line within a fixed
time and generate appropriate BCD
data and StD pulse for indicating a valid
data condition. The positive edge of this
StD pulse is used for subsequent opera-
tions.
• Generates a universal Reset signal
that includes a time-out and a power-on-
reset. This Reset signal is an active low
pulse of programmable duration.
• Generates a hang-up (HUP) signal
on expiry of the time-out and uses this
signal internally to take the device off-
line.
When a call arrives, a 75-80V AC ring
signal is available on the lines. This ring
signal is coupled to optocoupler Opto-1
(MCT2E) via DC blocking capacitor C1
and current-limiting resistor R1. LED1
serves as a ring indicator and as an anti-
parallel diode to the in-built LED of the
optocoupler for working with AC ring sig-
nal. The output of optocoupler triggers
timer IC1, which is configured as a
monostable retriggerable flip-flop to pro-
vide a pulse output to be used as a clock
for decade counter IC2 (CD4017) with de-
coded outputs.
The pulse-width of monostable should
be slightly greater than 0.6 second to en-
sure that the pulse does not terminate
during the 0.2-second pause between a
pair of ring signals of 0.4-second dura-
 C O N S T R U C T I O N
Fig. 2: Circuit diagram of the interface and control unit

the call has not been an-

swered yet (local tele-
phone handset still on
cradle), the counter (IC2)
is frozen and ‘D’ flip-flop
(IC3A) is set. This acti-
vates relay RL1 that
places a 220-ohm load
across the lines to simu-
late handset off-cradle
condition and also en-
ables CM8870 (IC4) by
applying a ‘low’ at its in-
hibit (active high) pin 5.
This causes the ring sig-
nal, in turn, to be taken
off the telephone lines
(by telephone exchange)
and establish a connec-
tion (analogous to the
maturity of a call). The
circuit is now ready to
receive signals from the
remote-end telephone.
In case the call is an-
swered from the local
telephone before the pre-
set count of IC2 is
reached, the ring ceases
as the local telephone is
in off-hook condition.
Since there is no other
way of re-triggering IC5,
a time-out eventually oc-
curs and the device
reinitialises all units au-
tomatically. The device is
also protected against ac-
tivation by dialing from
a parallel phone instru-
ment, since the ring sig-
nal is necessary to power
up the ASIC MT8870 (af-
ter a pre-programmed
number of rings).
CM8870 (IC4) gener-
ates an StD pulse when-
ever fresh data is
latched onto its outputs.
This signal is used as a
tion. Thus the monostable produces one The first pulse from IC1 also triggers ‘data valid’ gate wherever appropriate.
pulse for each ring (in fact, a pair), which the first stage of monostable multivibrator Also, when a key is pressed, an ESt (Early
clocks CD4017 counter. 74123 (IC5), which causes the Reset out- steering) pulse is generated at its pin 16,
IC2 will freeze after counting a pre- put to go high. As a result, CD4017 (IC2) which lasts till the key is pressed. This
programmed number of rings. This num- is enabled (which was otherwise reset, ESt pulse is used for clocking IC12B in
ber is determined by its output pin which when no ring signal was present). Also, the authentication and control unit and
is tied to its pin 13. In Fig. 2 pin 9 (O8 the authentication circuit is enabled to retriggering monostable multivibrator
output) is shorted to pin 13. Thus count receive BCD data and control signals, as 74123 (IC5), extending the duration of
of IC2 is frozen at the beginning of the and when generated by CM8870 (IC4). Reset pulse. This ensures that the cir-
eighth ring. If the preset count is reached and cuit will operate as long as the user

ELECTRONICS FOR YOU ❚  APRIL 2001


presses keys within preset time intervals,
or else a time-out is decreed and the de-
vice is reset.
The resetting process includes hang-
up (HUP) state, clearing the authentica-
tion circuit status, and consequently
deactivating the main switching circuit,
C O N S T R U C T I O N
thus restoring the device to its initial
state. (The flip-flops, which control de-
vices in the main device selection and
switching unit, are allowed to retain their
states.)
If the time-out period expires, the Re-
set pulse falls and the falling edge is
ELECTRONICS FOR YOU ❚  APRIL 2001
used to trigger the sec-
ond stage of monostable
multivibrator 74123
(IC5). The complemented
output 2Q of the second
stage of IC5 is a HUP
(hang-up) signal that
clears relay driver flip-
flop 74LS74 (IC3A), thus
causing the device to
hang up, and inhibit IC4.
It resets CD4017 (IC2)
counter that counts the
number of rings. Also, as
a Reset pulse goes low, it
resets the authorisation
circuit.
The additional cir-
cuitry around the input of
IC4 protects inbuilt op-
amp input terminals
within the chip.
The power-on-reset
circuit comprises resistor
R5 and capacitor C10. It
resets the device when
power to the circuit is
switched on. Since it is
low for some time after
power is switched on, it
resets the flip-flop (IC3A)
and decade counter
CD4017 (IC2). Fig. 4
shows the relative timing
waveforms pertaining to
this unit.
LED2 through LED5
are used to show the
Fig. 3: The authentication unit circuit diagram
BCD output for the
DTMF code received
over the telephone lines
(decoded after relay RL1
has energised).
The authentication
unit (Fig. 3). This cir-
cuit receives BCD data
and StD control signal
initially. It outputs
authorisation (Auth) sig-
nal only when the correct
security code has been
entered. Control pulses
can reach the ‘main
switching unit’ only when this signal is
low (implying that authentication of the
four digit code sent over the telephone
lines has been verified).
Note that when a wrong code is re-
ceived, IC9A clocks IC9B and a low is
latched by IC9B. As a result the Q2 out-

Fig. 4: Signal waveforms of the interface and control unit
Fig. 5: Method of programming code using
DIP switches
put of IC9B goes high and saturates tran-
sistor T2 in the interface and control unit
and thereby shunts capacitor C10 to
ground, thus simulating a power-on-re-
set condition. As a consequence CLR sig-
nal (at output of IC6A) is activated and
the line interface circuit is initialised.
Also, since the monoshot IC5 is cleared,
Reset goes low (active) and resets the
authentication unit also. When the Au-
thentication unit is initialised, IC9A and
9B are set, which causes Q2 output of
IC9 to be reset, and thus transistor T2 is
cut off again. Capacitor C10 now charges
through resistor R5 as it did when the
circuit was initially switched on.
The Reset signal is initially low. As a
result, this circuit is in its initialised state,
wherein IC13 (CD4017) is reset and ICs
9A and 9B (7474) are set (i.e. their Q
outputs are high and Q outputs are low).
Also, IC12A has its CLR pin low and it
is in reset state with its Q pin low. As
stated earlier, the Auth signal is initially
high.
The password consisting of four 4-bit
words is applied at the input pins D0_0
through D0_3 to D3_0 through D3_3 of
74LS244 ICs 15 and 14 respectively as
shown in Fig. 3. These words may be pro-
grammed using thumbwheel switches or
arrays of DIP switches with pull-down re-
sistors as shown in Fig. 5.
C O N S T R U C T I O N
As soon as the device establishes a
call (i.e. relay RL1 energises after a
preprogrammed number of rings), the au-
thentication unit (and not the main de-
vice selection and control unit) is acti-
vated due to a high Reset pulse that is
generated as soon as the ring arrives and
also on every pressing of a key due to
(ESt) signal from IC4 via OR gate (IC7A),
which triggers IC5.
Now the caller is expected to enter
the 4-digit password sequence from the
remote telephone set in DTMF mode. Ini-
tially, only the first word (nibble) of the
array of tri-state buffer drivers (ICs
74LS244) is enabled by O0 output of IC13
(CD4017). As a result, the first 4-bit
programmed word is applied to the ‘P’
inputs of 4-bit comparator IC 74LS85
(IC8). LED7 through LED10 indicate the
preset data present at ‘P’ inputs of the
comparator. The other 4-bit ‘Q’ inputs
for comparison are obtained from the
BCD output decoded by IC4 upon press-
ing a DTMF telephone key at the remote
end. This comparator result is available
at pin 6 of IC8 before the arrival of StD
pulse.
On the arrival of StD pulse, the out-
put of the comparator is latched into ‘D’
flip-flop (IC9A). Initially, both flip-flops
(IC9A and 9B) are set, as explained ear-
lier. So the ‘CLK’ input of the second flip-
flop (IC9B) is low.
If at any instant, a low is latched into
the first flip-flop IC9A (as a result of a
failed match between the preset code and
the code entered via the remote telephone
set), the second flip-flop (IC9B) is clocked,
and it latches a low at its Q output. This
resets decade counter IC13 via inverter
IC11F. The Q2 output of IC9B is nor-
mally low. But when a wrong password is
entered, this output goes high. As a re-
sult, transistor T2 (2N2222) of the inter-
face and control unit, grounds the power-
on-reset capacitor C10, as stated earlier.
Thus the unauthorized call is terminated
when the CLR signal (from the output of
IC6A) is activated. As a result, IC2 and
IC3A are reset (asynchronously) and the
ELECTRONICS FOR YOU ❚  APRIL 2001
off cradle simulation circuit is deactivated.
Also since the Reset signal is low, all other
units are initialised. This feature ensures
that a denial-of-service attack (wherein
unauthorised agents engage the system
and thus prevent authorised users from
using it) is discouraged.
However, if correct codes are entered,
each time when a StD pulse arrives, it
clocks CD4017 (IC13) counter so that the
next word is applied at the input of the
comparator. The result of the current com-
parison (high) is latched into the first ‘D’
flip-flop (IC9A).
When the user presses all four keys
in the correct sequence, the first flip-flop
always latches a high and the second
flip-flop is never clocked. At the end of
the sequence, when the last digit is com-
pared and the result is latched, O4 out-
put of CD4017 (IC13) goes high, and as
a result, IC12A is clocked and latches
a ‘high’ at its Q output and the input to
inverter gate IC11E and ‘D2’ pin of flip-
flop IC12B goes high. Simultaneously, sig-
nal at the output of gate IC11E goes low.
This low signal at pin 12 of IC10D AND
gate disables the gate from accepting any
further StD pulses. So the authentica-
tion unit is bypassed and subsequent BCD
data and StD pulses are transmitted to
the main switching unit. The ESt pulse
associated with fifth BCD data, latches
the high signal at D2 input of IC12 to its
Q2 output, while its Q2 output (Auth)
goes low to activate the main device se-
lection and switching unit at the start of
fifth code.
When the Reset signal goes high,
the output of inverter gate IC11F goes
low. This enables IC13 (CD4017) again by
taking its MR pin low. At the same time,
the high ‘Preset’ signal at both the flip-
flops (IC9A and IC9B) keeps them enabled.
When the code is not entered within
preset period, the Reset signal goes low
on expiry of the time-out period, the cir-
cuit again goes back to its initial state by
taking the preset pin on the flip-flops
(IC9A and 9B) low and MR pin of CD4017
(IC13) high. Simultaneously, IC12A is
cleared (its Q output goes low). As a re-
sult, Auth output goes high and the
main device selection and switching
circuit is initialised and deactivated.
Since the initialised state is maintained
as long as the Reset signal is low, any
possibility of noise triggering is elimi-
nated.
To be continued….
May

2001
Circuit Ideas

2001
 CIRCUIT IDEAS

PRECISION INDUCTANCE AND the capacitance value is given by the re-

lationship C=Tx10–3 while the inductor
value is given by the relationship

CAPACITANCE METER MAR

L=Tx103. The time period (1/frequency)
of timer 555 (IC2) is adjusted for 1 ms
and 1 µs in ‘b1’ and ‘b2’ positions, respec-
IL KU
SUN tively, of the range switch. The values of
capacitors and inductors covered in each
P. THANGAVEL
range, together with displayed values, are
shown in the table.
From the table it is obvious that this

T
his circuit for measurement of in- When switch S1 is pushed, the capacitor’s circuit can measure capacitance from 1
ductance and capacitance can be voltage begins to grow (or the inductor’s nF to 9,999 µF and inductance from 1
used to test whether the values voltage begins to drop). Simultaneously, mH to 9999 H. While presets VR1 and
of inductors and capacitors quoted by the the output of timer 555 IC, which is wired VR2 are to be adjusted for the in-circuit
manufacturer are correct. as an astable multivibrator, is passed value of 1.717 kilo-ohm each, the in-cir-
The principle used in the circuit is through NOR gates N1 and N2 and ap- cuit value of preset VR3 is close to 4.7
based on the transient voltages produced plied to the counter circuit. kilo-ohm. If a regulated +5V is not used,
across inductors and capacitors connected When the time constant (one CxR or the measurement of capacitance and in-
as series R-L and R-C networks, respec- one L/R, as the case may be) reaches, ductance will be imprecise.
tively, across a constant voltage source. gate N2 is inhibited as its pin 2 goes high Given below are some important
The time constant for R-C and R-L net- and the counter circuit freezes. Mode points to be taken care of:
works is given by the relationships t=RxC switch S2 is to be kept in position ‘a1’ for 1. The position of mode-select switch
and L/R, respectively, where resistance R capacitance measurement and in position S2 and range-select switch S3 should be
is in ohms, capacitance C in Farads, in- ‘a2’ for inductance measurement. changed before switch S1 is pressed.
ductance L in Henries, and time t in sec- As series resistance R1 is 1 kilo-ohm, 2. If the circuit is allowed to function
onds.
The voltage
across capacitor
in R-C network
rises exponen-
tially to 0.632 of
the applied volt-
age and voltage
across inductor in
R-L network de-
grades exponen-
tially to 0.368 of
the applied volt-
age in one RxC
and one L/R time
(referred to as
time constant T
of the combina-
tion), respec-
tively.
When the in-
ductor/capacitor
under test is con-
nected across ter-
minals A and B
shown in the cir-
cuit, it is dis-
charged through
the normally-
closed contacts of
two-way push-to-
on/off switch S1.

ELECTRONICS FOR YOU ❚  MAY 2001

 CIRCUIT IDEAS

TABLE and when it is be possible to get 1µs period. One may

555 IC Capacitance Inductance Displayed in position a2, therefore use a 2nF capacitor to get a
Time period range range value inductances period of 2 µs and multiply the displayed
C=Tx10– 3 L=Tx103 can be mea- value by 2, in b2 range.)
1 ms When T=1 ms, When T=1 ms, L=1H Capacitance in sured. 5. Use a breadboard for connecting
(Switch S3 in C=1 µF When T=9999 ms, µF and inductance 4. When inductors or capacitors across terminals
position b1) When T= L=9999 H in H range-select A and B.
9999 ms,
C=9999 µF switch S3 is in 6. Using both the ranges for measur-
1 µs When T=1 µs, When T=1 µs, Capacitance in nF position ‘b1’, ing an inductor or capacitor enables one
(Switch S3 in C=1 nF L=1 mH and inductance the output of to obtain the accurate value. For example,
position b2) When T=9999 µs, When T=9999 µs, in mH 555 IC will a 4.7µF capacitor will display only 4 µF
C=9999 nF L=9.999H
=9.999 µF =9999 mH have a time when measured in range b1 , while in b2
period of 1 ms range it will display 4700 nF (or 4.7 µF).
until it displays a constant value, the (frequency = 1 kHz), and when it is in 7. Don’t press switch S1 before insert-
maximum time taken for measurement position ‘b2’, the output of 555 IC will ing the capacitor or the inductor between
will be 10 seconds. have a time period of 1 µs. (EFY lab note. terminals A and B.
3. When mode-select switch S2 is in The guaranteed frequency of NE555 is
position a1, capacitances can be measured, limited to 500 kHz, and hence it may not

ELECTRONICS FOR YOU ❚  MAY 2001


UNDER-/OVER-VOLTAGE BEEP
FOR MANUAL STABILISER
K. UDHAYA KUMARAN
M
anual stabilisers are still popu-
lar because of their simple con-
struction, low cost, and high re-
liability due to the absence of any relays
while covering a wide range of mains AC
voltages compared to that handled by au-
tomatic voltage stabilisers. These are used
mostly in homes and in business centres
for loads such as lighting, TV, and fridge,
and in certain areas where the mains AC
voltage fluctuates between very low (dur-
ing peak hours) and abnormally high (dur-
ing non-peak hours).
Some manual stabilisers available in
the market incorporate the high-voltage
auto-cut-off facility to turn off the load
when the output voltage of manual
stabiliser exceeds a certain preset high
voltage limit. The output voltage may be-
come high due to the rise in AC mains
voltage or due to improper selection by
the rotary switch on manual stabiliser.
One of the major disadvantage of us-
ing a manual stabiliser in areas with a
wide range of voltage fluctuations is that
one has to keep a watch on the manual
stabiliser’s output voltage that is displayed
on a voltmeter and keep changing the
same using its rotary switch. Or else, the
output voltage may reach the preset auto-
cut-off limit to switch off the load without
the user’s knowledge. To turn on the load
again, one has to readjust the stabiliser
voltage using its rotary switch. Such op-
CIRCUIT IDEAS
IL KU
MAR
SUN
eration is very irritating and inconvenient
for the user.
This under-/over-voltage audio alarm
circuit designed as an add-on circuit for
the existing manual stabilisers overcomes
the above problem. Whenever the
stabiliser’s output voltage falls below a
preset low-level voltage or rises above a
preset high-level voltage, it produces dif-
ferent beep sounds for ‘high’ and ‘low’ volt-
age levels—short-duration beeps with
short intervals between successive beeps
for ‘high’ voltage level and slightly longer-
duration beeps with longer interval be-
tween successive beeps for ‘low’ voltage
level. By using these two different types
of beep sounds one can readily readjust
the stabiliser’s AC voltage output with the
help of the rotary switch. There is no need
of frequently checking voltmeter reading.
It is advisable to preset the high-level
voltage 10V to 20V less than the required
high-voltage limit for auto-cut-off opera-
tion. Similarly, for low level one may pre-
set low-level AC voltage 20V to 30V above
minimum operating voltage for a given
load.
The primary winding terminals of
step-down transformer X1 are connected
to the output terminals of the manual
stabiliser. Thus, 9V DC available across
capacitor C1 will vary in accordance with
the voltage available at the output termi-
nals of the manual stabiliser, which is
ELECTRONICS FOR YOU ❚  MAY 2001
used to sense high or low voltage in this
circuit.
Transistor T1 in conjunction with ze-
ner diode ZD1 and preset VR1 is used to
sense and adjust the high-voltage level
for beep indication. Similarly, transistor
T2 along with zener ZD2 and preset VR2
is used to sense and adjust low voltage
level for beep indication.
When the DC voltage across capaci-
tor C1 rises above the preset high-level
voltage or falls below the preset low-level
voltage, the collector of transistor T2 be-
comes high due to non-conduction of tran-
sistor T2, in either case. However, if the
DC voltage sampled across C1 is within
the preset high- and low-level voltage,
transistor T2 conducts and its collector
voltage gets pulled to the ground level.
These changes in the collector voltage of
transistor T2 are used to start or stop
oscillations in the astable multivibrator
circuit that is built around transistors T3
and T4. The collector
of transistor T4 is con-
nected to the base of
buzzer driver transis-
tor T5 through resis-
tor R8. Thus when the
collector voltage of
transistor T4 goes
high, the buzzer
sounds. Preset VR3 is
used to control the
volume of buzzer
sound.
In normal condi-
tion, the DC voltage sampled across ca-
pacitor C1 is within the permissible win-
dow voltage zone. The base of transistor
T3 is pulled low due to conduction of di-
ode D2 and transistor T2. As a result,
capacitor C2 is discharged. The astable
multivibrator stops oscillating and tran-
sistor T4 starts conducting because tran-
sistor T3 is in cut-off state. No beep sound
is heard in the buzzer due to conduction
of transistor T4 and non-conduction of
transistor T5.
When the DC voltage across capaci-
tor C1 goes above or below the window
voltage level, transistor T2 is cut off. Its
collector voltage goes high and diode D2
stops conducting. Thus there is no dis-
charge path for capacitor C2 through di-
ode D2. The astable multivibrator starts

oscillating. The time period for which the
beep is heard and the time interval be-
tween two successive beeps are achieved
with the help of the DC supply voltage,
which is low during low-level voltage sam-
pling and high during high-level voltage
CIRCUIT IDEAS
sampling. The time taken for charging
capacitors C2 and C3 is less when the DC
voltage is high and slightly greater when
the DC voltage is low for astable
multivibrator operation. Thus during low-
level voltage sensing the buzzer beeps for
ELECTRONICS FOR YOU ❚  MAY 2001
longer duration with longer interval be-
tween successive beeps compared to that
during high-voltage level sensing.
This circuit can be added to any ex-
isting stabiliser (automatic or manual) or
UPS to monitor its performance.

ULTRA-SENSITIVE SOLIDSTATE
CLAP SWITCH
PRADEEP G.
H
ere is the circuit of a highly sen-
sitive clap switch that can be
operated from a distance of up
to 10 metres from the microphone.
Signals picked up by the microphone
are amplified by transistors T1, T2, and
CIRCUIT IDEAS
SUN
IL KU
MAR
T3. Diode D1 detects clap signals and the
resulting positive voltage is applied to the
base of transistor T4. The output from
transistor T4 is further amplified by tran-
sistor T5, whose output is used to trigger
a monostable multivibrator wired around
ELECTRONICS FOR YOU ❚  MAY 2001
the 555 timer (IC1).
The output of IC1 is used as a clock
for decade counter 4017 (IC2) that is wired
as a divide-by-two counter. For each suc-
cessive clap, transistor T6 conducts and
cuts off alternately. As a result, for each
clap signal, the lamp is either switched
‘on’ or ‘off’.
Triac 8T44A (or ST044) can drive load
of up to 4-amp rating. The 12V DC for
operation of the circuit is directly derived
from the mains using rectifier diode D2,
current-limiting resistor R16, and 12V ze-
ner ZD1 shunted by filter capacitor C7.

15-STEP DIGITAL POWER SUPPLY
NAVEEN THARIYAN
H
ere is a simple circuit to obtain
variable DC voltage from 1.25V
to 15.19V in reasonably small
steps as shown in the table. The input
voltage may lie anywhere between 20V
and 35V.
The first section of the circuit com-
prises a digital up-down counter built
around IC1— a quad 2-input NAND
schmitt trigger (4093), followed by
IC2— a binary up-down counter (4029).
Two gates of IC 4093 are used to gen-
erate up-down logic using push but-
tons S1 and S2, respectively, while the
other two gates form an oscillator to
provide clock pulses to IC2 (4029). The
frequency of oscillations can be varied
by changing the value of capacitor C1
or preset VR1.
IC2 receives clock pulses from the os-
cillator and produces a sequential binary
output. As long as its pin 5 is low, the
counter continues to count at the rising
edge of each clock pulse, but stops count-
ing as soon as its pin 5 is brought to logic
1.
Logic 1 at pin 10 makes the counter
to count upwards, while logic 0 makes it
count downwards. Therefore the counter
counts up by closing switch S1 and counts
CIRCUIT IDEAS
NA
ANJA
RUP
down by closing switch S2.
The output of counter IC2 is used to
realise a digitally variable resistor. This
section consists of four N/O reed relays
that need just about 5mA current for their
operation. (EFY lab note. The original
circuit containing quad bilateral switch
IC 4066 has been replaced by reed relays
operated by transistorised switches be-
cause of unreliable operation of the
former.) The switching action is performed
using BC548 transistors. External resis-
tors are connected in parallel with the
reed relay contacts. If particular relay con-
tacts are opened by the control input at
the base of a transistor, the correspond-
ELECTRONICS FOR YOU ❚  MAY 2001
ing resistor across the relay contacts gets
connected to the circuit.
The table shows the theoretical out-
put for various digital input combinations.
The measured output is nearly equal to
the theoretically calculated output across
regulator IC3 (LM317). The output volt-
age is governed by the following relation-
ship as long as the input-to-output differ-
ential is greater than or equal to 2.5V:
Vout = 1.25(1+R2'/R1')
Where, R1' = R15 = 270 ohms (fixed)
and R2' = R11 + R12 + R13 + R14
= 220 + 470 + 820 +1500 ohms
= 3,010 ohms (with all relays
energised)
One can use either the binary
weighted LED display as indicated by
LED1 through LED4 in the circuit or a
74LS154 IC in conjunction with LED5
through LED20 to indicate one of the 16
selected voltage steps of Table I. The in-
put for IC4 is to be tapped from points
 CIRCUIT IDEAS

TABLE sets itself, and hence the output at pins

Binary Equivalent LED4 LED3 LED2 LED1
6, 11, 14, and 12 is equivalent to binary
output dec no. R14 (W) R13 (W) R12 (W) R11 (W) R2' (W) Vout (V) zero, i.e. ‘0000’. The corresponding DC
0000 0 Shorted Shorted Shorted Shorted 0 1.25 output of the circuit is minimum (1.25V).
0001 1 Shorted Shorted Shorted 220 220 2.27 As count-up switch S1 is pressed, the
0010 2 Shorted Shorted 470 Shorted 470 3.43 binary count of IC2 increases and the
0011 3 Shorted Shorted 470 220 690 4.44 output starts increasing too. At the high-
0100 4 Shorted 820 Shorted Shorted 820 5.05
0101 5 Shorted 820 Shorted 220 1040 6.06 est count output of 1111, the output volt-
0110 6 Shorted 820 470 Shorted 1290 7.22 age is 15.19V (assuming the in-circuit re-
0111 7 Shorted 820 470 220 1510 8.24 sistance of preset VR2 as zero). Preset
1000 8 1500 Shorted Shorted Shorted 1500 8.19 VR2 can be used for trimming the output
1001 9 1500 Shorted Shorted 220 1720 9.21
1010 10 1500 Shorted 470 Shorted 1970 10.37
voltage as desired. To decrease the out-
1011 11 1500 Shorted 470 220 2190 11.39 put voltage within the range of 1.25V to
1100 12 1500 820 Shorted Shorted 2390 11.99 15.2V, count-down switch S2 is to be de-
1101 13 1500 820 Shorted 220 2540 13.01 pressed.
1110 14 1500 820 470 Shorted 2790 14.17
Notes. 1. When relay contacts across
1111 15 1500 820 470 220 3010 15.19
a particular resistor are opened, the cor-
marked ‘A’ through ‘D’ in the figure. This count value. LEDs at the output of this responding LED glows.
arrangement can be used to replace the IC can be arranged in a circular way along 2. The output voltages are shown as-
LED arrangement at points A, B, C, and side the corresponding voltages. suming the in-circuit resistance of preset
D. This 74LS154 IC is a decoder/ VR2 as zero. Thus when the in-circuit re-
demultiplexer that senses the output of sistance of preset VR2 is not zero, the
IC2 and accordingly activates only one of
Working output voltage will be higher than that
its 16 outputs in accordance with the When the power is switched on, IC2 re- indicated here.

ELECTRONICS FOR YOU ❚  MAY 2001


MICROPHONE FOR
COMPUTER
VYJESH M.V.
B
uying a microphone for a com-
puter is costly. Especially when
there is a need to have two mi-
crophones—one for modem and another
for sound card—or if the present micro-
phone is not working properly and needs
to be replaced, you are likely to feel the
burden of extra cost. Here is a low-cost
microphone circuit that comes within your
budget.
All sound cards and modems have a
CIRCUIT IDEAS
the help of a multimeter, find out the
positive terminal out of the three wires.
EDI
DWIV There exists a potential difference of
S.C.
4V or so between the positive and ground
terminals. The third terminal will obvi-
ously be for the signal input. The positive
terminal is used for biasing the condenser
microphone. After identifying all the ter-
socket for microphone that is in compat- minals, connect them as shown in the ac-
ible with stereo jack pins. The stereo socket companying circuit diagram.
takes condenser microphone as
input and provides the neces-
sary positive voltage for a con-
denser microphone. Before
building the full circuit, con-
nect three wires to the jackpin,
switch on the computer, and
insert the jack pins; into the
socket of the sound card. With
ELECTRONICS FOR YOU ❚  MAY 2001
Construction

2001

PROGRAMMABLE MELODY
GENERATOR - PART I
VYJESH M.V.
A
number of melody generator cir-
cuits based on chips like UM3481,
UM3482, UM34815A, UM66, etc
have appeared in EFY. All these UMC
chips contain preprogrammed masked
ROM and are not field-programmable as
such.
Here is the detailed design of a typi-
cal melody generator circuit using differ-
ent types of memories, including EPROM,
RAM, and ROM (hard-wired).
As soon as the power is switched on
to UMXX series melody generators, a tune
is heard, which stops after a while. When
a switch on the melody generator is
pressed, the second tune is heard. If the
chip is capable of producing twelve tunes,
each successive depression of the switch
results in a new tune being played. After
the twelfth tune has been played, the next
depression of the switch causes the first
tune to repeat, and so on. The circuit pre-
sented here can be programmed exactly
the same way.
Basics of music
Generally, an electronic organ or piano is
played with both hands. Now imagine
playing a 32-key organ with a single
finger. In that case, only one key can
be pressed at a time and hence only one
note can be heard. Considering that the
time taken by the finger to move from
one key to another is very short, the re-
Fig. 1: Block diagram of EPROM-/RAM-based melody generator
CONSTRUCTION
RUP
ANJA
NA
quired notes can be played properly and
hence the tune can be heard. The notes
can also have breaks in between. This
feature can be explained by considering
five notes written in the following two
ways:
1. SA RE GA MA PA
2. SA---RE GA---MA PA
In the first case the notes are con-
tinuous. In the second case there are
breaks (no sound), indicated by ‘—’ for a
stipulated amount of time, in between
SA and RE as well as GA and MA. Each
of the circuits explained in this project
incorporates the break (no sound) fea-
ture.
You should make sure that you have
access to a musician before attempting
any of the circuits. In addition, you would
need a computer and a frequency meter
or a digital multimeter. The computer is
required to test the tunes, i.e. to make
sure that the given notes match the tune
of a given song.
A brief on music from the software
article ‘Generation of Indian Classical Mu-
sic on a Microprocessor’ by Prof. V.V.
Athani, published in April ’94 issue of
EFY, is as follows:
“Taking into account only one elec-
tronic organ (piano), the number of notes
in music are only seven—SA RE GA MA
PA DHA NI. But these basic notes are
divided into three octaves (refer Fig. 4),
where each octave also has notes called
ELECTRONICS FOR YOU ❚  MAY 2001
half notes. So each octave has twelve
notes. On a piano keyboard, black keys
in between white keys produce the aver-
age frequency of adjacent keys. For
example, ‘SA’ has a frequency of 595
Hz and ‘RE’ has a frequency of 668 Hz.
When a black key in between them is
pressed, a frequency of 631.5 Hz is pro-
duced. These black keys are called half-
note keys.”
Here we have selected a total of 28
notes, including all notes from the middle
octave, eleven notes from upper octave,
and a few from the lower octave. All the
28 notes with their respective frequen-
cies are given in Table I.
Software and testing of notes
Before moving to the software program,
let us see how the notes for a tune can
be obtained. Give your musician the
song for which you need notes. Write
those notes in terms of SA RE GA etc,
making sure that all the notes of the
tune lie within the range of the 28 notes
given in Table I. No sound in between
the notes, including its duration, as
also the duration of each particular
note, should be taken into account. For
example, if in a tune the time period of
a note SA is 500 ms and that of RE 1500
ms, the two notes can be written as
SA RE RE RE. Similarly, no sound
in between can be written as SA RE-RE-
SA.
The notes so obtained have to be con-
verted into data characters. This can be
done directly by using Table I; for ex-
ample, SA-RE RE GA---MA can be writ-
ten as C-E E G---H.
Execute the program (refer Appendix
‘A’ for the source code of the program)
and enter the delay value (say, 300). Now
enter the first line of the tune and press
‘Enter’ key. The tune can be heard. This
tune can be repeated
by pressing ‘R’. If this
tune needs to be
changed, or a new tune
is to be entered, press
any key. In this way all
the lines in a tune are
tested line by line. Af-
ter testing all the lines,
enter all the lines of the
tune once again and re-
check the tunes until
 CONSTRUCTION

you are satisfied. Press

‘E’ to quit the program.
Now convert the tunes
(data characters) to
hexadecimal values us-
ing Table I. These hexa-
decimal values are to be
entered into EPROM/
RAM at consecutive lo-
cations to get the tune.

EPROM-/RAM-based
melody generator
Since most parts of the
circuits for EPROM- and
RAM-based melody gen-
erators are similar, the
main circuits for both
versions have been in-
tegrated in Fig. 2. Rel-
evant changes have
been described appropri-
ately.
The common block
diagram for EPROM-
and RAM-based melody
generators is shown in
Fig. 1. A low-frequency
oscillator followed by a
binary counter is used to
generate the addresses
for EPROM/RAM.
In the case of
EPROM, the
preprogrammed data
output is directly
coupled to two 1-of-16
decoders (one for upper
nibble and the other for
Fig. 2: Main circuit of EPROM-/RAM-based melody generator

lower nibble of data).

However, in RAM
based-circuit, a key-
board is deployed at the
time of writing the data
at specified locations
(addresses) into the
RAM. Thereafter the
keyboard is detached
and data output pins are
connected to two 1-of-16
decoders, as in EPROM-
based circuit. Only 28
outputs (out of 32 out-
puts) of the two decod-
ers, with each repre-
senting a unique note,
are used in conjunction
with individual presets
to control the oscillator’s

ELECTRONICS FOR YOU ❚  MAY 2001

 CONSTRUCTION

‘F’ and ‘M’ within pa- for ‘Reset’ and ‘Stop-clock’ functions.
rentheses indicate fe- The remaining 14 outputs from each
male and male connec- of the two CD4514 (IC4 and IC5) are
tors, respectively. used together for generating one of the 28
Data bits of the notes corresponding to the hex data
lower nibble (D0 stored and the output from a specific
through D3) are con- memory location. The Q2 to Q15 outputs
nected from EPROM to of IC4 and IC5 are connected via diodes
the address pins of 1- D101 (and preset VR101) through diode
of-16 decoder IC4 D128 (and preset VR 128), respectively, to
(CD4514) and those of the tone oscillator circuit built around
the higher nibble (D4 timer NE555 (IC101), as shown in Fig. 3.
through D7) to the ad- (EFY lab note. The numbering of diodes
dress pins of another 1- and other components of this circuit has
of-16 decoder IC5 been done for convenience.)
(CD4514). IC101 is wired with presets to form
Fig. 3: Tone oscillator The ‘Hex value’ col- an oscillator. At any time, only one of
umn in Table I indi- diodes D101 to D128, depending on the
cates that either the current note selected via EPROM’s ad-
lower nibble or the up- dressed location, will be forward biased
per nibble, or both and its corresponding preset will form part
nibbles, of stored hex of the oscillator circuit. Each preset is ad-
data in memory will al- justed to a value (refer Table I) to obtain
ways be zero. It means the frequency corresponding to the se-
Fig. 4: Piano keyboard that at least one of the lected note.
two CD4514 (IC4 and No sound (00 hex). Breaks are nec-
frequency and thus the resulting sound IC5) will have binary 0000 at its address essary in between the notes to make a
from the loudspeaker. input. The Q0 output of these ICs is not tune sound perfect. The break period,
used for generating any note. The hex termed as ‘no sound,’ is obtained by out-
data 00 (i.e. 0000 0000) is, in fact, used putting hex value 00 from the EPROM.
EPROM-based circuit for no sound. Similarly, hex values 01 During this input to the two 1-of-16 de-
In Fig. 2, NE555 timer (IC1) is wired in (0000 0001) and 10 (0001 0000) are used coder ICs (IC4 and IC5), the Q0 outputs
astable mode, which provides clock pulses
for the 12-stage binary counter CD4040
(IC2). In the EPROM version, jumper J1
is used to permanently short pin 3 of IC1
and pin 10 of IC2, while there is no need
to operate push-to-on switches S2 and S3
and you can leave them open (i.e. in off
state).
An 8-bit, 4k EPROM 2732 is used for
IC3. Since its pin 21 is
address A11, switch S6 is
to be kept in position ‘a’
to connect it to O11 out-
put of IC2. When clock
pulses are fed to IC2, it
starts counting up from
its reset state (all outputs
zero). The binary outputs
of IC2 serve as the ad-
dress for memory loca-
tions in the EPROM,
where the data for the
notes is stored. For the
EPROM version, the pins
of connector K2(F) are to
be kept shorted to the
Fig. 5: Flow
chart of corresponding pins of
doorbell connector K3(M). Suffixes Fig. 6: Actual-size single-sided PCB-1 layout for circuit of Fig. 2

ELECTRONICS FOR YOU ❚  MAY 2001

 CONSTRUCTION

input from PARTS LIST

NAND gate (Common to EPROM, RAM and ROM)
N1 and the Semiconductors:
clock oscilla- IC101 - NE555 timer
tor starts os- IC201 - 7805 +5V regulator
D101-D128 - 1N4007 rectifier diode
cillating.
D201-D204 - 1N4001 rectifier diode
The flow
Resistors (¼-watt ±5% carbon, unless other-
chart for a wise stated)
doorbell R101 - 5-kilo-ohm
given in Fig. VR101-VR128 - Refer Table I
5 shows the VR129 - 10-kilo-ohm preset
order in Capacitors:
which the C101 - 0.1µF ceramic disc
data is en- C102 - 0.22µF ceramic disc
C103 - 10µF, 12V electrolytic
tered/read. C201 - 100µF, 25V electrolytic
First, the C202 - 1000µF, 16V electrolytic
data per- Miscellaneous:
taining to LS101 - 8-ohm, 4W loudspeaker
the first X201 - 230V AC primary to 0-6V,
tune is 500mA sec. transformer
stored. Once (for EPROM and ROM)
all the notes Semiconductors:
(including IC1 - NE555 timer
breaks/‘no IC2 - CD4040 counter
IC3 - (1) 2732 EPROM
sound’ peri- - (2) 6116 RAM
ods) for the IC4, IC5 - CD4514 1-of-16 decoder
first tune IC6 - CD4011 quad NAND gate
are stored, a T1-T8 - BC547 npn transistor
D1-D64 - 1N4007 rectifier diode
stop-clock LED1-LED20 - Red LED
data (10
Resistors (¼-watt ±5% carbon, unless other-
hex) is wise stated)
stored at the R1, R7 - 10-kilo-ohm
Fig. 7: Actual-size single-sided PCB-2 layout for circuit of Figs 3 and 11
end of tune- R2 - 22-kilo-ohm
1 that stops R3, R8 - 470-ohm
of both decoder ICs go high. after the first tune. Now on pressing R4 - 1-mega-ohm
R5, R9-R16 - 1-kilo-ohm
Since Q0 outputs are not connected push-to-off switch S1 momentarily, the R6 - 2.2-kilo-ohm
to the tone oscillator circuit (or anywhere clock advances to start the second tune R17, R18 - 100-ohm
else), no note or sound is produced for (tune-2). Thus each tune is made to end R19 - 330-ohm
hex value 00, and there is only time with 10 hex code for stop signal. When VR1 - 100-kilo-ohm preset
elapse. ‘No sound’ code is used as break all tunes of the doorbell are exhausted, Capacitors:
between the notes. the last stop-clock data is followed by a C1 - 22µF, 12V electrolytic
C2 - 0.1µF ceramic disc
Reset (01 hex). When the data out- reset data (01 hex), so that one goes to
C3 - 0.01µF ceramic disc
put of EPROM corresponds to 01 (hex), the start of tune-1 (on reset), and the cycle C4 - 0.22µF ceramic disc
Q1 output of IC4 goes high. Since Q1 out- repeats. Miscellaneous:
put of IC4 is connected to MR (master For instance, the hexadecimal value S1 - Push-to-off switch
reset) pin 11 of counter IC2 via resistor- of ‘SA’ is 70H (refer Table I) or binary S2-S5 - Push-to-on switch
capacitor network R2-C3, IC2 is reset 0111 0000, which means that binary data S6 - SPDT switch
when data 01 hex appears at the output at the input of IC4 and IC5 is 0000 and J1, J2 - Jumper
K1-K5 - Connectors
of EPROM. 0111, respectively. As a result, only Q7
Stop-clock signal (10 hex). When output of IC5 goes high. This output
the data output of EPROM corresponds brings the associated preset resistor tuned into circuit the corresponding preset tuned
❚
to 10 (hex), Q1 output of IC5 goes high, to the frequency of SA (595 Hz) into the to the frequency of SA (1190 Hz). The
which after inversion by NAND gate N1 oscillator circuit. Simultaneously, data Q0 output of IC5 has no effect, as Q0 is
is applied to pin 4 of IC1 via normally- 0000 at the input pins of IC4 causes its open. In this way both the ICs (IC4 and
closed contacts of push-to-off switch S1. Q0 pin to go high. But since Q0 is left IC5) function in accordance with data at
As a result, IC1 stops oscillating and pro- open, there is no effect. their inputs to produce the corresponding
ducing clock pulses. The active ‘high’ Q1 Similarly, when binary data corre- notes.
❚
output of IC5 is therefore referred to as sponding to note SA (05 hex) is output Power supply. The circuit shown in
stop-clock signal in this circuit. Pushing by the EPROM, Q5 of IC4 and Q0 of IC5 Fig. 11 is used to obtain the regulated 5V
switch S1 at this stage removes logic ‘high’ go high. The Q5 output of IC4 brings DC using IC 7805.

ELECTRONICS FOR YOU ❚  MAY 2001


Fig. 8: Component layout for PCB-1
The actual-size, single-sided PCB lay-
outs for the circuits of Figs 2 and 3
(common for EPROM and RAM versions
of the melody generator) are shown in
Figs 6 (PCB-1) and 7 (PCB-2), respectively.
The component layouts for PCBs of Figs 6
and 7 are shown in Figs 8 and 9, respec-
tively. The power supply circuit (Fig. 11)
has also been integrated in PCB-2.
This circuit can be used as a door-
bell, or even as a car-reverse horn. The
flow chart for car-reverse horn is shown
in Fig. 12. The necessary connections are
shown in Fig. 13. When the circuit is used
as a car-reverse horn, data flows from
the next address location to where it
stopped earlier.
Preset adjustment
Connections to join the two PCBs should
be made only after the adjustment of pre-
sets on PCB-2 using any of the following
three procedures:
Using frequency meter. Assemble all
the components of PCB-2. Connect a probe
to the Vcc using a crocodile clip at the
other end. Switch on the 5V power supply
and connect the output from the tone
oscillator on the PCB to the frequency
meter. Now connect the probe to the an-
ode of diode D101 and adjust preset resis-
CONSTRUCTION
tor VR101 for 446 Hz (refer Table I).
In this way all the variable resistors are
adjusted one by one by connecting +5V
from the probe to the corresponding di-
odes.
With the help of a musician. You
can seek the help of a musician if you
don’t have access to a frequency meter or
a digital multimeter. Connect the output
from the tone oscillator to the speaker
and switch on the power supply. First,
choose the main notes in the middle oc-
tave. Connect the probe to the respective
diode of SA and tell the musician to
adjust the variable resistor to the fre-
quency of SA. Now connect the probe
to the respective diode of RE and adjust
the variable resistor to the frequency
of RE, and so on. After adjusting main
notes, adjust half notes. (In Table I,
music notes shown in small letters are
half notes.) This method will be success-
ful only if the musician is well trained in
music.
Using digital multimeter. First, as-
semble only preset resistors VR101
through VR128. Now adjust the variable
resistors to their respective values (shown
in column 6 of Table I) using a digital
multimeter. Use the variable resistors with
maximum value as given in column 7 of
Table I. You can also use the values shown
ELECTRONICS FOR YOU ❚  MAY 2001
in the circuit diagram of Fig. 3, but ad-
justing the variable resistors to lower val-
ues in the table may be very tedious.
Any method may be used to adjust
all the variable resistors. But after play-
ing a tune, it may be felt that the tune
doesn’t sound proper, even if it sounded
right with computer. The reason can be
that the resistors were not properly tuned
or it may be due to minute imperfections
in output voltages from IC4 and IC5.
These imperfections can be overcome by
readjusting the resistors by the method
given below.
The imperfections can only be ad-
justed when data from the EPROM is
heard. But, the notes of a tune will not
be in an increasing frequency sequence.
The sequence should be PA , dha , ----- to
❚ ❚
❚ ❚
----- DHA , ni . To do this, include at least
two sets of sequence data from Table I
with 2-3 bytes of gap in between succes-
sive sequences, after all the tunes, as
shown in the flowchart of Fig. 10. This
method of readjustment is used only to
prevent disconnection of PCB of Fig. 7
from PCB of Fig. 6 and tuning the resis-
tors again and again.
Remove jumpers J1 and J2. Switch
on the power supply. Press switch S4 to
provide clock pulses for IC2. Say, if the
EPROM contains 10 tunes, after the tenth
tune release S4. Now keep pressing S2
momentarily until the first note of the
sequence (PA ) sounds. Now connect the
❚
frequency meter at the speaker terminals
(disconnect speaker if necessary) and ad-
just VR101 if the value of the frequency
meter reading is not consistent with the
value in the Table I. Press S2 again to
adjust VR102, and so on. After the read-
justment process insert jumpers J1 and
J2 and press S3 to reset IC2.
RAM-based circuit
The only difference between the EPROM-
and RAM-based circuits is the use of
RAM chip in place of EPROM and a key-
board for programming the RAM in RAM-
based circuits. Besides, an LED panel is
used for displaying the selected RAM ad-
dress.
Switch S2 is used to manually pro-
vide clock pulses to IC2. Similarly, switch
S3 is used to manually reset IC2 before
and after programming. Both switches (S2
and S3) are integrated into Fig. 2. The
connector K1 in between IC2 and IC3 is
used to connect to K5(M) connecter along

Fig. 9: Component layout for PCB-2
with the associated LEDs as shown in
Fig. 14. EPROM 2732
(IC3) is replaced with an
8-bit, 2k SRAM (6116).
Pin 21 of 6116 is WE
(write enable – active
low). Switch S6 is to be
kept in position ‘b’ while
working with RAM.
At the time of writ-
ing (programming) data
into the RAM, there is
no connection between
connectors K2(F) and
K3(M). Also, jumper J1
is removed. To program
the RAM, K4(M) is to be
mated with K2(F). After
programming is over,
K2(F) is connected to
K3(M).
IC6 (CD4011) con-
tains four NAND gates,
Fig. 10: Flow
of which NAND gate N1
chart for re- is used for stop-clock sig-
adjustment nals. It functions in the
CONSTRUCTION
same man- The LEDs indicate
ner as in an addresses of
EPROM- memory locations of
based cir- RAM. Glowing of
cuit. The in- LED1 through
puts of N1 LED11 together
are shorted means that last
and con- RAM location is be-
nected to ing addressed. (We
the ground are using a 2kB
via resistor RAM.)
R7. So the Keyboard. The
output of N1 circuit diagram of
becomes keyboard is shown
high, which in Fig. 15. Male con-
keeps IC1 nector K4(M) should
oscillating. be connected to
After a Fig. 12: Flow chart K2(F) during pro-
of car-reverse horn
stop-clock gramming. The
(active circles shown with
‘high’) signal the corresponding hex values are simple
appears at metallic contacts (or tabs) that avoid
the input of the use of a large number of switches.
NAND gate To enter the hex data, the probe is
N1, its out- touched to the corresponding metallic con-
put goes tact tab.
low. When The keyboard can be easily wired us-
switch S1 is ing a general-purpose board. To test the
pressed, the keyboard after wiring, connect point ‘A’
output of N1 to the ground via a 100-ohm resistor (R18)
goes high as shown in Fig. 15. Now touch each and
and IC1 every tab one by one using the metallic
starts oscil- probe and verify that the data shown by
lating again. the LEDs (LED13 through LED20) is con-
Gates N2 and N3 are used to provide read sistent with the hex value shown on the
and write logic for RAM. In read condi- tab/circle. After checking, disconnect re-
tion, the output of N3 is at logic 0 be- sistor R18.
Connector K3 should
be soldered to the PCB
by using a ribbon cable
of adequate length, so
that it could be easily
connected to K2(F) after
programming. The out-
puts from IC4 and IC5
go to preset-array part
of the tone oscillator.
Wiring is done similar to
that in an EPROM ver-
Fig. 11: Power supply sion.
cause its inputs are at logic 1. Press-
ing of switch S5 provides ‘write’
condition, since the output of gate N3
is at logic 1 and that of gate N2 at
logic 0.
LED connector. A separate male
connector K5(M) is fabricated with
LEDs as shown in Fig. 14. This con-
nector should be connected to K1(F). Fig. 13: Wiring connections for car-reverse horn
ELECTRONICS FOR YOU ❚  MAY 2001
 CONSTRUCTION

TABLE I Program-
ming. Connect
Music Frequency Data Hex Variable Variable Maximum
note of music character value resistor resistor value of LED connector
note (preset) in-circuit variable K5(M) to K1(F)
(Hz) number value (ohm) resistor and keyboard
Lower octave connector
PA❚ 446 1 20 VR101 8274 10k K4(M) to
dha❚ 472 2 30 VR102 7740 10k K2(F). Press
DHA❚ 500 3 40 VR103 7230 10k switch S3 mo-
ni❚ 530 A 50 VR104 6744 10k mentarily to
NI❚ 561 B 60 VR105 6288 10k reset IC2. No
Middle octave LED glows on
SA 595 C 70 VR106 5850 10k the LED con-
re 630 D 80 VR107 5445 10k nector, indicat-
RE 668 E 90 VR108 5055 10k ing the initial
ga 707 F A0 VR109 4698 5k address as
GA 749 G B0 VR110 4356 5k zero. Now
MA 794 H C0 VR111 4029 5k touch the tab
ma 841 I D0 VR112 3726 5k Fig. 14: LED indicator
circuit marked ‘00’
PA 891 J E0 VR113 3438 5k
dha 944 K F0 VR114 3165 5k with the probe.
DHA 1000 L 02 VR115 2910 5k Press S5 momentarily and lift the probe.
ni 1062 M 03 VR116 2655 5k Glowing of no LED on the keyboard indi-
NI 1120 N 04 VR117 2445 5k cates that ‘00’ is entered in the initial
Upper octave memory location. (It is good to enter ‘00’
SA❚ 1190 O 05 VR118 2220 5k in the first memory location.)
re❚ 1260 P 06 VR119 2016 5k Now get the hex dump values of the
RE❚ 1335 Q 07 VR120 1824 2k tunes. Press switch S2 to go to the next
ga❚ 1414 R 08 VR121 1644 2k memory location, indicated by LED1 (cor-
GA❚ 1498 S 09 VR122 1473 2k responding to address line A0), on the
MA❚ 1588 T 0A VR123 1308 2k LED connector strip. Touch the appropri-
ma❚ 1682 U 0B VR124 1158 2k ate tab with the probe to enter the corre-
PA❚ 1782 V 0C VR125 1014 2k
sponding hexadecimal value at memory
dha❚ 1888 W 0D VR126 876 1k
DHA❚ 2002 X 0E VR127 747 1k location 1. Press switch S5 and lift the
ni❚ 2122 Y 0F VR128 624 1k probe. The data entered into memory lo-
no sound — — 00 — — —
cation 1 is shown by keyboard LEDs in
binary form.
Reset à 01
Hex data values (refer Table I) are
Stop-clock à 10
such that any of the four LEDs corre-

Fig. 15: Keyboard and probe for programming RAM

ELECTRONICS FOR YOU ❚  MAY 2001

 CONSTRUCTION

Appendix ‘A’
#include <stdio.h> } case’F’:sound(707); break;
#include <dos.h> } break; case’S’:sound(1498);
#include <stdlib.h> void play(char *str,int d) case’G’:sound(749); break;
#include <conio.h> { break; case’T’:sound(1588);
#include <ctype.h> int i=0; case’H’:sound(794); break;
void play(char *str,int d); while(str[i]!=’\0') break; case’U’:sound(1682);
void main() { case’I’:sound(841); break;
{ switch(str[i]) break; case’V’:sound(1782);
int f,d=200; { case’J’:sound(891); break;
char ch1[180],ch2; case’1':sound(446); break; case’W’:sound(1888);
clrscr(); break; case’K’:sound(944); break;
printf(“\n Enter delay value:”); case’2':sound(472); break; case’X’:sound(2002);
scanf(“ %d” ,&d); break; case’L’:sound(1000); break;
while(1) case’3':sound(500); break; case’Y’:sound(2122);
{ break; case’M’:sound(1062); break;
printf(“\n enter tune :”); case’A’:sound(530); break; case’-’:nosound();
scanf(“ %s” ,&ch1); break; case’N’:sound(1120); break;
play(ch1,d); case’B’:sound(561); break; }
a:ch2=getch(); break; case’O’:sound(1190); delay(d);
if (tolower(ch2)==’r’) case’C’:sound(595); break; i++;
{ play(ch1,d); break; case’P’:sound(1260); }
goto a; case’D’:sound(630); break; nosound();
} break; case’Q’:sound(1335); }
if (tolower(ch2)==’e’) case’E’:sound(668); break;
exit(0); break; case’R’:sound(1414);

sponding to either D0 through D3 bits or
D4 through D7 bits would glow to show
the data entered. So it is easy to identify
whether the data entered is correct or
not. If necessary, make a table of binary
data along with corresponding hex val-
ues.
After entering all the tunes, discon-
nect keyboard from K2(F) and connect
K3(M) to K2(F). Now connect external
jumper J1 as shown in the circuit dia-
gram.
Switch S4 across jumper J1 terminals
is not necessary but it may prove useful if
any readjustment of variable resistors is
needed (as in the case of EPROM), or for
checking each and every tune one by one.
The programming steps are
summarised as below:
1. Press switch S3.
2. Touch tab 00 with the probe.
3. Press and release switch S5.
4. Lift the probe.
5. Press S2 to go to the next memory
location.
6. Repeat from step 2 onwards for the
next hex value programming.
7. After last data is entered, press S3.
8. Keep S4 pressed to check all the
tunes that have been entered.
9. Connect jumper J1 if all tunes are
entered.
The data table (Table I), writing of
musical notes, conversion of notes to hex
values, preset-array alignment, and flow
charts for door-bell and car-reverse tune
are also applicable for the RAM version.
(Stay tuned for the next issue)

ELECTRONICS FOR YOU ❚  MAY 2001

 C O N S T R U C T I O N

TELEPHONE LINE-INTERFACED Semiconductors:

PARTS LIST

GENERIC SWITCHING SYSTEM IC1 - NE555 timer

IC2, IC13, IC25 - CD4017 decade counter
IC3, IC9, IC12,
IC21, IC22 - 7474 dual ‘D’ flip-flops

PART II DWIV
EDI
IC4
IC5
- MT8870 DTMF decoder
- 74123 dual retriggerable
S.C. monostable multivibrator
IC6 - *7411 triple 3-input AND
gates
IC7 - 7432 quad OR gates
AJAY SUBRAMANIAN AND NAYANTARA BHATNAGAR IC8 - 74LS85 4-bit magnitude
comparator
IC10, IC19 - 7408 quad 2-input AND
gates

I
n Part I we had covered the inter- CLR1 pin 1 of IC12A, so that authentica- IC11, IC17 - 7404 hex inverters
face and control unit and the au- tion signal AUTH is deactivated on sys- IC14, IC15 - 74LS244 octal buffers/line
thentication unit. Before we proceed tem reset. drivers
IC16 - 7427 triple 3-input gates
with the description of the next unit (main Main device selection and switch- IC18 - 7400 quad 2-input NAND
device selection and switching unit) shown ing unit (Fig. 7). This circuit receives gates
in the block diagram of Fig. 1, the follow- StD control signal after a successful au- IC20 - 74125 quad bus buffers
ing modifications may be incorporated in thentication of the four-digit code by the IC23, IC24 - 74195 4-bit parallel access
shift registers
Part I: authentication unit. The AUTH and its IC26 - 7414 hex Schmitt inverters
1. In the interface unit (Fig. 2), re- inverse AUTH signals available on code IC27-IC29 - 74LS154 4-line to 16-line
place 2-input AND gate IC6A (7408) with authentication are used in this circuit for decoders
a 3-input AND gate (7411) and connect enabling various chips such as IC23 and Opto-1 - MCT2E opto-coupler
Reset signal from pin 13 of IC5 (1Q) to IC24 (74LS195), IC25 (CD4017), IC27 T1,T2 - 2N2222 npn transistor
D1,D2 - 1N4001 rectifier diode
the third input of the new 3-input AND through IC29 (74LS154), and StD gate D3, D4 - 1N4148 switching diode
gate. This modification has been done so IC19C (7408). ZD1, ZD2 - Zener diode 5.1V
that when Reset signal is low (active), no A combinational logic circuit, compris- LED1-LED10 - Red LEDs
part of the circuit is active. All ICs will ing three 3-input NOR gates inside 7427 Resistors (1/4W ± 5% carbon, unless speci-
be asynchronously reset. To avoid any con- (IC16) and two inverter gates (IC17B and fied otherwise)
fusion, change in the input connections of 17C) of 7404, has been used to discrimi- R1, R2, R5, R29 - 10-kilo-ohm
R3, R12, R30 - 100-kilo-ohm
IC6A AND gate is shown in Fig. 6. nate between an address (numeric digit)
R4 - 220-ohm
2. In the authentication circuit (Fig. and a switching signal (‘*’ for ‘on’ and ‘#’ R6-R9 - 51-kilo-ohm
3), CLR2* pin 13 of IC12B is to be discon- for ‘off’). DTMF digit switches 1 through R10 - 39-kilo-ohm
nected from +5V rail and joined with 9 and 0 (0 on the telephone keypad stands R11 - 56-kilo-ohm
for decimal 10 and the de- R13 - 330-kilo-ohm
R14-R18 - 1.2-kilo-ohm
coded output from R19 - 20-kilo-ohm
MT8870 is the equivalent R20, R27, R28 - 1-mega-ohm
binary number 1010) gen- R21-R24,
erate a logic-1, R_EN R31-R34 - 470-ohm
R25,R26 - 1-kilo-ohm
(register enable) signal,
R31-R34 - 4.7-kilo-ohm
while keys marked ‘*’ and
Capacitors:
‘#’ generate a logic-1,
C1 - 0.47µF, 160V polyester
S_EN (switching enable) C2,C4-C6 - 0.01µF ceramic disc
signal. Thus this combi- C3, C9, C13 - 10µF, 16V electrolytic
national logic differenti- C7, C8, C14 - 0.1µF ceramic disc
ates between register en- C10 - 100µF, 16V electrolytic
C11, C12 - 47µF, 16V electrolytic
able (R_EN) and device
Miscellaneous:
switching enable (S_EN)
Xtal - 3.57946MHz quartz crystal
signals. The R_EN and RL1 - Relay 6V, 100-ohm, 1 C/O
S_EN outputs for various - 5V, 1A regulated power
key depressions of the supply
telephone keypad are - Berg stick/FRC connectors
shown in Truth Table. - Ribbon cable etc.
The combinational *Note. IC 7408 is replaced with 7411 (refer
Fig. 6).
Fig. 6: Modification logic circuit is followed

ELECTRONICS FOR YOU ❚  MAY 2001

 C O N S T R U C T I O N

Fig. 7: Main device selection and switching unit

ELECTRONICS FOR YOU ❚  MAY 2001

 C O N S T R U C T I O N

by the RCLK and SCLK generation cir-

cuitry comprising ICs 18, 19, 25, and 26,
which allows the following functions to
be performed:
• After AUTH signal at Q (pin 8 of
IC12B in Fig. 3) goes low (active), one
can select a group and a device within
the selected group by next two DTMF
switch depressions on the telephone key-
pad, while a third key depression of ‘*’ or
‘#’ results into switching ‘on’ or ‘off’ of the
desired device.
• Multiple devices can be switched
on/off one after the other, once
authorisation signal AUTH becomes ac-
tive (low) without a system reset.
• The system can be reset after or
before switching ‘on’/‘off’ of the desired
device with the help of remote telephone
keypad. This feature can also be used for
avoiding switching on/off of a device if
the user perceives that he has selected a
wrong device.
When R_EN signal is logic 1, IC25
(CD4017) is clocked at the leading edge
of StD pulse, while one of the 74LS195
registers (IC23 or IC24, as enabled by
one of the Q outputs of IC25) is latched
at the trailing edge of the delayed Std
pulse (RCLK) as indicated by the direc-
tion of arrow on RCLK pulse in Fig. 7.
The resistor-capacitor combinations R26-
Fig. 8: Actual-size, single-sided PCB for the circuits in Figs 2 and 3 C11 and R25-C12 wired around Schmitt
inverter gates A through D of IC26 (7414)
provide the necessary delay for reliable
latching of the data in IC23 and IC24.
Resistors R27 and R28 across capacitors
C11 and C12, respectively, serve as bleed-
ers for discharging the respective capaci-
tors.
When S_EN signal is logic 1, clocking
of 7474 ‘D’ flip-flops via active 74LS125
gates occurs corresponding to the leading
edge of Std (SCLK) pulses, while the trail-
ing edge resets IC25 via capacitor C14, to
enable receiving of fresh group and de-
vice selection data.
(EFY note. The circuit comprising
IC25 and IC26 includes some modifica-
tions by EFY Lab to improve the timing
of RCLK and SCLK for reliable operation
of the RCLK and SCLK generation part
of the circuit.)
Group selection. When any of DTMF
numeric keys 1 through 9 and 0 on the
remote telephone keypad is depressed im-
mediately after AUTH signal goes active
low, R_EN signal goes to logic 1 (while
S_EN is logic 0). As a result, Std pulse
Fig. 9: Actual-size, single-sided PCB for the circuit in Fig. 7 passing through NAND gates IC18B and

ELECTRONICS FOR YOU ❚  MAY 2001

 C O N S T R U C T I O N

IC18C clocks IC25 with its leading edge.

IC25 is in reset condition before code au-
thentication due to ‘high’ AUTH signal,
and its Q0 (pin 3) is ‘high’. On clocking,
shifting of ‘high’ state from Q0 to Q1 (pin
2) enables AND gate IC19B, while AND
gate IC19 is still disabled. Thus the trail-
ing edge of RCLK passes through IC19B
to latch the MT8870-decoded data corre-
sponding to the mentioned numeric key
depression, which is available at the in-
put of group select register IC24, at its
output. This is the group select address.
The group select address is applied
to the address lines of 4-line-to-16-line
decoder IC29 (group selector). In the nor-
mal telephone keypad, we use only ten
numeric keys (1 through 9 and 0) and
hence only ten outputs (Y1 through Y10)
are available from IC29. The other six
outputs Y0 and Y11 through Y15 are not
used. Thus we can select any of the
groups 1 through 10 via outputs marked
Y1 through Y10 of IC29.
The output corresponding to the ad-
dress present at IC29’s input pins goes
low (active). This low (active) output se-
lects/enables another IC 74LS154 repre-
senting the corresponding group. (Please
note that this is only a demo version
circuit, wherein only two groups, out of
ten possible groups, can be accessed us-
Fig. 10: Component layout for PCB-1 ing IC27 and IC28. Pin 19 of IC27 and
IC28 can be connected to any of the group
select pins Y1 through Y10 of IC29, as
desired. Once connected, the specific
group numbers will get allocated to IC27
and IC28.)
Device selection within the se-
lected group. The next DTMF number
key depression (i.e. the sixth after
energisation of relay RL1 or the second
after the 4-digit authentication code)
causes shifting of ‘high’ on pin 2 (Q1) of
IC25 to pin 4 (Q2) in synchronism with
the leading edge of StD pulse clocking
IC25. As a result, AND gate IC19A is
enabled while AND gate IC19B is dis-
abled.
The trailing edge of delayed StD pulse
(RCLK) causes the data corresponding to
the mentioned numeric key to be latched
at the output of device select register
IC23. This device select address is ap-
plied to address input pins of all group
ICs (IC27 and IC28, here) in parallel.
However, since only one group IC is in
selected condition (as explained earlier),
the device control output corresponding
Fig. 11: Component layout for PCB-2 to the device select address present at

ELECTRONICS FOR YOU ❚  MAY 2001

 C O N S T R U C T I O N
Truth Table for Device Selection and Switching Switching on or
Keypad Decoded data input Switch and register off refers to Q out-
Key from MT8870 enable outputs put of the corre-
No. D3 D2 D1 D0 S_EN R_EN sponding ‘D’ flip-flop
1 0 0 0 1 0 1 (7474) going high or
2 0 0 1 0 0 1 low, respectively.
3 0 0 1 1 0 1 You may suitably
4 0 1 0 0 0 1
5 0 1 0 1 0 1 use the flip-flop out-
6 0 1 1 0 0 1 puts to energise a re-
7 0 1 1 1 0 1 lay or fire a triac or
8 1 0 0 0 0 1 control the corre-
9 1 0 0 1 0 1
0(10) 1 0 1 0 0 1
sponding device/de-
* (11) 1 0 1 1 1 0 vices.
#(12) 1 1 0 0 1 0 If you press any
number key (1
the active group input is pulled low. This through 9 or 0) instead of ‘*’ or ‘#’ key on
active low output is used as the control the DTMF keypad, IC25 will receive a
signal for a corresponding tri-state gate clock pulse via AND gates IC18B and
of 74LS125 (IC20). IC18C, and the ‘high’ state will shift from
We have shown only four gates, out Q2 to Q3 (pin 7 of IC25). Since Q3 output
of possible 100, in this circuit. The out- is coupled to the base
put pins of tri-state gates are connected of transistor T2 via diode D4, it will re-
to the clock inputs of the corresponding sult into a system reset (as explained
‘D’ flip-flops (only four out of possible 100 in Part I). A system reset implies that
are shown). The clock pins of IC21 and you have to redial the local telephone
IC22 have been pulled high to avoid any number from remote telephone. When re-
noise triggering when tri-state buffers are lay RL1 again energises, redial the four-
in high-impedance state. digit authentication code, followed by
Switching the selected device. Only group select, device select, and switch on
one device corresponding to the digit in (*) or switch off (#) codes, as explained
the registers— IC24 for group address and earlier.
IC23 for device address— is enabled to be Thus, after dialing two digits identi-
affected by the signal (‘*’ or ‘#’) as the fying the group and the device within that
seventh (or the third after authentica- group, if we press a third numeric digit
tion) code. On pressing DTMF keypad instead of ‘*’ or ‘#’ on the remote tele-
switch ‘*’ or ‘#’, the selected device is phone keypad, a system reset can be
switched on or switched off depending on achieved remotely. This feature can also
the key pressed. D0 bit of the decoded be utilised to bypass switching operation
switching signals ‘*’ and ‘#’ is applied if the user realises that he has selected a
to data pins of all 7474 flip-flops in wrong group/device.
parallel. Only the data corresponding Operation summary. The entire op-
to the selected device gets clocked via eration can be summarised as below:
the corresponding tri-state gate of • Using the remote telephone key-
74LS125. pad, dial the local number of the
The Q2 output of IC25 is still high telephone to which the circuit is con-
when SCLK is generated and, as a re- nected.
sult, AND gate IC18D is enabled to al- • If the local handset is lifted before
low application of SCLK to all 74LS125 the programmed number of rings, a nor-
gates on depression of either ‘*’ or ‘#’ on mal conversation can ensue.
the remote keypad. Switching takes place • If the handset is not lifted before
at the trailing edge of SCLK pulse, while the programmed number of rings, wait
the trailing edge of SCLK pulse causes for simulated off-hook status of the local
resetting of IC25, thereby creating condi- telephone handset (indicating energisation
tions that were unavailable just before of relay RL1).
the previous group selection. Subse- • Now dial the four digits of the pre-
quently, you can select any other (or the set authentication code in a proper se-
same) group and any other (or the same) quence from the remote keypad within
device. You can switch on or off the se- the preset duration. A system reset will
lected device by following the same pro- occur in case the 4-digit code is not
cedure. dialed within the preset duration or
ELECTRONICS FOR YOU ❚  MAY 2001
the code used is wrong, which causes
de-energisation of the relay and creates
conditions similar to on-hook state of
the local telephone handset. So you will
have to repeat all steps from the begin-
ning.
• If the 4-digit authentication code
matches the preset code, you can dial the
next two digits identifying the group and
the device within that group selected for
the purpose of switching on or off (or even
as a dummy operation for the purpose of
forcing a system reset).
• Dialing ‘*’ from the remote tele-
phone keypad will result into switching
on of the selected device, while dialing ‘#’
will result into switching off of the se-
lected device. (Dialing any number, 1
through 9 or 0, causes a system reset.
Relay RL1 will be de-energised, and you
will have to restart from the initial step.)
You can proceed with the same procedure
to switch on/off the next selected device.
The procedure can be repeated for any
number of devices (one-at-a-time) with-
out affecting the status of non-selected
devices.
Testing. It is recommended that the
circuit be built in stages, verifying proper
operation at each stage. The main switch-
ing circuit may be assembled convention-
ally, with logic operation tested at vari-
ous points. The authentication circuit is
also self-contained and may be assembled
and debugged independently.
However, care must be taken while
assembling the interface and control unit.
The ASIC must be assembled first and
tested for proper operation and output lev-
els, followed by rigging and testing of
monostable multivibrators in the 74123.
The ring pulse generator and decade
counter, CD4017, comes next. Finally, in-
terface connections between the various
circuits should be made after verifying
the proper functioning of each circuit in
isolation.
A single-sided PCB for the circuits in
Figs 2 and 3, and including modification
referred in Fig. 6, is shown in Fig. 8,
while another single-sided PCB for the
circuit in Fig. 7 is shown in Fig. 9. The
component layouts for both the PCBs are
given in Figs 10 and 11, respectively.
Suitable connectors are provided to en-
able isolation and joining of individual
circuits using jumpers/connectors, for
easy testing and fault analysis during as-
sembly. ❏
June

2001
Circuit Ideas

2001
 CIRCUIT IDEAS

VERSATILE ZENER DIODE TESTER operation. In quick-test mode, you can

perform a rough check of zener diode’s
breakdown voltage up to 47 volts. In qual-
ity-test mode, you can check dynamic im-
MAR
K. UDHAYA KUMARAN IL KU pedance characteristic for zener diodes
SUN
from 3.3V to 120V.
Commonly available step-down trans-

Z
ener diodes available in the mar- digital voltmeters, control systems, and formers X1 and X2 (230V AC primary to
ket are specified according to their precision power-supply circuits. However, 9V AC, 750 mA sec. each) are connected
breakdown voltage as well as tol- for a common hobbyist it is not necessary back-to-back as shown in the figure. A
erance. The tolerance may vary from 5 to check zener diodes critically, and only bridge rectifier followed by filter capaci-
per cent to 20 per cent. The circuit of a checking its dynamic impedance charac- tor C1 converts the output from X2 trans-
versatile zener diode tester presented here teristic is sufficient. former to DC. Neon lamp L1 indicates
enables you to verify the specified break- Dynamic impedance implies the de- the presence of higher DC voltage (220V
down voltage and tolerance values. In ad- gree of change in a zener diode’s voltage approximately) across capacitor C1, which
dition, you can check the dynamic imped- with the change in current. Expressed in is used to test various zener diode values
ance of a zener diode. ohms, it equals the small change in zener from 3.3V to 120V.
The dynamic imped-
ance characteristics of a
zener diode determine
as to how well the ze-
ner diode regulates its
own breakdown voltage.
Thus this circuit can be
used to compare the dy-
namic impedance char-
acteristics of zener di-
odes from a lot and seg-
regate/categorise them
accordingly.
For full-fledged ze-
ner diode testing you
will have to refer to the manufacturer’s voltage divided by the corresponding An advantage of using this high-volt-
datasheet to check zener diode parameters change in zener current (centered around age circuit is that the current gets re-
such as zener voltage, power, and cur- the test current figure prescribed in stricted to a low value. It delivers only 3
rent (maximum/nominal) ratings. In ad- datasheets by manufacturers). From mA (approx.) when testing zener diodes
dition, temperature coefficient and dy- datasheets it is observed that test cur- with higher breakdown values (e.g. 120V
namic impedance have also to be checked rent value is high for low-voltage zener zener diode), but while testing zener di-
if zener diode is to be used for critical diodes and low for higher-voltage zener odes of low breakdown values, such as
functions such as voltage reference for diodes. However, the dynamic impedance 3.3V, it delivers a current slightly above
value will be low for low-voltage zener 20 mA. Such power-supply characteris-
TABLE I
Minimum and Maximum Test Current diodes and vice versa for higher-voltage tics suit our requirement, as stated ear-
Values zener diodes. lier. Since a small current is used for test-
Zener diode values IT(min) IT(max) To test 3.3V to 120V zener diodes by ing of zener diodes, there is no danger of
3.3V to 4.3V 10mA 15mA the practical dynamic impedance method, zener diodes getting damaged during test-
4.7V to 18V 5mA 10mA you need to have a variable voltage (0 to ing using the dynamic impedance method.
20V to 39V 2mA 4mA Before using the circuit, check DC volt-
above 120V) and current (1 mA to 150
Note: Zener diode power ratings are 250 mW, mA) supply source. Designing this type of age across test terminals A and B without
400 mW, and 500 mW.
power supply is quite complicated and is connecting any zener diode and then flip
TABLE II prone to damage if excess current is toggle switch S2 to quick-test position. DC
Minimum and Maximum Test Current drawn accidentally. voltage available across terminals A and
Values The zener diode tester circuit pre- B will be around 200V DC. Now put toggle
Zener diode values IT(min) IT(max) sented here has been designed consider- switch to quality-test position. DC voltage
3.3V to 12V 10mA 15mA ing the above factors. It is capable of test- can now be adjusted from 6V DC to 200V
13V to 27V 5mA 10mA ing zener diodes of breakdown voltage rat- DC (approx.) with the help of potentiom-
30V to 43V 2mA 5mA ings of upto 120V and wattage ratings of eter VR1. After these preliminary checks,
47V to 75V 1.5mA 3mA
250 mW, 400 mW, 500 mW, and 1W. the circuit is ready for operation.
82V to 120V 1mA 2mA
The circuit can be deployed in quick- To test zener diode by quick-test
Note: Zener diode power rating is 1 watt.
test mode as also in quality-test mode of method, connect zener diode across termi-

ELECTRONICS FOR YOU ❚  JUNE 2001


nals A and B and flip switch S1 to ‘on’
position. Note down DC voltage in digital
multimeter M2, which is the rough break-
down voltage. In quick-test method you
can test zener diode values up to 47 volts
safely. For higher-value zener diodes you
will have to increase the value of resistor
R3 suitably. If zener diode presents a short,
digital multimeter M2 will read ‘0’ volts.
To perform quality test on the same
zener diode, turn switch S1 ‘off’ and re-
move zener diode from across terminals A
and B. Now turn switch S1 ‘on’ and adjust
potentiometer VR1 to obtain DC voltage
(on digital multimeter) across terminals A
CIRCUIT IDEAS
and B equal to the one found during quick
test method. Now keep potentiometer VR2
in mid position and connect zener diode
across terminals A and B.
(Note. Before testing zener diode, re-
fer Table I and Table II for the minimum
test current (ITmin) and maximum test
current (ITmax) required for various ze-
ner diode values, depending upon their
wattage rating.)
Test current is adjusted using poten-
tiometer VR2 and measured using meter
M1 (A 0-25mA analogue milliampere
meter or a 0-20mA digital multimeter can
be used.)
ELECTRONICS FOR YOU ❚  JUNE 2001
Now adjust potentiometer VR2 and
note down changes in zener voltage dur-
ing ITmin and ITmax conditions. If the re-
quired current is not available, increase
DC voltage by adjusting potentiometer
VR1 suitably. While changing test current
from ITmin to ITmax, the voltage variation
across zener diode should be less than 1
volt for lower-value zener diodes and a
few volts for higher-value zener diodes. A
voltage variation of more than this value
indicates that zener diode is not properly
regulating. When comparing zener diodes
of same values, the zeners showing less
voltage deviation would regulate better.

DTMF PROXIMITY DETECTOR
K.S. SANKAR
A
DTMF-based IR transmitter and
receiver pair can be used to realise
a proximity detector. The circuit
presented here enables you to detect any
object capable of reflecting the IR beam
and moving in front of the IR LED photo-
detector pair up to a distance of about 12
cm from it.
The circuit uses the commonly avail-
able telephony ICs such as dial-tone gen-
erator 91214B/91215B (IC1) and DTMF
decoder CM8870 (IC2) in conjunction with
infrared LED (IR LED1), photodiode D1,
and other components as shown in the
figure. A properly regulated 5V DC power
supply is required for operation of the cir-
cuit.
The transmitter part is configured
around dialer IC1. Its row 1 (pin 15) and
CIRCUIT IDEAS
NA
ANJA
RUP
column 1 (pin 12) get connected together
via transistor T2 after a power-on delay
(determined by capacitor C1 and resis-
tors R1 and R16 in the base circuit of the
transistor) to generate DTMF tone (com-
bination of 697 Hz and 1209 Hz) corre-
sponding to keypad digit “1” continuously.
LED 2 is used to indicate the tone
output from IC3. This tone output is am-
plified by Darlington transistor pair of T3
and T4 to drive IR LED1 via variable re-
sistor VR1 in series with fixed 10-ohm
resistor R14. Thus IR LED1 produces
tone-modulated IR light. Variable resis-
tor VR1 controls the emission level to vary
the transmission range. LED 3 indicates
that transmission is taking place.
A part of modulated IR light signal
transmitted by IR LED1, after reflection
ELECTRONICS FOR YOU ❚  JUNE 2001
from an object, falls on photodetector di-
ode D1. (The photodetector is to be
shielded from direct IR light transmis-
sion path of IR LED1 by using any opaque
partition so that it receives only the re-
flected IR light.) On detection of the sig-
nal by photodetector, it is coupled to
DTMF decoder IC2 through emitter-fol-
lower transistor T1.
When the valid tone pair is detected
by the decoder, its StD pin 15 (shorted to
TOE pin 10) goes ‘high’. The detection of
the object in proximity of IR transmitter-
receiver combination is indicated by
LED1. The active-high logic output pulse
(terminated at connector CON1, in the
figure) can be used to switch on/off any
device (such as a siren via a latch and
relay driver) or it can be used to clock a
counter, etc.
This DTMF proximity detector finds
applications in burglar alarms, object
counter and tachometers, etc.
 CIRCUIT IDEAS

first flip-flop and CLR pins of the other

STEPPER MOTOR CONTROL

three flip-flops goes active ‘low’ (because
of the power-on-reset circuit formed by
MAR R1-C1 combination) to set the first flip-
IL KU
JAYDIP APPASAHEB DHOLE SUN flop and reset the remaining three flip-
flops. On reset, Q1 of IC2 goes ‘high’ while

A
simple, low-cost hardwired step inside ULN2003 (IC4) and connected to all other Q outputs go ‘low’. External re-
per motor control circuit that can the stepper motor windings marked ‘A’ set can be activated by pressing the reset
be used in low-power applications, through ‘D’ in the figure. The common switch. By pressing the reset switch, you
such as moving toys etc is presented here.
The circuit comprises a 555 timer IC
configured as an astable multivibrator
with approx. 1Hz frequency. The fre-
quency is determined from the following
relationship:
Frequency = 1/T = 1.45/(RA + 2RB)C
Where RA = RB = R2 = R3 = 4.7 kilo-ohm
and C = C2 = 100 µF.
The output of timer is used as clock
for two 7474 dual ‘D’ flip-flops (IC2 and
IC3) configured as a ring counter. When
power is initially switched on, only the
first flip-flop is set (i.e. Q output at pin 5
of IC2 will be at logic ‘1’) and the other
three flip-flops are reset (i.e. their Q out-
puts will be at logic ‘0’). On receipt of a
clock pulse, the logic ‘1’ output of the first
flip-flop gets shifted to the second flip- point of the winding is connected to +12V can stop the stepper motor. On releasing
flop (pin 9 of IC2). Thus with every clock DC supply, which is also connected to pin the reset switch, the stepper motor again
pulse, the logic ‘1’ output keeps shifting 9 of ULN2003. The colour code used for starts moving further in the same direc-
in a ring fashion. the windings is shown in the figure. tion.
Q outputs of all the four flip-flops are When the power is switched on, the
amplified by Darlington transistor arrays control signal connected to SET pin of the

ELECTRONICS FOR YOU ❚  JUNE 2001


LOW-COST INTERCOM
PRADEEP G.
T
he intercom circuit described here
uses two transistors, an audio
transformer, and a few passive
CIRCUIT IDEAS
SUN
IL KU
MAR
pacitor C3 gets connected between the
components in addition to condenser mi- base of transistor T2 and the top end of
crophone and low-wattage speaker (refer primary winding of audio output trans-
Fig. 1). The complete unit can be made former. As a result, the amplifier circuit
on a general-pur-
pose veroboard.
The micro-
phone signals are
amplified by a
two-stage transis-
tor amplifier,
while the speaker
is driven through
an audio output wired around transistor T2 gets converted
transformer (similar into a Hartley oscillator and produces an
to the one used in audible tone for call-bell.
transistor radios). To build a two-way intercom set, make
When ring button two identical units with the speaker of
(push-to-on switch each circuit installed near the other unit
S1) is pressed, ca- as shown in Fig. 2.
ELECTRONICS FOR YOU ❚  JUNE 2001
 CIRCUIT IDEAS

HIGH-POWER CAR BATTERY cuit is added. If the output voltage ex-

ceeds 15V due to some reason such as

ELIMINATOR
component failure, the SCR fires because
of the breakdown of zener ZD2. Once SCR
fires, it presents a short-circuit across the
MAR
IL KU unregulated DC supply, resulting in the
SUN
blowing of fuse F1 instantly. This offers
T.K. HAREENDRAN guaranteed protection to the equipment

T
o operate car audio (or video) sys-
tem from household 230V AC
mains supply, you need a DC
adaptor. DC adaptors available in the
market are generally costly and supply
an unregulated DC. To overcome these
problems, an economical and reliable cir-
cuit of a high-power, regulated DC adap-
tor using reasonably low number of com-
ponents is presented here.
Transformer X1 steps down 230V AC
mains supply to around 30V AC, which is
then rectified by a bridge rectifier com-
prising 5406 rectifier diodes D1 through
D4. The rectified pulsating DC is connected and to the
smoothed by two 4700µF filter capacitors circuit itself.
C1 and C2. This circuit can
The next part of the circuit is a se- be assembled using a
ries-transistor regulator circuit realised small general-pur-
using high-power transistor 2N3773 (T1). pose PCB. A good-
Fixed-base reference for the transistor is quality heat-sink is
taken from the output pin of 3-pin regu- required for transis-
lator IC1 (LM 7806). The normal output tor T1. Enclose the
of IC1 is raised to about 13.8 volts by complete circuit in a
suitably biasing its common terminal by age reference at a low cost. LED1 also readymade big adaptor cabinet as shown
components ZD1 and LED1. This simple works as an output indicator. in the figure.
arrangement provides good, stable volt- Finally, a crowbar-type protection cir-

ELECTRONICS FOR YOU ❚  JUNE 2001

 CIRCUIT IDEAS

AUTOMATIC PLANT IRRIGATOR the water. LED1 glows up as the water

reaches the probes.
EDI For small areas a small pump such
PRIYANK MUDGAL DWIV
S.C. as the one used in air coolers is able to
pump enough water within 5 to 6 sec-

T
he circuit presented here waters ciently wet, the resistance between sen- onds. The timing components for IC2 are
your plants regularly when you sor probes decreases rapidly. This causes selected accordingly. The timing can be
are out for a vacation. pin 1 of op-amp N1 to go ‘high’. LED1 varied with the help of preset VR2.
The circuit comprises a sensor part glows to indicate the presence of adequate The circuit is more effective indoors
built using only one op-amp (N1) of quad water in the soil. The threshold point at if one intends to use it for long periods.
op-amp IC LM324. Op-amp N1 is config- which the output of op-amp N1 goes ‘low’ This is because the water from reservoir
ured here as a comparator. Two stiff cop- can be changed with the help of preset (bucket, etc) evaporates rapidly if it is
per wires are inserted in the soil contain- VR1. kept in the open. For regulating the flow
ing plants. As long as the soil is wet, con- To arrange the circuit, insert copper of water, either a tap can be used or one
ductivity is maintained and the circuit re- wires in the soil to a depth of about 2 cm, end of a rubber pipe can be blocked us-
mains off. keeping them 3 cm apart. When the soil ing M-seal compound, with holes punc-
When the soil
dries out, the resis-
tance between the
copper wires (sensor
probes A and B) in-
creases. If the resis-
tance increases be-
yond a preset limit,
output pin 1 of op-amp
N1 goes ‘low’. This
triggers timer IC2
(NE 555) configured
as a monostable
multivibrator. As a re-
sult, relay RL1 is ac-
tivated for a preset
time. The water pump starts immediately gets dried, adjust VR1 towards ground tured along its length to water several
to supply water to the plants. rail until LED1 turns off and relay RL1 plants.
As soon as the soil becomes suffi- is energised. The motor starts pumping

ELECTRONICS FOR YOU ❚  JUNE 2001

Construction

2001

PROGRAMMABLE MELODY
GENERATOR - PART II
VYJESH M.V.
P
art I of this article dealt with the
design of EPROM and RAM ver-
sions of a programmable melody
generator. In this concluding part we shall
study a programmable melody generator
using home-brewed ROM.
There were only a few differences be-
tween the circuits of RAM- and EPROM-
based programmable melody generators
and as such we could integrate the com-
mon portion of the two circuits into a
single schematic/PCB design. However,
the circuit of a ROM-based programmable
melody generator is totally a new one.
The ROM, as stated earlier, is home-built
using discrete components, which can be
used for storage of 100 bits (100 notes).
The block diagram of the ROM-based
melody generator is shown in Fig. 16.
Note that the last block comprising
variable resistor array is identical to that
used in EPROM/RAM version (refer Fig.
3 in Part I of the article). The power-
supply circuit shown in Fig. 11 can also
be used for ROM-based melody genera-
tor. Thus PCB and component layouts
shown in Figs 7 and 9 can be used with-
out any modification in this system.
ROM-based circuit
The circuit diagram of ROM-based melody
generator is shown in Fig. 17. Here timer
NE 555 (IC1) is wired as an astable
multivibrator. The output pulses from IC1
are used as clock for decade counter
CD4017 (IC2). The ten sequential outputs
from IC2 are applied to npn BC547 tran-
sistors T1 through T10.
CONSTRUCTION
‘Stop-clock’ and ‘Reset’ functions) are to
be strapped (shorted) together for connec-
tion to the corresponding input points of
NA
ANJA the ‘variable-resistor array and tone os-
RUP
PARTS LIST
Semiconductors:
IC1 - NE555 timer
IC2, IC3 - CD4017 decade counter
IC4, IC5 - CD4069 hex inverters
T1-T10 - BC547 npn transistor
Similarly, the outputs from another T11-T110 - BC558 pnp transistor
similar decade counter IC3 are connected Resistors (¼-watt ±5% carbon, unless other-
to pnp BC558 transistors T11 through wise stated)
T110 via inverter gates N1 through N10 R1 - 10-kilo-ohm
R2 - 100-kilo-ohm
of IC3 and IC4 (CD4069). Each of these
R3 - 680-ohm
100 transistors (T11 through T110) R4 - 1-mega-ohm
provides one bit for one note. The out- R5 - 1-kilo-ohm
puts are taken from the collectors of R6 - 68-ohm
transistors and connected to the ‘variable- Capacitors:
resistor array and tone oscillator’ circuit. C1 - 2.2µF, 12V electrolytic
(Note: Collectors of transistors represent- C2, C3 - 0.01µ ceramic disc
ing identical notes are shorted together.) Miscellaneous:
As in the previous circuits of RAM- S1 - Push-to-off switch
*Parts List of tone oscillator and power sup-
and EPROM-based melody generators, ply is given in Part I of the article (published
here also ‘Stop-clock’ and ‘Reset’ signals in May issue).
are made available. You may program
any/all of the hundred transistors T11 cillator’ circuit, while the ‘Stop-clock’ and
through T110 for 28 notes as well as for ‘Reset’ lines are to be connected as shown
the ‘Stop-clock’ and ‘Reset’ functions. How- in Fig. 17.
ever, both ‘Stop-clock’ and ‘Reset’ func- We can have a maximum of 30 out-
put lines (28 for
the notes and two
for ‘Stop-clock’
and ‘Reset’ func-
tions) from the
100-transistor ar-
ray. Transistors
Fig. 16: Block diagram of ROM-based melody generator T1 through T10
are used to switch
tions are optional, depending upon the on Vcc to transistors T11 through T110.
number of tunes and number of notes.
For ‘Stop-clock’ function, the output from
a transistor is applied to inverter N11
Operation
whose output is connected to reset pin 4 Initially, when power is switched ‘on’ to
of IC1. Similarly, for ‘Reset’ function, the the circuit, IC2 and IC3 are in Reset con-
output from a transistor is applied to pins dition. So only pin 3 (Q0) of IC2 and IC3
15 of IC3 and IC4. will be at ‘high’ logic. These high outputs
The collectors of transistors pro- are applied to the base of transistor T1
grammed for each specific note (including and the input of inverter N1. As a result,
ELECTRONICS FOR YOU ❚  JUNE 2001

Fig. 17: Schematic diagram of ROM-based melody generator
transistor T1 is switched on and +5V Vcc
is available at the emitter of transistor
T1. This potential is extended to the emit-
ters of T11, T21, T31,… , T91 and T101.
Simultaneously, the output of inverter N1
will be at logic ‘0’, which is applied to the
bases of pnp transistors T11 through T20.
Since transistor T11 is the only tran-
sistor that has both Vcc at its emitter
and nearly 0V at its base simultaneously,
it gets forward biased and its collector is
pulled toward its emitter voltage (Vcc).
CONSTRUCTION
Thus initially, on powering the circuit,
transistor T11 is activated and its collec-
tor goes high.
The initial state lasts for a few
seconds and as soon as IC1 generates a
clock pulse (which is applied to the clock
pin of IC2), Q1 (pin 2) of IC2 goes ‘high’
and pin 3 goes ‘low’, while no change takes
place in IC3. Now transistor T2 is
switched on.
Since the base of transistor T12 is at
low potential, the positive voltage will be
ELECTRONICS FOR YOU ❚  JUNE 2001
available at its collector. Thus transistors
T11 through T20 will be switched on and
off sequentially with the arrival of each
new clock pulse.
At the beginning of tenth pulse, the
carry-output pulse from pin 12 of IC2 is
applied to clock pin 14 of IC3. Now pin 3
(Q0) of IC2 and pin 2 (Q1) of IC3 go ‘high’.
Therefore, transistors T21 through T30
are now switched ‘on’ and ‘off’ in a se-
quential fashion. In this way one out of
100 transistors is switched ‘on’ sequen-

Fig. 18: Actual-size, single-sided PCB layout for the circuit
tially to produce an output to drive the
‘resistor-array tone oscillator’ according to
the tune data. Thus when power is
switched on, the tune is produced.
PCB layout and assembly
The PCB design should ideally be double-
sided for such types of transistor arrays.
However to keep the cost down, we have
included only a single-sided PCB layout,
which is shown in Fig. 18 with its compo-
nent layout in Fig. 19.
CONSTRUCTION
First, assemble transistors T11
through T110. Solder the transistors, leav-
ing a length from the PCB. Now take a
thin, bare wire and connect the emitter
leads of transistors T11, T21... T91 and
T101 together from the components side.
Similarly connect emitters of other rows
of transistors. Suitable pads for the pur-
pose have been provided on the PCB.
Similarly the collectrors of transis-
tors T1 through T10 may be connected
together using bare wire from the com-
ponents side. Now assemble all the re-
ELECTRONICS FOR YOU ❚  JUNE 2001
maining components.
Programming
In this circuit, programming means hard
wiring. You should have a lot of patience
to do all the hard wiring. No hexadecimal
values are required. Before starting with
the wiring, label diodes D101 through
D128 of ‘variable resistor array oscillator’
PCB (Fig. 7 and 9 in Part 1) in terms of
their respective notes i.e. label D101 as
❚
PA❚, D102 as dha❚, ..., D128 as NI , and so
on.
Now starting from transistor T11 con-
nect the transistor outputs (refer PCB of
Fig. 18) to diodes D101 through D128 ac-
cording to the tune note that each tran-
sistor (T11 through T110) sequentially
represents. Extreme care should be taken
while wiring, because if any error occurs,
it will be very tedious to find out.
Let us consider the example of five
notes ‘SA RE— GA SA PA’. In this case
programming can be done as under:
Connect
T11àSAàD6
T12àREàD8
T13àNO connection, leave open (be-
cause the data is no sound)
T14àGAàD10
T15àSAàD6 (Again to D6)
T16àPAàD13
Reset. With this circuit a maximum of
100 notes are feasible. However if all notes
are not utilised, Reset is necessary after
the last utilised note. Because if the total
number of notes is less than 98, for ex-
ample, 86, then after 86th note there are 14
more bits to reach for an automatic reset
to occur. (The circuit automatically resets
itself after 100th bit.) So there is a big delay
for the tune to get repeated. To skip the
delay, we use Reset. For this, the output
from the next transistor after the last note
is connected to point marked ‘RESET’ on
PCB. When the pulse appears at pin 15 of
IC2 and IC3, the circuit resets.
Stop-clock. Stop-clock is used when
more than one tune is to be programmed.
If the clock is to be stopped, say, after the
1st tune, we use stop-clock. For this, the
 CONSTRUCTION

output from the

next transistor after
the last note of the
tune is connected to
the stop-clock point
in the PCB. Please
refer to flow charts
of Fig. 20 and 21,
Fig. 20: Flow chart which show
for repetitive playing
of 99 notes (single occurance of auto-
tune) matic reset and use
of stop-clock and re-
set functions.
Housing. There is a
lot of wiring in between
the ROM circuit of Fig.
17 and the resistor-array
oscillator. So the enclo-
sure must have enough
space for all the wires to
fit properly without get-
ting detached from the
PCB while installing.
[EFY note. To overcome
Fig. 21: Flow
this problem to some ex-
chart for tent, a 28-pin (16+12)
repetitive SIP connector (with pins
playing of a projecting towards both
number of sides of the PCB) may be
tunes
used. This will obviate
the need to run loose wires between ROM
PCB and variable-resistor array oscilla-
tor PCB. Wires originating from the col-
lectors of the transistor array may be con-
nected to one side of the connector on
ROM PCB itself and a ribbon cable with
28-pin SIP connector on both sides can
Fig. 19: Component layout for the PCB be used between the two PCBs.] ❏

ELECTRONICS FOR YOU ❚  JUNE 2001

 CONSTRUCTION

AUTO CONTROL FOR

3-PHASE MOTORS
EDI PARTS LIST
DWIV
S.C. Semiconductors:
IC1-IC3 - MCT2E optocoupler
IC4 - CD4027 J-K flip-flop
D. DINESH IC5, IC6 - NE555 timer
IC7, IC9, IC10 - CD4017 decade counter
IC8 - CD4060 14-stage counter

I
nduction motors widely used in work- with under-frequency cut-out. and oscillator
shops, irrigation pump sets, etc re- • Current sensing for single-phasing IC11 - 7805 5V regulator
quire a 3-phase supply. Normally, prevention. D1-D30 - 1N4007 rectifier diode
ZD1, ZD2 - 3.3V zener diode
these motors are connected to 3-phase • Current sensing for overload cut-
LED1-LED4 - Red LED
supply from electricity boards using ther- out.
Resistors (1/4W ± 5% carbon, unless speci-
mal bimetal relays and relay contactors. • Automatic starting/tripping. fied otherwise)
Thermal relays protect the motor from • Programmable timer with battery R1-R3 - 100-kilo-ohm, 0.5 watt
overload. Relay coils having hold-on con- backup to count the motor’s run time. R4-R6, R16,
tacts with push-to-‘on’ and push-to-‘off’ • Latching circuit to prevent the mo- R18-R23, R25,
switches are used for activating and de- tor from frequently starting and tripping. R30, R31, R38,
R47, R49 - 4.7-kilo-ohm
activating the relay contacts. • Easy operation with just two R7, R24 - 27-kilo-ohm
Single-phasing, line dropout, and re- switches for time set and reset. R8-R10 R17,
verse phasing are harmful for 3-phase mo- The phase-sequence detector protects R26, R29, R32,
tors. In the event of line dropout and single- the motor before starting, while the cur- R37, R39, R43,
R44, R46, R48,
phasing, the motor draws a heavy current rent-sensing circuit protects it during run- R51-R53 - 10-kilo-ohm
from the existing phases, and during phase ning. This double protection makes the R11, R28, R34 - 1-kilo-ohm
reversal the motor simply rotates in re- motor operation really safe. R12 - 220-kilo-ohm
verse direction. Further, an operator (at- R13, R41 - 1-mega-ohm
R14, R35, R36,
tendant) for switching ‘on’/‘off’ the motor
is always not possible, especially when the
Circuit description R45, R50 - 470-ohm
R15 - 470-ohm, 0.5 watt
motor has to be operated round the clock. The schematic circuit diagram of induc- R27 - 180-kilo-ohm
Also the protection provided by the ther- tion motor controller is shown in Fig. 1. R33 - 2.2-kilo-ohm
R40 - 22-kilo-ohm
mal relay in the starter assembly is inad- 3-Phase sequence checker. The volt-
R42 - 82-kilo-ohm
equate, since it involves some delay in ac-
age from each of the three phases is con- VR1 - 4.7-kilo-ohm preset
tivation. Thus some damage to the wind- nected to optocouplers IC1 through IC3 VR2 - 47-kilo-ohm preset
ings of the motor can take place, especially
via rectifier diodes D1 through D3. The Capacitors:
if overload conditions occur frequently. outputs from the optocouplers are half- C1-C3, C6,
The circuit presented here incorpo- wave rectified DC pulses with a phase dif- C13 - 0.1 ceramic disk
rates the following features to overcome ference of 120° (during the conduction pe- C4, C7, C11, C17- 100µF, 63V electrolytic
C5, C14-C16,
all the above-mentioned problems: riod of diodes), which are applied to a posi- C18, C19 - 10µF, 25V electrolytic
tive-edge-triggered, dual JK flip-flop IC4.
• Electronic sensing of phase sequence C8, C10, C12 - 47µF, 25V electrolytic
When the red phase rises, the output C9 - 1000µF, 63V electrolytic
TABLE I of IC1 goes from ‘low’ to ‘high’, resulting Miscellaneous:
Phase sequence Signal OK LED RL1 in clearing of both flip-flops FF1 and FF2 X1-X3 - Current-sensing trans-
Correct On On through 0.1µF capacitor C1. While the red formers
Incorrect Off Off X4 - 0-230V AC primary to
phase is still ‘high’, the yellow phase rises, 12V-0-12V, 500mA
resulting in the secondary transformer
TABLE II output of IC2 going S1 - ‘On’/‘off’ switch
Motor Core Core Primary Secondary ‘high’ and provid- S2 - SPDT switch
HP size area Max SWG Turns SWG Turns S3 - 7-way rotary switch
ing a clock pulse to - 1.5V X4 battery
(Max) amps
FF1. As a result, Q - Starter assembly
6 17 0.25 10 14 14 38 170
20 23 0.56 22 11 9 38 110 output of FF1 goes - Cabinet

ELECTRONICS FOR YOU ❚  JUNE 2001

 CONSTRUCTION

Fig. 1: Schematic diagram of auto control for 3-phase motor

‘low’ (since J1 input of FF1 is already the output of IC2 is already ‘high’, result- FF1 and FF2 are ‘low’, the phase sequence
‘high’ when the clock pulse arrives at ing in the output Q of FF2 going ‘low’. is correct and both diodes D28 and D29
CLK1 pin). Now, when the blue phase The above process repeats once dur- are in blocking mode. The base of tran-
rises, the output of IC3 goes ‘high’, while ing each 50Hz cycle. If Q outputs of both sistor T1 is pulled towards ground via re-

ELECTRONICS FOR YOU ❚  JUNE 2001


Fig. 2: Actual-size, single-sided PCB layout for the circuit
sistor R11 and transistor T1 starts con-
ducting. As a result, IC5 is triggered and
hence ‘sequence OK’ LED connected to
pin 3 of IC5 via resistor R14, glows.
IC5 is a popular 555 timer wired as a
retriggerable monoshot. Its time period
is set at 25 milliseconds (approx.). If the
monoshot is not retriggered within 25 mil-
liseconds, the ‘sequence OK’ signal goes
‘low’. The circuit operates smoothly at fre-
CONSTRUCTION
quencies up to 42 Hz.
If any of the phase fails, the phase
sequence is disturbed, resulting in the out-
put of IC5 going ‘low’ and ‘sequence OK’
LED goes ‘off’. The LED status in relation
to the phase sequence is shown in Table I.
The output of IC5 is also used for driving
relay RL1 via transistor T2 (SL100).
Normally-open (N/O) contacts of re-
lay RL1 are wired in series with ‘off’
ELECTRONICS FOR YOU ❚  JUNE 2001
switch of starter assembly as shown
in the Fig. 1. Thus when phase se-
quence is correct and the frequency is
above 42 Hz, the relay is in energised
state and it is feasible to switch on
the starter by momentary energisation
of relay RL2, whose N/O contacts are
wired in parallel with the ‘on’ switch
of starter assembly.
Auto-starter and current-sens-
ing circuit. As soon as the phase se-
quence is detected to be correct (as
explained in the previous section), the
output of IC5 goes ‘high’. This output,
via resistor R15, is used to reset IC7
and enable IC6, besides acting as a
clock for decade counter IC10.
IC6 is an NE555 timer wired in
astable mode to provide clock pulses
to decade counter CD4017 (IC7). Even-
tually, when Q8 output of CD4017
(IC7) goes ‘high’, relay RL2 energises
through transistor T9 (SL100). N/O
contacts of RL2 are connected across
‘on’ switch of starter assembly, as
stated earlier and the starter’s relay
coil energises. The next clock pulse to
IC7 deactivates relay RL2, but starter
remains in ‘on’ state due to hold-on
contact (the fourth contact of contactor
in starter assembly). When Q9 (pin 11)
of IC7 goes ‘high’, its CK pin 14 is
muted due to conduction of transistor
T8 (which pulls it to ground) to pre-
vent further counting. The Q9 output
of IC7 is also used in the motor ‘on’/
‘off’ timer circuit, explained later.
The supply to starter is connected
through primaries of three small cur-
rent transformers used for sensing
the load in each phase. These trans-
formers can be constructed using com-
mon EI laminations generally used for
power transformers. Core number 23 or
17 may be employed as per details given
in Table II.
The secondaries of these transformers
are connected to the current-sensing cir-
cuit wired around transistors T3 through
T5. If any phase goes ‘off’, it cuts off the
corresponding transistor and thereby pro-
vides forward bias to transistor T6.
The outputs of transistors T3 through

Fig. 3: Component layout for the PCB
T5 are wired-OR via diodes D15, D16, and
D17. Any excessive increase in load cur-
rent (overload) results in forward biasing
of transistor T7. The excess current limit
can be set with the help of preset VR1.
The conduction of transistors T6 and/
or T7 causes their common collector junc-
tions to be pulled low. This ‘low’ signal is
coupled to transistor T2 via diode D30.
As a result, relay RL1 deactivates to trip
CONSTRUCTION
the starter and thus stop the induction
motor. The above conditions are
summarised in Table III.
Motor on/off counter and latch.
Frequent start and stop operations sub-
ject the motor to lot of fatigue due to
heavy currents, which may damage the
motor. In this circuit, automatic restart-
ing of motor is limited to three attempts
for each power ‘on’, by using another de-
ELECTRONICS FOR YOU ❚  JUNE 2001
cade counter CD4017 (IC10). It moni-
tors each ‘on-off’ cycle of the motor by
advancing the count of decade counter
by one on every start.
The clock for IC10 is obtained from
the output of IC5 via resistor R15. This
point i.e. the junction of resistor R15
and diode D30 is also used as supply
point for transistors T6, T7, T12 and
T13 as also for reset pin of timer IC6.
On the third start, pin 7 (Q3) goes ‘high’
and transistor T13 gets forward biased.
As a result, CK pin 14 of IC10 is pulled
low to stop any further clock to the
decade counter, which thus gets latched
and LED3 glows to indicate the latched
state of the counter. Simultaneously,
this ‘low’ signal causes transistor T2 to
cut off and de-energise relay RL1. Thus
the motor cannot restart automatically
and only complete resumption of power
can reset the latch.
Motor on-off timer. A timer is pro-
vided to run the motor for a predeter-
mined time. It counts run time of the
motor and thereafter switches off the
motor automatically. The signal from
pin 11 (Q9) of IC7 is connected to the
base of transistor T11 via resistor R38
(as referred in ‘auto-starter and curre-
sensing circuit’). Thus the collector of
transistor T11 goes ‘low’ to activate the
oscillator circuit of CD4060 (IC8), while
the motor is running. Prior to that, the
oscillator circuit of CD4060 was inac-
tive because its pin 11 was at logic ‘1’,
being connected to +ve rails via resis-
tors R39, R40 and diode D22. The fre-
quency of oscillation is set by R-C net-
work comprising 47µF capacitor C8 and
resistor R42 in series with preset VR2.
A timing of either 30 minutes or 60
minutes can be selected with the help
of switch S2 for the output of ‘on’/‘off’ timer
to go from ‘low’ to ‘high’ state.The output
from the pole of switch S2 is connected to
the clock input of decade counter IC9. The
outputs of IC9 go ‘high’ sequentially after
30/60-minute time intervals, depending on
the selection made via switch S2. Thus
multiples of 30-/60-minute basic timing
can be selected with the help of 7-way
rotary switch S3. (The 7-way rotary switch
 CONSTRUCTION

power in standby mode TABLE III

and is powered by four Truth Table of Current Sensing Circuit
1.5V cells as standby Phase R Phase Y Phase B T6 T7 RL1
supply. A battery-low (ON) (ON) (ON) R.B. R.B. Energised
indicator is provided to (ON) (ON) (OFF) F.B. R.B. De-energised
warn the user about (ON) (OFF) (OFF) F.B. R.B. De-energised
(OFF) (OFF) (ON) F.B. R.B. De-energised
the low battery condi- (OFF) (ON) (OFF) F.B. R.B. De-energised
tion. (ON) (OFF) (ON) F.B. R.B. De-energised
Power supply. (OFF) (ON) (ON) F.B. R.B. De-energised
The normal DC power In case of overloading
supply for the circuit in any phase — X F.B. De-energised
is provided by a small Note: R.B. = Reverse bias; F.B. = Forward bias; X = Don’t care
step-down transformer
X4 connected between R (red) phase once again. Then after a delay of 15 sec-
and neutral, followed by rectifier and onds, relay RL2 should again energise for
filter capacitor. The unregulated volt- one second. Now short momentarily pin
age is used for operation of the relays, 14 of counter CD4017 (IC10) to ground
while the 5V regulated supply is used thrice. On the third touching, Q3 of IC10
Fig. 4: Layout of cabinet for mounting for the remaining circuit. will go ‘high’ and LED3 will glow, fol-
transformer relays and the PCB lowed by de-energisation of relay RL1. The
mains should be interrupted completely
may be substituted with decade thumb-
Construction and testing to reset IC10.
wheel switch, if desired.) An actual-size, single-sided PCB for the Current transformers X1 through X3,
The output available at the pole of motor controller circuit of Fig. 1 is shown step-down transformer X4, and relays RL1
rotary switch S3 goes ‘high’ after the se- in Fig. 2, with its component layout shown and RL2 may be mounted side by side in
lected duration to forward bias transistor in Fig. 3. It is recommended to use bases a compact box as shown in Fig. 4. The
T12, which, in turn, causes de- for ICs. PCB may be mounted over the transform-
energisation of relay RL1. Also, when Before connecting the circuit to starter ers and relays using insulated spacers.
the selected run time is over, the oscilla- assembly, a bench test is required for the Current transformers are to be connected
tor of IC8 (CD4060) gets inhibited because adjustment of timer. Apply 3-phase power before the starter relay contacts.
oscillator pin 11 of IC8 goes ‘high’ due to to the circuit. Observe pin 3 of IC5 Over-current adjustment can be done
(NE555), which should go only after connecting the load. Connect
‘high’, provided the sequence all the wires to the starter point and the
is correct. Else, interchange load. Keep wiper contact of VR1 towards
any two phase wires. As ‘se- ground side and switch on the 3-phase
quence OK’ signal at pin 3 of supply. Relay RL1 activates. After 5 sec-
IC5 goes ‘high’, relay RL1 onds, relay RL2 also activates and the
energises and IC6 (IC555) is motor starts running. Now slide the wiper
activated. As a result, relay of VR1 and mark the position just before
RL2 energises after a delay the motor trips. (Remember that such
of 15 seconds for one second. trips will be counted by latching counter.)
Now adjust preset VR2 Caution. Some parts of this circuit
such that 30-minute-duration contain live 3-phase voltages. So avoid
Fig. 5: Creation of virtual neutral from 3-phaes 3-wires
system pulse train (time period 60 touching the circuit with bare hands.
minutes) is available at pin Note. In the case of non-availability
the feedback from the pole of switch S3 14 of IC8 (CD4060). Flip switch S2 to 30- of neutral terminal, assembler a circuit
via resistor R43 and diode D23. LED1 minute position. Select the required run as shown in Fig. 5. Connect ‘N’ marked
glows to indicate that run time is over. time using rotary switch S3. On comple- wire (shown in Fig. 1) to two more trans-
To restart the motor, IC8 and IC9 can be tion of the selected run time, ‘time over’ formers X5 and X6 that are identical to
manually reset by closing and then open- LED should glow and the timer should X4. The secondaries of these transform-
ing switch S1. The timer may be bypassed stop. Relay RL1 should de-energise. ers (X5 and X6) are kept open, while the
by keeping switch S1 closed. After resetting the timer with the help secondary of X4 is connected to the power-
The timer section requires very low of switch S1, relay RL1 should energise supply circuit as shown in Fig. 1. ❏

ELECTRONICS FOR YOU ❚  JUNE 2001

July

2001
Circuit Ideas

2001

PC-BASED DIAL CLOCK-CUM-
ELECTRONIC ROULETTE
VIJAYA KUMAR P.
T
his hardware-cum-software project
is meant to control hardware
through software. The hardware
using LEDs to simulate both dial clock
and electronic roulette is rather simple.
Of the two 4-line-to-16-line decoders
used in the circuit, the first (IC1) drives
‘hour LEDs’ and the other (IC2) drives
‘minute LEDs’. These decoders are inter-
faced directly to the PC’s printer port pro-
vided on its backside.
Data output lines D0 to D3 (pins 2
through 5 of 25-pin ‘D’ connector) of the
CIRCUIT IDEAS
NA
ANJA
RUP
printer port are connected to four address
inputs of the decoder used for minute dis-
play, while data output lines D4 to D7
(pins 6 through 9) are connected to four
data inputs of the decoder used for hour
display.
Since the outputs of these decoders
are active-low, the positive terminals of
LEDs are made common. This obviates
the need to use additional inverters. In
accordance with 4-bit binary address at
inputs A through D of decoders, only one
of the 16 outputs at a time goes active-
ELECTRONICS FOR YOU ❚  JULY 2001
low to light the corresponding LED.
Since a dial clock requires only 12
LEDs, only 12 of 16 outputs of 74154 de-
coders are used in this circuit. Only the
minute decoder (IC2) is used for electronic
roulette.
The dial clock and electronic roulette
functions, which can be selected via the
software program, are explained below:
Dial clock. When dial clock is se-
lected, system time is displayed on the
LED panel. The hour-indicating LED
glows continuously, while minute-indicat-
ing LED blinks for each odd second (i.e.
1, 3, 5,.… , and so on). The clock incorpo-
rates hourly chime and alarm setting fea-
tures. Chime and alarm sound can be dis-
tinguished from the duration for which it
will sound.
Electronic roulette. Roulette is a
game of chance that basically comprises
a circular wheel divided into a number of
sectors that are numbered serially and a
pointer. There exists a relative motion be-
tween the pointer and the wheel. The ro-
tation is initiated by mechanical means.
The wheel is allowed to stop itself and
the number indicated by the pointer de-
cides the winner.
This game can also be arranged elec-
tronically by using sequential running
lights, which will simulate the rotating
wheel, and making them to stop at ran-
dom position. The chance of a number to
be winner is 1 out of 12 in the PC-based
electronic roulette explained here. The
software for dial clock and electronic rou-
lette is written in ‘C’ language.
For simulation of dial clock, the soft-
ware uses gettime () function to read time
from the computer, which is then stored
 CIRCUIT IDEAS

DialCLK.C
#include <stdio.h> { scanf(“%d” ,&scs);
#include <dos.h> ho=ho-12; Aclock(hrs,mns,scs);
#include <stdlib.h> } }
#define PORT 0x0378 if(ho==0) alarm(int beps) /*Function to produce beeping
main() { sound*/
{ int k=0; ho=12; {
clrscr(); } int i;
gotoxy(30,10); i=sc % 2; for(i=0;i<beps;i++)
printf(“1.(D)ial Clock\n”); mn=mn*i; /*Making minute LED to blink*/ {
gotoxy(30,12); mn=mn/5; sound(1500);
printf(“2.(R)un Electronic Roulette \n”); outportb(PORT,ho*16+mn); delay(100);
gotoxy(30,14); printf(“hour:min:sec = %02d:%02d:%02d\n”, nosound();
printf(“3.(E)xit\n”); ho,mnt,sc); delay(100);
do gotoxy(30,10); }
{ printf(“1.(G)oto MAIN MENU\n”); }
k=getch(); gotoxy(30,12); Roulet()/*Function for Roulette Wheel*/
k=toupper(k); printf(“2.(S)et Alaram\n”); {
if(k==‘D’) if(shor==ho&&smin==mnt&&ssec==sc) int i,k=0;
{ { clrscr();
Aclock(0,0,0); alarm(15); gotoxy(30,10);
} } printf(“1.Press any key to Reset\n”);
if(k==‘R’) if(mnt==0&&sc==0) gotoxy(30,12);
{ { printf(“2.(P)lay\n”);
Roulet(); alarm(1); gotoxy(30,14);
} } printf(“3.(G)oto MAIN MENU\n”);
} if(bioskey(1)) /* To check Whether any key is k=getch();
while(k!=‘E’); pressed */ k=toupper(k);
clrscr(); k=getch(); do
printf(“By Vijaya kumar.P,3rd Sem,E&C, k=toupper(k); {
K.V.G.C.E,Sullia\n”); if(k==‘S’) for(i=1;i<13;i++)/* To generate decimal
printf(“Dedicated to Father of Electricity { number from 1 to 12*/
Michael Faraday who is my favorite setala(); {
Scientist.\n”); } if(bioskey(1))
exit(0); } k=getch();
} while(k!=‘G’); k=toupper(k);
Aclock(int shor,int smin,int ssec) { if(k==’P’)
{ outportb(PORT,0); break;
int ho,sc,mn,mnt,k,i=0; main(); outportb(PORT,i);/*outputting binary
struct time tim; } equivalents of i
clrscr(); } through Data pins of LPT port*/
do setala() /*Function to set Alarm*/ delay(50);
{ { }
gettime(&tim); int hrs,mns,scs; }
gotoxy(30,8); clrscr(); while(k!=’G’);
ho=tim.ti_hour; printf(“Enter hour\n”); outportb(PORT,0);
mn=tim.ti_min; scanf(“%d” ,&hrs); main();
sc=tim.ti_sec; printf(“Enter Minute\n”); }
mnt=mn; scanf(“%d” ,&mns);
if(ho>12) printf(“Enter seconds\n”);

in a variable. This time is written into
the parallel-port as 8-bit binary number
by using outportb () function. To make
minute-indicating LED to blink, minute
variable is multiplied by (second % 2).
The multiplication result comes out to be
1 for odd seconds and 0 for even seconds.
i=sc%2;
mn=mn*i;
The binary equivalent of minute vari-
able is written into data pins D0 to D4 of
the parallel-port. Hour variable is multi-
plied by 16 to write the binary equivalent
of hour into data pins D5 to D7.
Outportb (0x0378,ho*16+mn);
Simulation of roulette wheel is quite
simple. The software uses a decimal num-
ber (1 through 13) generator whose bi-
nary equivalents are written into data
pins D0 to D4 of the parallel port using
outputb () function. The roulette can be
reset by initialising decimal number gen-
erator that simulates running lights.
The decimal number generator can be
stopped at random for play. The speed of
running can be adjusted by using delay ()
function. The delay time has to be se-
lected appropriately, as it should not be
either too low or too high. Keeping the
delay time very low is undesirable, since
it will cause continuous glowing of LEDs.
Similarly, a very high delay time is also
undesirable, since the player can stop the
wheel at his winning position.

ELECTRONICS FOR YOU ❚  JULY 2001


SIMPLE TELEPHONE
RING TONE GENERATOR
K. UDHAYA KUMARAN, VU3GTH
H
ere is a simple telephone ring
tone generator circuit designed
using only a few components. It
produces simulated telephone ring tone
and needs only DC voltage (4.5V DC to
12V DC). One may use this circuit in or-
dinary intercom or phone-type intercom.
The sound is quite loud when this circuit
is operated on +12V DC power supply.
However, the volume of ring sound is ad-
justable.
The commonly available 14-stage bi-
nary ripple counter with built-in oscilla-
CIRCUIT IDEAS
IL KU
MAR
SUN
tor (CMOS IC CD4060B) is used to gen-
erate three types of pulses, which are
available from pin 1 (O11), pin 3 (O13), and
pin 14 (O7), respectively. Preset VR1 is
adjusted to obtain 0.3125Hz pulses (1.6-
second ‘low’ followed by 1.6-second ‘high’)
at pin 3 of IC1. At the same time, pulses
available from pin 1 will be of 1.25 Hz
(0.4-second ‘low’, 0.4-second ‘high’) and 20
Hz at pin 14. The three output pins of
IC1 are connected to base terminals of
transistors T1, T2, and T3 through resis-
tors R1, R2, and R3, respectively.
Transistors T1 through T3 are cas-
ELECTRONICS FOR YOU ❚  JULY 2001
caded in such a way that the positive volt-
age available at the emitter of transistor
T1 is extended to the collector of transis-
tor T3 when the outputs of all the three
stages are low. As a result, transistors
T1 through T3 are forward biased for 0.4,
1.6, and 0.025 seconds, respectively and
reverse biased for similar durations.
Using a built-in oscillator-type piezo-
buzzer produces around 1kHz tone. In this
circuit, the piezo-buzzer is turned ‘on’ and
‘off’ at 20 Hz for ring tone sound by tran-
sistor T3. 20Hz pulses are available at
the collector of transistor T3 for 0.4-sec-
ond duration. After a time interval of 0.4
second, 20Hz
pulses become
again avail-
able for an-
other 0.4-sec-
ond duration.
This is fol-
lowed by two
seconds of no-
sound inter-
val. Thereaf-
ter the pulse
pattern re-
peats itself.
Refer the figure that indicates wave-
forms available at various points includ-
ing the collector of transistor T3. Preset
VR2 can be used for adjusting the ampli-
tude of the ring tone.

DUAL-INPUT HIGH-FIDELITY
AUDIO MIXER
PRASAD J.
T
he circuit described here is based
on the superior characteristics of
dual-gate MOSFET (metal-oxide
semiconductor field-effect transistor). It
exhibits a very high input impedance that
lends for good sensitivity and very less
loading of the input signal source. Low
cross-modulation characteristic leads to
minimal distortion of the output with re-
spect to the input signals. Also, the
MOSFET offers low feedback capacitance
and high transconductance. All these ad-
vantages make the MOSFET the most ef-
fective for high-quality mixer and con-
verter applications.
This dual-input audio frequency mixer
circuit employs a single dual-gate
MOSFET 3N200. One may, however, sub-
stitute it with any other dual-gate
MOSFET such as 3N187 and BF966. (It
is to be noted that BF966 is not gate-
protected and hence calls for suitable pre-
caution in handling it.)
The audio frequency (AF) input from
the first channel (CH1) is applied on
gate 1 (G1) of the MOSFET through 500-
kilo-ohm potentiometer VR1. The AF in-
put from the second channel (CH2) is ap-
plied on gate 2 (G2) of the MOSFET
through another 500-kilo-ohm potentiom-
eter VR2. Potentiometers VR1 and VR2
serve as gain controls for the mixer in-
CIRCUIT IDEAS
SUN
IL KU
MAR
puts.
Gate 1 receives the negative bias re-
sulting from the voltage developed by the
current passing through resistor R1 that
is in series with the source. Gate 2 re-
ceives the positive bias produced across
resistor R3 by the voltage divider formed
by resistors R3 and R4.
The mixed common output signal de-
veloped across drain load resistor R2 is
coupled to the output through capacitor
C5. This output can be, in turn, fed to
any audio amplifier system for further
amplification.
The input impedance at each signal
input is approximately 500 kilo-ohm,
which is determined largely by the resis-
tance of potentiometers VR1 and VR2.
ELECTRONICS FOR YOU ❚  JULY 2001
Higher input impedance may be obtained
by substituting higher-resistance potenti-
ometers, but this will lead to the pickup
of stray signals.
The current drain of this circuit at 6V
DC is less than 3 mA. The open-circuit
voltage gain is 10 for each channel. The
maximum amplitude of input signals at
gates G1 and G2 is 0.1V RMS. Signals of
higher amplitudes are reduced by the ad-
justment of potentiometers VR1 and VR2,
hence evading the output signal peak-clip-
ping. The corresponding output signal am-
plitude is 1V RMS.
The entire circuit can be built on a
general-purpose PCB or veroboard. The
complete assembly
is shielded using a
metal container.
The two input jacks
should be fixed on
the opposite sides of
the container
against the output
jack.
This simple cir-
cuit can be utilised
for various combina-
tions of devices at
the input end. A few
examples are two microphones, two au-
dio players, or one audio player and one
microphone, etc.
Note. Adequate precautions should be
taken to prevent the destruction of
MOSFET due to static electricity. The use
of a grounded tip for the soldering iron is
recommended.

ANTI-THEFT SECURITY
FOR CAR AUDIOS
T.K. HAREENDRAN
T
his small circuit, based on popu-
lar CMOS NAND chip CD4093,
can be effectively used for protect-
ing your expensive car audio system
against theft.
When 12V DC from the car battery is
applied to the gadget (as indicated by
LED1) through switch S1, the circuit goes
into standby mode. LED inside
optocoupler IC1 is lit as its cathode ter-
minal is grounded via the car audio (am-
plifier) body. As a result, the output at
pin 3 of gate N1 goes low and disables
the rest of the circuit.
CIRCUIT IDEAS
S.C.
DWIV
EDI
Whenever an attempt is made to re-
move the car audio from its mounting by
cutting its connecting wires, the
optocoupler immediately turns off, as its
LED cathode terminal is hanging. As a
result, the oscillator circuit built around
gates N2 and N3 is enabled and it con-
trols the ‘on’/‘off’ timings of the relay via
transistor T2. (Relay contacts can be used
to energise an emergency beeper, indica-
tor, car horns, etc, as desired.)
Different values of capacitor C2 give
different ‘on’/‘off’ timings for relay RL1 to
be ‘on’/‘off’. With 100µF we get approxi-
ELECTRONICS FOR YOU ❚  JULY 2001
mately 5 seconds as ‘on’ and 5 seconds as
‘off’ time.
Gate N4, with its associated compo-
nents, forms a self-testing circuit. Nor-
mally, both of its inputs are in ‘high’ state.
However, when one switches off the igni-
tion key, the supply to the car audio is
also disconnected. Thus the output of gate
N4 jumps to a ‘high’ state and it provides
a differentiated short pulse to forward bias
transistor T1 for a short duration. (The
combination of capacitor C1 and resistor
R5 acts as the differentiating circuit.)
As a result, buzzer in the collector
terminal of T1 beeps for a short duration
to announce that
the security cir-
cuit is intact.
This ‘on’ period
of buzzer can be
varied by chang-
ing the values of
capacitor C1
and/or resistor
R5.
After con-
struction, fix the
LED and buzzer
in dashboard as
per your re-
quirement and
hide switch S1
in a suitable location. Then connect lead
A to the body of car stereo (not to the
body of vehicle) and lead B to its positive
lead terminal. Take power supply for the
circuit from the car battery directly.
Caution. This design is meant for car
audios with negative ground only.
 CIRCUIT IDEAS

UNIPOLAR/BIPOLAR TRIANGULAR
AND BIPOLAR SQUARE S.C. DWIV
EDI

WAVE GENERATOR
YOGESH KATARIA

T
he circuit given here is capable of ing double the frequency in the first
generating unipolar and bipolar case.
triangular waves as well as bipo- Op-amp 301 acting as a com-
lar square waves. In unipolar mode, the parator produces bipolar square
output frequency is double that of wave with output swinging between
bipolar mode (using identical component +Vcc and –V EE. The square wave
values). output is fed to op-amp 741 that is
When switch S1 is closed, the circuit configured as an integrator to pro-
generates bipolar triangular as well duce a triangular waveform.
as bipolar square waves, and when switch Figs 2 and 3 show the wave-
S1 is open, it generates unipolar triangu- forms with switch S1 in closed and
lar and bipolar square waves—both hav- open positions, respectively, using
0.047µF ca-
pacitor C and
in-circuit
value of preset
VR1 as 28
kilo-ohm. The
circuit is ca-
pable of work-
ing on a few
hertz to
around 250
kHz.

ELECTRONICS FOR YOU ❚  JULY 2001

Construction

2001
 CONSTRUCTION

TELEPHONE REMOTE IL KU
MAR
the relays, press ‘*’ and then press key
for digit 8. A musical note is heard, which
indicates that all the relays have been
SUN

CONTROL
switched ‘off’. Keep the handset on cradle.

The circuit
At the remote telephone end, the ringing
JUNOMON ABRAHAM signal is detected by a high-input-imped-

Fig. 1: Schematic diagram of the telephone remote control

T
elephone remote control implies number of the
control of devices at a remote remote tele-
location via a circuit interfaced to phone to
the remote telephone line/device by dial- which the cir-
ing specific DTMF (dual-tone multi-fre- cuit is con-
quency) digits from a local telephone. The nected. In a
telephone remote control system described short while
here has the following features: you will hear
1. It can control multiple channels/ a musical
relays. note indicat-
2. It provides you feedback when the ing that the
circuit is in energised state and also sends circuit con-
an acknowledgement indicating action nected to the
w.r.t. the switching ‘on’ of each requested remote tele-
relay and switching ‘off’ of all relays (to- phone is ac-
gether). tive.
3. It can selectively switch ‘on’ any one 2. Now if
or more relays one after the other and you want to
switch ‘off’ all relays simultaneously. switch ‘on’ a
particular re-
lay/device,
Operation press ‘*’ but-
Instead of straightway proceeding with ton on the
the circuit description, we shall start with telephone
the operation as this would help us in keypad fol-
understanding the circuit better. The op- lowed by any
eration is as follows: one of digits 1
1. From the local telephone, dial the to 7 corre-
sponding to
TABLE I(A) the device/re-
Input Output lay number
A2 A1 A0 Qn = addressed that you de-
L L L Q0 sire to switch
L L H Q1 ‘on’. The
L H L Q2
L H H Q3 switching ‘on’
H L L Q4 of the relay
H L H Q5 will be ac-
H H L Q6 knowledged/
H H H Q7
indicated by a
TABLE I(B) musical note.
WR R Q Q Now you may
Addressed un-addressed keep the
L L = DATA hold handset on
L H = DATA L the cradle.
H L hold hold 3. If you
H H L L
want to
H = High; L = Low switch ‘off’

ELECTRONICS FOR YOU ❚  JULY 2001


Fig. 2: Actualsize, single-sided PCB for the circuit
Fig. 3: Component layout for the PCB
ance op-amp CA3140E that is wired as a
comparator. Since this op-amp output is
CONSTRUCTION
open-collector type, the output pin has
been pulled towards Vcc via 10-kilo-ohm
ELECTRONICS FOR YOU ❚  JULY 2001
resistor R21. IC2 (NE556) com-
prises two timers (NE555 type) that
have been configured as
monostables.
When a ring is detected by IC1,
its output triggers one of the tim-
ers in IC 556. The output of the
timer after inversion by one of the
NAND gates of IC3 (CD4011), en-
ables IC4 (CD4060) by taking its
reset pin 12 ‘low’. (IC4 is an oscil-
lator-cum-14-bit binary counter.) As
a result, IC4 starts counting when
the ring signal strikes the input of
the circuit.
After some time, decided by the
setting of preset VR3, Q12 output
of IC4 goes ‘high’. This output
coupled to pin 8 of a NAND gate
inside IC3 will enable it. The de-
tected ring signal (if the ring sig-
nal is still persisting) applied to pin
9 of the same NAND gate (after
inversion by another NAND gate)
will pass through it to trigger the
second monostable inside IC2
(NE556) as well as IC5 (NE555),
which is again wired as a
monostable. This arrangement
avoids the circuit from being trig-
gered by any transients or false ring
signals on the telephone line.
The output of the second
monostable of IC2, available at its
pin 9, drives transistor T2 and
shunts the telephone line with 220-
ohm resistor (R20). As a result, the
telephone line voltage drops to
around 10 to 12 volts. This is
equivalent to the lifting of the tele-
phone handset of the remote tele-
phone. As mentioned earlier, both
IC5 and the second monostable of
IC2 are triggered simultaneously.
The output of monostable IC5 starts
melody generator IC6 (UM66) and
the musical note obtained from it
is coupled to the telephone line.
This informs the caller that the re-
mote circuit is in energised state.
As the remote circuit is in energised
condition, the next step for the operator
 CONSTRUCTION

PARTS LIST at local telephone is to press the ‘*’ but-

Semiconductors: ton, which makes the local telephone to
IC1 - CA3140E op-amp operate in the tone-dialing mode. The dig-
IC2 - NE556 dual timer its that are pressed after pressing the ‘*’
IC3 - CD4011 quad NAND gate button are converted to DTMF tones.
IC4 - CD4060 14-stage counter/
oscillator
The tone is decoded by IC7 and its
IC5 - NE555 timer three LSBs (covering binary equivalent
IC6 - UM66 melody generator of decimal digits 0 through 7) are con-
IC7 - CM8870 DTMF-decoder nected to the address inputs, while the
IC8 - CD4099 8-bit addressable MSB line is connected to reset pin 2 of
latch
IC9 - 7805 regulator +5V IC8 (CD4099, an 8-bit addressable latch).
T1 - BC548 npn transistor When a valid DTMF tone is detected at
T2-T9 - BC547 npn transistor (only the input of IC7, its pin 15 goes ‘high’ to
T2 and T6 shown) enable IC8 after inversion by NAND gate
LED1, LED2 - Green LED
LED3 - Yellow LED
of IC2. At the same time, it triggers IC5
LED4 - Red LED for informing the caller that his key-press
D1, D2 - 1N4148 switching diode is accepted.
D3-D10 - 1N4007 rectifier diode (only Numbers 1 to 7 on the local keypad
D3 and D4 shown) cause latching of the corresponding re-
Resistors (all ¼-watt, ±5% carbon, unless lays, while number 8 causes reset opera-
otherwise stated)
tion, which means that we can switch ‘on’
R1, R16, R17 - 150-kilo-ohm
R2, R21 - 10-kilo-ohm seven relays independently one by one and
R3 - 33-kilo-ohm switch ‘off’ all relays simultaneously by
R4 - 680-kilo-ohm pressing number 8. The output of IC8
R5 - 560-ohm drives the relays via the relay driver tran-
R6, R10 - 22-kilo-ohm
sistor. Truth tables I(A) and I(B) of
R7 - 1-mega-ohm
R8, R15 - 390-ohm CD4099 indicate relay operation.
R9, R12 - 15-kilo-ohm
R11 - 270-ohm
R13, R14 - 3.3k-kilo-ohm Alignment
R18 - 330-kilo-ohm
R19, R22-R27 - 4.7-kilo-ohm (R22-R27 not 1. Connect the circuit to the telephone
shown in the figure) line.
R20 - 220-ohm 2. Adjust preset VR1 so that the ring-
VR1 - 10-kilo-ohm preset ing pulse causes LED1 to flicker. For bet-
VR2 - 1-mega-ohm preset
ter performance, set the voltage at pin 3
VR3 - 220-kilo-ohm preset
VR4 - 470-kilo-ohm preset of IC1 at approximately 2 volts.
Capacitor: 3. The time required to activate/
C1 - 0.22µF ceramic disk energise the circuit is adjusted by preset
C2 - 220µF, 10V electrolytic VR3 with the help of LED2.
C3 - 100µF, 10V electrolytic 4. The time available for remote
C4, C5, C8 - 0.01µF ceramic disk switching action can be set by preset VR2
C6, C11, C12 - 0.1µF ceramic disk
C7 - 10µF, 10V electrolytic with the help of LED4. Indirectly, the set-
C9 - 0.02µF ceramic disk ting of preset VR2 determines the charge
C10 - 0.47µF, 100V polyester that will have to be paid to the telecom
Miscellaneous: department.
XTAL - 3.58MHz crystal 5. The period of the musical note can
RL1-RL7 - 6V, 150-ohm 1C/O relay be controlled by the adjustment of VR4
(only RL4 shown) with the help of LED3. ❏

ELECTRONICS FOR YOU ❚  JULY 2001

 C O N S T R U C T I O N

MICROCONTROLLER-BASED PARTS LIST

SCHOOL TIMER NA
Semiconductors:
IC1 - 68HC705JIACP
microcontroller
ANJA IC2 - CD4532 8-bit priority
RUP encoder
U.B. MUJUMDAR IC3 - 74LS138 3-line to 8-line
decoder
IC4 - 74LS47 BCD-to-7-segment
decoder/driver

T
he basic requirements of a real- T1-T3 - BC547/BC147 npn
transistor
time programmable timer gener- T4-T7 - 2N2907 pnp transistor
ally used in schools and colleges D1- D7 - 1N4007 diode
for sounding the bell on time are: ZD1 - 5.6V, 0.5watt zener
• Precise time base for time keep- Resistors (¼-watt, ±5% carbon, unless stated
ing. otherwise)
• Read/write memory for storing the R1 - 210-ohm, 0.5 watt
R2 - 27-ohm
bell timings. R3, R12-R14,
• LCD or LED display for display- R24-R27 - 1-kilo-ohm
ing real time as well as other data to R4-R8 - 100-kilo-ohm
make the instrument user-friendly. Fig. 1: MC68HC705J1A pin assignment R9 -R11,
• Keys for data entry. R23,R29 - 10-kilo-ohm
R15-R22 - 47-ohm
• Electromechanical relay to oper- This provides the timing reference for R28 - 10-mega-ohm
ate the bell. timer functions. Capacitors:
We are describing here a sophisti- The programmable timer status and C1 - 350µF, 25V electrolytic
cated, yet economical, school timer control register (TSCR) is used for de- C2, C3 - 1µF, 16V electrolytic
based on Motorola’s 20-pin ciding the interrupt rate. It can be pro- C4, C5 - 27pF ceramic disk
C6 - 0.1µF ceramic disk
MC68HC705J1A microcontroller. grammed to give interrupts after every
16,384, 3,2768, 65,536, or 131,072 clock Miscellaneous:
S1-S5 - Push-to-on switch (key)
cycles. In Table I, the control word is
Description set to provide the interrupts after ev-
S6 - On/off switch
PZ1 - Piezo buzzer
The pin assignments and main features ery 16,384 cycles. For a 32,768MHz RL1 - Relay 12V, 300-ohm, 1C/O
of the microcontroller are shown in crystal, the interrupt period will XTAL - 3.2768MHz AT-cut crystal
X1 - 230V AC primary to 12V-
Fig.1 and the Box, respectively. The be 10 ms. Thus, timer interrupts will
0-12V, 500mA secondary
complete system is divided into four be generated after every 10 ms (100 transformer
sections, namely, the time keeping sec- Hz). That is, 100 interrupts will make DIS.1-DIS.4 - LTS542 common-anode
tion, the input section (keyboard), the 1 second. display
output (display, indicators, and relay Now time-keeping becomes very - 4 x 1.2V Ni-Cd cells
driving) section, and power supply and simple. As we are having a precise
battery backup. 1-second time count, a real-time clock
can be easily built. microcontroller is driven by AT-cut par-
The time-keeping section. Accu-
allel resonant crystal oscillator that is
rate time-keeping depends on the The MC68HC705J1A has a 64 byte
expected to provide a very stable clock.
accuracy of time base used for driving RAM that is used for data storage. Real
A 3.2768MHz crystal provides a time
the microcontroller. In this project, the time (in terms of seconds, minutes,
base to the controller. The frequency
Main features of MC68H705JIA (fosc) of the oscillator is internally di-
vided by 2 to get the operating fre-
• 14 bidirectional input/output (I/O) lines.
quency (fop). This high-frequency clock
(All the bidirectional port pins are programmable as inputs or outputs.)
• 10mA sink capability on four I/O pins (PA0-PA3). source is used to control the sequenc-
• 1,240 bytes of OTPROM, including eight bytes for user vectors. ing of CPU instructions.
• 64 bytes of user RAM. Timer. The basic function of a timer
• Memory-mapped I/O registers. is the measurement or generation
• Fully static operation with no minimum clock speed.
of time-dependant events. Timers usu-
• Power-saving stop, halt, wait, and data-retention modes.
• Illegal address reset. ally measure time relative to the inter-
• A wide supply voltage range from – 0.3 to 7 volts. nal clock of the microcontroller. The
• Up to 4.0MHz internal operating frequency at 5 volts. MC68HC705J1A has a 15-stage ripple
• 15-stage multifunction timer, consisting of an 8-bit timer with 7-bit pre-scaler. counter preceeded by a pre-scaler that
• On-chip oscillator connections for crystal, ceramic resonator, and external clock.
divides the internal clock signal by 4.

ELECTRONICS FOR YOU ❚  JULY 2001

 C O N S T R U C T I O N

hours, days of a month, and months)

is stored in this RAM. Thus an accu-
rate real-time clock is generated.
The input section. For setting the
real-time clock and storing operating
times, the timer requires to be pro-
grammed externally. Data is fed us-
ing the keyboard.
Press-to-on type keys are inter-
faced to the microcontroller using an
8-bit priority encoder CD4532. This en-
coder detects the key-press operation
and generates the equivalent 3-bit bi-
nary data. Its truth table is shown in
Table II. The priority encoder is in-
terfaced to port A of the
microcontroller.
Various keys used in the timer,
along with their functions, are de-
scribed below:
Time (4): For setting real time in
minutes and hours.
Bell (5): For setting the bell’s op-
erating timings.
Digit Advance (6): Data setting is
done digitwise (hour’s digit followed
by minute’s digit). The Digit Advance
key shifts the decimal point to the
right.
Store (7): For storing the data (real
time or bell time).
Fig. 2: Schematic diagram of the microcontroller-based school timer

Delete (3): For deleting a particu-

lar bell timing.
Here, the figures within parenthe-
ses indicate the decimal equivalents
of 3-bit binary data from the keyboard.
Set and run modes. Data setting
is possible only in set mode. Set mode
or run mode can be selected by toggle
switch S6. By using a lock switch for
S6, the timer can be protected from
unauthorised data entry/storage.
In run mode if you press ‘Bell’ key
once, the display shows the bell’s vari-
ous operating timings one after the
other, in the same order in which
these had been previously stored. In
case you want to discontinue seeing
all the bell timings, you may press
‘Time’ key at any stage to revert back
to the display of real time.
The output section. Seven-seg-

ELECTRONICS FOR YOU ❚  JULY 2001

 C O N S T R U C T I O N

Power supply
and battery backup.
The microcontroller
and the associated IC
packages require a
5V DC supply, while
the relay and the
buzzer require 12V
DC supply. A simple
rectifier along with
zener diode-regulated
power supply is used.
Fig. 3: Power supply circuit for the school timer The microcontroller is
fed through a bat-
ment displays are used for data dis- tery-backed power supply, so that in
play. As LEDs are brighter, these have the case of power failure the function-
been used in the system. There are two ing of the controller’s timer section is
techniques for driving the displays: (i) not affected. During power failure the
driving each display using a separate timer is taken to ‘low power’ mode
driver (like 74LS47 or CD4511) and (ii) (called ‘wait’ mode). In this mode the
using multiplexed displays. controller draws a very small current.
The first technique works well, but So small Ni-Cd batteries can provide a
practically it has two problems: it uses good backup.
a large number of IC packages and con- A simple diode-resistance (27-ohm,
sumes a fairly large amount of current. 1/4-watt) charger maintains the charge
By using multiplexed display both the of the battery at proper charging rate.
problems can be solved. In multiplex-
ing, only one input is displayed at any
given instant. But if you chop or alter
Software
inputs fast enough, your eyes see the Motorola offers Integrated Development
result as a continuous display. With Environment (IDE) software for pro-
LEDs, only one digit is lighted up at a gramming its microcontroller and com-
time. This saves a lot of power and plete development of the system.
also components, making the system The development board comes with
economical. Editor, Assembler, and Programmer
Generally, displays are refreshed at software to support Motorola’s device
a frequency of 50 to 150 Hz. Here, dis- programmer and software simulator.
plays are refreshed at a frequency of The ICS05JW in-circuit simulator
100 Hz (after every 10 ms). The dis- along with development board (pod)
play-refreshing program is an interrupt forms a complete simulator and
service routine program. BCD-to-7-seg- non-real-time I/O emulator for simu-
ment decoder/driver 74LS47, along with lating, programming, and debugging
transistor 2N2907, and 3-line-to-8-line code for a MC68HC705J1A/KJ1 family
decoder 74LS138 are used for driving device.
common-anode displays. When you connect the pod to your
In multiplexed display, the current host computer and target hardware,
through the segments is doubled to you can use the actual inputs and
increase the display’s brightness. outputs of the target system during
74LS47 is rated for sinking a current simulation of the code. You can
of up to 24 mA. As the current persists also use the ISC05JW software to edit
for a very small time in multiplexed and assemble the code in standalone
display, it is peaky and can be as high mode, without input/output to/from pod.
as 40 mA per segment. The pod (MC68HC705J1CS) can be in-
The decimal point is controlled terfaced to any Windows 3.x- or Win-
individually by transistor BC547, dows 95-based IBM computer using se-
as 74LS47 does not support the deci- rial port.
mal point. PA0 and PA1 bits of port The software for the timer has been
A are used for controlling the electro- so developed that the system becomes
mechanical relay and buzzer, respec- as user-friendly as possible. The main
tively. constraint is read/write memory (RAM)

ELECTRONICS FOR YOU ❚  JULY 2001

 C O N S T R U C T I O N

TABLE I divided into the following modules:

Timer Status and Control Register (TSCR) Keyboard. When a key is pressed,
CD4532 sends the corresponding data.
Bit 7 6 5 4 3 2 1 0
After reading the data, the controller
Signal TOF RTIF TOIE RTIE TOFR RTIFR RTI RTO decides on the action. ‘Set/ Run’ key
Reset 0 0 0 0 0 0 1 1 (S6) is connected to port PA4.
TOF: Timer overflow flag RTIF: Real-time interrupt flag
RTIE: Real-time interrupt enable RTI and RTO: Real-time interrupt select bit.
Bell. This part of the program is
used for displaying the bell operating
RTI RTO Interrupt period
0 0 fop ÷ 214 For 3.2768MHz crystal
timings stored in the RAM. The oper-
0 1 fop ÷ 215 Frequency of operation (fop) ating timings are displayed one by one
1 0 fop ÷ 216 = 3.2768x106/2 = 1.638x106MHz with a delay of 5 seconds between two
1 1 fop ÷ 217 For RTI=RTO=0 consecutive timings.
Interrupt period = 10ms (100Hz) Set. The real time and bell timings
are stored using this part of the soft-
The software rou- ware. Data is entered digitwise; for ex-
tines for the timer, ample, 08:30 a.m. will be stored as 0,
along with their As- followed by 8, followed by 3, and finally
sembly language 0. Data is stored in 24-hour format.
codes, are listed in a Data fed from the keyboard is con-
folder. (Note: This verted into equivalent hex and stored
folder, containing in RAM. Any particular operating tim-
source code (.asm) and ing can be deleted from the memory
listing file (.lst) will using ‘Delete’ key, provided the timing
form part of the EFY- is already stored in the memory.
CD provided with the Run. Here the real time is com-
August issue. As files pared with bell operating time. If the
are quite large, it is two match, the relay is operated.
not feasible to include DataCon. This part of the software
them here.) Basically, is used for finding out the decimal
the following func- equivalent of hex data. The
tions are performed microcontroller manipulates the hex
by the software pro- data and converts it into BCD format
gram: for display.
1. Initialisation of Timer. The timer of the
ports and the timer. microcontroller is initialised to give an
2. Reading of key- interrupt after every 10 ms. A real-
pressed data. time clock is generated using the inter-
3. Storing of real rupt. Also the display is refreshed dur-
time and bell timings. ing the interrupt service routine.
4. Comparison of For real-time systems battery
real time and bell backup is very essential, because power
time. If the two failure affects the time keeping. In in-
match, the bell rings. terrupt service routine, the availability
5. Display of data. of power supply is checked. If the power
6. Time-keeping. is available, displays are refreshed and
Fig. 4: Actual-size single-sided PCB for the circuits in Figs 1 and 2 For a user-friendly the timer operates normally. However,
system, the associated during the power-failure period, dis-
space. As mentioned earlier, the software is required to perform many plays are off and system is taken to
microcontroller has only 64 byte RAM. data manipulation tricks and internal ‘low power’ mode. In this mode only
About twenty bell operating timings are branching. The operation and logic can the timer part of the microcontroller
required to be stored. So the efficient be understood from the Assembly lan- remains activated while operations of
use of RAM becomes essential. guage listings. The software is mainly all other peripherals are suspended.

ELECTRONICS FOR YOU ❚  JULY 2001

 C O N S T R U C T I O N

This considerably reduces the power

TABLE II
consumption. When the supply gets re-
Truth Table for Priority Encoder CD4532
stored, the controller starts operating
in normal fashion. Keys E1 D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
Store 1 1 X X X X X X X 1 1 1
Digit Adv. 1 0 1 X X X X X X 1 1 0
Operating procedure Bell 1 0 0 1 X X X X X 1 0 1
When the power is switched on, the Time 1 0 0 0 1 X X X X 1 0 0
display shows 12.00. Two settings are Delete 1 0 0 0 0 1 X X X 0 1 1
required in the timer: (a) setting of real
time and (b) setting of bell operating pressing of ‘Time’ key will increment the previously stored timings is deleted.
timings. For setting real-time clock the data, like 0.000, 1.000, 2.000, and Deletion of bell operating tim-
‘Time’ key is used, while for setting thereafter it will repeat 0.000, etc. ings. For deleting a particular timing,
bell timings ‘Bell’ key is used. To select the digit, press ‘Digit Ad- first store this timing using the steps
Storing of real time. To store real vance’. This stores the present digit given above. Then press ‘Delete’ key to
time, say, 05:35 p.m., flip ‘Run’/’Set’ and the next digit is selected as indi- delete the specific data from the memory.
key (S6) to set mode. The display will cated by the decimal pointer. Data is Display of real time. If ‘Run’/’Set’
show ‘0.000’. Press ‘Time’ key. Further stored in 24-hour format. The time to key is taken to run mode, real time
be stored is 17.35, of will be displayed.
which the first digit Checking of bell operating times.
will be 1.000. The For checking the bell operating times,
second, third, and press bell key in ‘Run’ mode only. The
fourth digits can be stored bell operating timings will be dis-
stored in similar played one by one with a delay of 5
fashion. After the seconds between two consecutive tim-
fourth digit, press ings.
‘Digit Advance’ key
once more. The dis-
play will show 1735
Programming
(with no decimal). There are two ways to program the
Now press ‘Store’ to EPROM/OTPROM (one-time program-
store the data. mable ROM):
Storing of bell 1. Manipulate the control bits in the
timings. The proce- EPROM programming register to pro-
dure to store bell op- gram the EPROM/OTPROM on a byte-
erating timings is by-byte basis.
similar to that of set- 2. Program the EPROM/OTPROM
ting real time. The with Motorola’s MC68HC705J in-circuit
only difference is that simulator.
here data is changed The author has used the second
by ‘Bell’ key in place method for programming the OTPROM.
of ‘Time’ key. Any (EFY note. Readers who wish to
number of bell tim- acquire a Pod for 705KJ1/J1A
ings (<20) can be microcontrollers, along with the re-
stored in the same quired software, may contact Vinay
fashion. If the num- Chaddha at gvc@vsnl.com.)
ber of bell operating An actual-size, single-sided PCB
timings exceeds 20, for the circuits in Figs 2 and 3 is shown
the timer will not ac- in Fig. 4, with its component layout
cept any new bell shown in Fig. 5.
Fig. 5: Component layout for the PCB timing until one of ❏

ELECTRONICS FOR YOU ❚  JULY 2001

August

2001
Circuit Ideas

2001

LONG-RANGE CORDLESS
BURGLAR ALARM
T.K. HAREENDRAN
T
his long-range cordless burglar
alarm circuit makes use of a
cordless telephone (CLT) unit with
paging facility and a few low-cost discrete
components. The circuit is so simple that
even a novice can easily construct it with-
out any difficulty.
When the ‘page’ button on a CLT is
pressed and held in that position, the
handset starts beeping to indicate that
somebody is calling. This function is used
here to build the gadget. The system con-
sists of three sub-assemblies:
1. Wireless beeper. The handset of
the CLT.
2. Infrared transmitter. A number
of IR transmitter circuits based on the
Fig. 1
Fig. 2
CIRCUIT IDEAS
EDI
.C. DWIV
S
well-known 555 chip have been published
earlier in EFY. Just select one circuit with
a modulating frequency of 36 to 38 kHz
and assemble it on a veroboard. After that,
enclose it in a proper cabinet. (EFY note.
A typical IR transmitter circuit used dur-
ing testing is shown in Fig. 1.)
3. Infrared receiver-cum-control
unit. The circuit diagram of this unit is
shown in Fig. 2. Front end of this block is
Sharp’s GP1U561X integrated infrared re-
ceiver module (or TK1836/
TSOP1836 from Temic/ Fig. 3
Telefunken, etc). This mod-
ule can demodulate 36kHz
modulated IR beam to pro-
duce an active-similar ‘low’
output. You may also use
any other module, provided
it has an active-‘low’ output.
The modulated IR beam
from the transmitter is re-
ceived by the receiver mod-
ule and its output at pin 2
goes ‘low’. The rest of the cir-
cuit is in sleep mode as it
does not get power for its op-
eration. The SCR here plays
ELECTRONICS FOR YOU ❚  AUGUST 2001
the role of an electronic switch.
When the infrared beam is inter-
rupted, the output of the receiver module
goes ‘high’ to apply a forward bias to the
base of transistor T1. As a result, the gate
of SCR gets sufficient forward bias to con-
duct (and latch). The astable multivibrator
built around IC1 starts working to con-
trol the ‘on’/‘off’ relay timings. Diode D1
prevents the relay from latching and di-
ode D2 works as a free-wheeling diode.
Normally open (N/O) contacts of the
relay are used to close the ‘page’ button
contacts until the circuit is reset by press-
ing push-to-off switch S1 (N/C type). One
may replace switch S1 with a key-lock
switch to avoid its unauthorised opera-
tion. The astable circuit helps the hand-
set user to distinguish between a normal
paging call and an intrusion warning
alarm.
After construction, fix the trans-
mitter and receiver modules at oppo-
site sides in the door frame as shown
in Fig. 3. Carefully open the CLT and
solder two wires to the ‘page’ button
terminals with their free ends con-
nected to the relay contacts (N/O). Now
your cordless burglar alarm with a
wireless monitoring range of about 500
metres (actual range is based on the
CLT’s paging range) is ready to detect
an intruder.
EFY note. The author has success-
fully tested his prototype with the fol-
lowing CLT makes:
1. Panasonic KX-T 3611 BH (made
in Japan)
2. Panaphone WT-3990 (made in
China)
3. Citizen JRT-5400 (made in India)
 CIRCUIT IDEAS

WATER-LEVEL CONTROLLER IL KU
MAR
ter level touches probe L in the overhead
tank, transistor T5 gets forward biased
SUN
JOYDEEP KUMAR CHAKRABORTY and starts conducting. This, in turn, re-
verse biases transistor T6, which then cuts

I
n most houses, water is first stored transistor T1 gets forward biased and off. But since transistor T6 is bypassed
in an underground tank (UGT) and starts conducting. This, in turn, switches through the relay contacts, the pump con-
from there it is pumped up to the transistor T2 on. Initially, when the over- tinues to run. The level of water contin-
overhead tank (OHT) located on the roof. head tank is empty, transistors T3 and ues to rise.
People generally switch on the pump T5 are in cut-off state and hence pnp tran- When the water level touches probe
when their taps go dry and switch off the
pump when the overhead tank starts over-
flowing. This results in the unnecessary
wastage and sometimes non-availability
of water in the case of emergency.
The simple circuit presented here
makes this system automatic, i.e. it
switches on the pump when the water
level in the overhead tank goes low and
switches it off as soon as the water level
reaches a pre-determined level. It also
prevents ‘dry run’ of the pump in case
the level in the underground tank goes
below the suction level.
In the figure, the common probes con-
necting the underground tank and the
overhead tank to +9V supply are marked
‘C’. The other probe in underground tank,
which is slightly above the ‘dry run’ level,
is marked ‘S’. The low-level and high-level
probes in the overhead tank are marked
‘L’ and ‘H’, respectively.
When there is enough water in the
underground tank, probes C and S are
connected through water. As a result,
sistors T4 and T6 get for- H, transistor T3 gets forward biased and
ward biased via resistors starts conducting. This causes reverse bi-
R5 and R6, respectively. asing of transistor T4 and it gets cut off.
As all series-con- As a result, the relay de-energises and
nected transistors T2, the pump stops. Transistors T4 and T6
T4, and T6 are forward will be turned on again only when the
biased, they conduct to water level drops below the position of L
energise relay RL1 probe.
(which is also connected Presets VR1, VR2, and VR3 are to be
in series with transistors adjusted in such a way that transistors
T2, T4, and T6). Thus T1, T3, and T5 are turned on when the
the supply to the pump water level touches probe pairs C-S, C-H,
motor gets completed via and C-L, respectively. Resistor R4 ensures
the lower set of relay that transistor T2 is ‘off’ in the absence
contacts (assuming that of any base voltage. Similarly, resistors
switch S2 is on) and the R5 and R6 ensure that transistors T4 and
pump starts filling the T6 are ‘on’ in the absence of any base
overhead tank. voltage. Switches S1 and S2 can be used
Once the relay has to switch on and switch off, respectively,
energised, transistor T6 the pump manually.
is bypassed via the up- You can make and install probes on
per set of contacts of the your own as per the requirement and fa-
relay. As soon as the wa- cilities available. However, we are describ-

ELECTRONICS FOR YOU ❚  AUGUST 2001


ing here how the probes were made for
this prototype.
The author used a piece of non-me-
tallic conduit pipe (generally used for do-
mestic wiring) slightly longer than the
depth of the overhead tank. The common
wire C goes up to the end of the pipe
CIRCUIT IDEAS
through the conduit. The wire for probes
L and H goes along with the conduit from
the outside and enters the conduit through
two small holes bored into it as shown in
Fig. 2.
Care has to be taken to ensure that
probes H and L do not touch wire C di-
ELECTRONICS FOR YOU ❚  AUGUST 2001
rectly. Insulation of wires is to be removed
from the points shown. The same arrange-
ment can be followed for the underground
tank also. To avoid any false triggering
due to interference, a shielded wire may
be used.

INVISIBLE BROKEN
WIRE DETECTOR
K. UDHAYA KUMARAN, VU3GTH
P
ortable loads such as video cam-
eras, halogen flood lights, elec-
trical irons, hand drillers, grind-
ers, and cutters are powered by connect-
ing long 2- or 3-core cables to the mains
plug. Due to prolonged usage, the power
cord wires are subjected to mechanical
strain and stress, which can lead to in-
ternal snapping of wires at any point. In
such a case most people go for replacing
the core/cable, as finding the exact loca-
tion of a broken wire is difficult. In 3-core
cables, it appears almost impossible to de-
tect a broken wire and the point of break
without physically disturbing all the three
wires that are concealed in a PVC jacket.
The circuit presented here can easily
and quickly detect a broken/faulty wire
and its breakage point in 1-core, 2-core,
and 3-core cables without physically dis-
turbing wires. It is built using hex in-
verter CMOS CD4069. Gates N3 and N4
are used as a pulse generator that oscil-
lates at around 1000 Hz in audio range.
CIRCUIT IDEAS
EDI
DWIV
S.C.
The frequency is determined by timing
components comprising resistors R3 and
R4, and capacitor C1. Gates N1 and N2
are used to sense the presence of 230V AC
field around the live wire and buffer weak
AC voltage picked from the test probe.
The voltage at output pin 10 of gate N2
can enable or inhibit the oscillator circuit.
When the test probe is away from any
high-voltage AC field, output pin 10 of
gate N2 remains low. As a result, diode
D3 conducts and inhibits
the oscillator circuit from
oscillating. Simulta-
neously, the output of gate
N3 at pin 6 goes ‘low’ to
cut off transistor T1. As a
result, LED1 goes off.
When the test probe is
moved closer to 230V AC,
50Hz mains live wire, dur-
ing every positive half-
cycle, output pin 10 of gate
N2 goes high.
Thus during every
positive half-cycle of the
mains frequency, the os-
cillator circuit is allowed
to oscillate at around 1 kHz, making red
LED (LED1) to blink. (Due to the persis-
tence of vision, the LED appears to be
glowing continuously.) This type of blink-
ing reduces consumption of the current
from button cells used for power supply.
A 3V DC supply is sufficient for pow-
ering the whole circuit. AG13 or LR44
type button cells, which are also used in-
side laser pointers or in LED-based conti-
nuity testers, can be used for the circuit.
The circuit consumes 3 mA during the
sensing of AC mains voltage.
ELECTRONICS FOR YOU ❚  AUGUST 2001
For audio-visual indication, one may
use a small buzzer (usually built inside
quartz alarm time pieces) in parallel with
one small (3mm) LCD in place of LED1
and resistor R5. In such a case, the cur-
rent consumption of the circuit will be
around 7 mA. Alternatively, one may use
two 1.5V R6- or AA-type batteries. Using
this gadget, one can also quickly detect
fused small filament bulbs in serial loops
powered by 230V AC mains.
The whole circuit can be accommo-
dated in a small PVC pipe and used as a
handy broken-wire detector. Before detect-
ing broken faulty wires, take out any con-
nected load and find out the faulty wire
first by continuity method using any mul-
timeter or continuity tester. Then connect
230V AC mains live wire at one end of
the faulty wire, leaving the other end free.
Connect neutral terminal of the mains
AC to the remaining wires at one end.
However, if any of the remaining wires is
also found to be faulty, then both ends of
these wires are connected to neutral. For
single-wire testing, connecting neutral
only to the live wire at one end is suffi-
cient to detect the breakage point.
In this circuit, a 5cm (2-inch) long,
thick, single-strand wire is used as the
test probe. To detect the breakage point,
turn on switch S1 and slowly move the
test probe closer to the faulty wire, begin-
ning with the input point of the live wire
and proceeding towards its other end.
LED1 starts glowing during the presence
of AC voltage in faulty wire. When the
breakage point is reached, LED1 immedi-
ately extinguishes due to the non-avail-
ability of mains AC voltage. The point
where LED1 is turned off is the exact
broken-wire point.
While testing a broken 3-core rounded
cable wire, bend the probe’s edge in the
form of ‘J’ to increase its sensitivity and
move the bent edge of the test probe closer
over the cable. During testing avoid any
strong electric field close to the circuit to
avoid false detection.

PC-BASED MULTI-MODE
LIGHT CHASER
VIJAYA KUMAR P.
F
or those who want to use their PC
for various electronic functions,
here is a circuit that converts a
PC to a multi-mode light chaser. The ad-
vantage of this light chaser over other
light chasers is that users can define their
own patterns (designs) of running lights
by altering the source program that re-
quires a simple hardware. The program
given here produces 24 different patterns
of running light.
The circuit shown in Fig. 1 is mainly
used to physically isolate the PC hard-
ware from the mains supply and to make
it capable of driving 230V loads. The PC’s
parallel port (LPT1) provided on its back
is used to interface with the circuit. LPT
CIRCUIT IDEAS
NA
ANJA
RUP
port is terminated in a 25-pin ‘D’ type
female connector. Its pin configuration is
shown in Table I.
Triacs are used to drive 230V bulbs.
Triac BT136 used here can take up a load
of up to 800 watts. If you want to drive
higher loads, BT136 (4A) can be replaced
with triacs of higher current ratings, like
BT139 (16A). Since we are using triacs to
drive 230V bulbs, the mains supply would
also appear on the PC. Optocouplers have
been used to isolate the PC from 230V
mains supply.
The circuit can be assembled on a
general-purpose dotted PCB and can be
linked to the PC’s LPT port (female) us-
ing a 25-pin male ‘D’ type connector along
ELECTRONICS FOR YOU ❚  AUGUST 2001
TABLE I
Pin Configuration
Pin Description
1 *Strobe
2 Data bit 0
3 Data bit 1
4 Data bit 2
5 Data bit 3
6 Data bit 4
7 Data bit 5
8 Data bit 6
9 Data bit 7
10 Acknowledge
11 *Busy
12 Paper end
13 Select
14 *Auto feed
15 Error
16 Initialise
17 *Select input
18-25 Ground
Note: *indicates that pins are internally
(hardware) inverted.
with a 25-core cable. Instead of connect-
ing 230V bulbs you can connect small
6.2V miniature lamps, which are easily
available in electrical shops. Connections
are shown in Fig. 3. While using
6.2V miniature lamps, 50 miniature
lamps must be connected in series
and the net combination of 50 bulbs
in series should be connected to
each channel (channel 1 through
channel 8).
Since LEDs require very small
current, parallel ports can directly
drive LEDs. Software can be tested
using simple hardware as shown in
Fig. 2.
C language provides a built-in
outportb() function to output binary
data to a hardware port. To under-
stand this, let us consider the fol-
lowing program:
#include <dos.h>
main()
{
int i;
printf(“Input a decimal number”);
scanf (“%d”,&i);
outportb() (0x0378,i);
}
The above program is used to
output a binary equivalent of the
decimal number entered. Scanf func-
tion is used to take the input deci-
mal number from the keyboard. The
outportb() function directly outputs
the binary equivalent of the decimal
number to LPT1 (Port ID is 0x0378).

For example, if the number entered is 15,
its binary equivalent 00001111 is written
into data pins D0 to D7 of the parallel
port.
To understand the logic of multi-mode
light chaser, first consider the following
simple sequential running light program:
#include <stdio.h>
#include <dos.h>
#include <math.h>
CIRCUIT IDEAS
main() are generated. The outportb() function is
{ used to write binary equivalents of 1, 2,
int temp=0,i,ch,PORT = 0x0378; 4, 8, 16, 32, 64, and 128 to data pins D0
printf(“Press x to exit”); to D7, with D0 as the least significant
run: digit and D7 as the most significant digit.
for(i=0;i<8;i++) The binary equivalents of numbers
{ obtained by incrementing powers of 2 up
tempb=pow(2,i); to 7 are given below:
outportb(PORT,temp); /* outputs BINARY no.
Decimal number Binary equivalents
to LPT1 */
1 00000001
delay(2000); /*using delay to control speed */
2 00000010
if(bioskey(1))/*To check whether any key is 4 00000100
pressed */ 8 00001000
ch=getch(); 16 00010000
ch=toupper(ch); 32 00100000
64 01000000
if(ch==’X’) 128 10000000
{
It is clear from the table that the re-
sulting binary numbers will produce the
running light effect. Delay function de-
fines the speed of running. ‘Go to’ state-
ment is used to take control uncondition-
ally to ‘for’ loop, so as to repeat the run-
ning process.
By changing the formula of producing
binary number patterns, one can get dif-
ferent actions. The multi-mode light
chaser program is divided into a number
of cases. Each case will produce two or
more actions. These cases are made to
switch automatically using switch state-
ment and one ‘for’ loop. Further, by chang-
exit(0); ing the delay time, one can increase or
} decrease the speed of running lights.
} EFY note. The complete source-level
goto run; program of multi-mode chaser lights in
} C language has been published in Soft-
In the above program, ‘for’ loop is used ware Section of this issue on page No.
to increment ‘i’ in steps of 1 up to 7. As 86. It will also be included along with
these values of ‘i’ get substituted in the executable version of the program in
temp=pow(2,i), numbers temp= 20=1, 21=2, the next month’s EFY-CD.
22 =4, 23=8, 24=16, 25=32, 26=64, and 27=128
ELECTRONICS FOR YOU ❚  AUGUST 2001
 CIRCUIT IDEAS

the bottom part of the LED gets the sup-

FUSE STATUS INDICATORS

ply and therefore only the red part of the
LED is lit. The formulae for working out
the values of current-limiting resistors for
each colour LED are shown in Table I.

FOR POWER-SUPPLIES S.C.

DWIV
EDI
These relationships are applicable to the
circuits of Figs 1 and 2.

M.K. CHANDRA MOULEESWARAN

F
use status indicators are very with all sorts of power-supplies and
simple to construct using a few other instruments that use power-
components. These go very nicely supply sections. The logic and the
formula, if any, used with
each circuit/figure are shown
in the corresponding
truth tables.
Fig. 1 shows the
use of a 3-pin bi-
colour LED. When
the fuse is intact,

TABLE I (REFER FIG. 1)

Indicator Details
both red and
Fuse status Bias to LED1 Colour of LED1
green parts of
A1-red anode A2-green anode
the LED are lit
Intact Forward Forward Red+green=yellow
Blown Forward Nil Red and the LED
Relationship to evaluate R1 and R2 in Figs 1 and 2:
emits a yellow
DCVin-VLED % ILED=R1 or R2 in ohms light. With the
where Vin and VLED are in volts, ILED in amperes fuse in blown
In Fig. 2, VLED=VD2+VLED for flasher LED path condition, only

TABLE II (REFER FIG. 2) Fig. 2 employs an additional flashing

Indicator Details LED in series with the red part of the bi-
Fuse status Bias to LED1 and LED2 Colour of colour LED. So the fuse failure is indi-
LED2-anode A1-red anode A2 green anode LED1 and LED2 cated by the flashing of LED as well as
Intact Forward Forward Forward Continuous green LED1+ the red part of the bi-colour LED.
flash red LED1+flash red Fig. 3 shows the use of a bi-colour
LED2=green and yellow LED in the AC mains supply circuit. The
alternate+flash red
Blown Forward Forward Nil Flashing red LED1 and LED2 unique feature of this circuit is that just
by altering the resistor values, it can be
TABLE III (REFER FIG. 3) used in low-voltage AC circuits or DC cir-
cuits.
Indicator Details
The AC is converted into pulsating
Bias to LED1 Colour of LED1
A1-red anode A2-green anode DC using rectifier diodes before applica-
Intact Forward Forward Red+green=yellow at 50Hz flicker
tion to the LED sections via current-lim-
Blown Forward Nil Red at 50Hz flicker iting resistors. For higher power dissipa-
Note. Approximate DCVin at C of D1 or D2 is 200 volts tion in current-limiting resistors, a series
combination of resistors can be used. Be-
TABLE IV (REFER FIG. 4) cause of the pulsating voltage, the LEDs
Indicator Details would produce a flickering effect. The to-
Supply input Polarity of Polarity to LED1 Colour of LED1 tal series resistance with each LED sec-
the supply at P1 at P2 tion may be calculated by dividing 200
DC Forward Positive Negative Red-continuous volts with the desired LED current (say,
Reverse Negative Positive Green-continuous 10 mA).
AC Alternates Alternates Alternates between red Fig. 4 shows the use of a 2-pin bi-
at 50Hz/s at 50Hz/s and green at 50 Hz and colour LED. The two LEDs are internally
appears yellow
connected in reverse, so they glow both

ELECTRONICS FOR YOU ❚  AUGUST 2001

 CIRCUIT IDEAS

ways of the supply polarity connections
and can be easily used for AC circuits as
indicators. The correct polarity is indi-
cated by green and the reverse polarity
by red. The AC supply is shown by yel-
low, which, in fact, is due to the turning
‘on’ of both the colours at the AC mains
frequency. When the frequency is more
than 20 Hz, the two colours combine to
produce yellow light. Pin identification of
this LED is done usually by using a cur-
rent-limiting resistor and DC supply only.
All the circuits can be effectively al-
tered to suit an individual’s requirement.

ELECTRONICS FOR YOU ❚  AUGUST 2001

Construction

2001
 CONSTRUCTION

DIGITAL CAPACITANCE-CUM-
FREQUENCY METER SUN
IL KU
MAR
position 3, 1-kilo-ohm charging resistor
R6 is selected by SR1, while SR2 selects
1 kHz as the frequency for counter opera-
tion.
PRATAP CHANDRA SAHU Ganged rotary switches SR3 and SR4
are used for frequency measurement mode
only. (EFY note. As decimal indication

H
ere is an inexpensive circuit of We get the capacitance value directly from is not required during capacitance mea-
a digital capacitance-cum-fre- the readout of the counter in picofarads. surement, one might have an additional
quency meter that can measure Similarly, if we take R = 1 mega-ohm
capacitance in the range of 1 pF to 10,000 and external frequency = 1 kHz, we can PARTS LIST
Semiconductors:
µF and frequency in the range of 0 to 100 read the value of the capacitor under test
IC1 - NE555 timer
kHz. With a slight modification, this cir- (CUT) directly in nanofarads. With R = 1 IC2, IC3 - CA3140 high-input
cuit can be used as an article counter or kilo-ohm and frequency = 1 kHz, we can impedance op-amp
a time meter. read the value of the CUT directly in mi- IC4 (A-D) - 7408 AND gate
The principle. In a frequency crofarads. IC5 - MM74C925 4-digit counter/
7-segment driver
counter, the unknown input is ANDed Frequency measurement. This in-
IC6 - 74LS121 monostable MV
with a known time-base period, so that volves passing the unknown frequency sig- IC7-IC9 - 74LS90 decade counter
the numbers of cycles passed over the nal for a known time base period through (divide-by-10)
time-base period are counted. The time the counter. In a 4-digit counter with a IC10 - 7476 JK flip-flop
period can be measured similarly if a time base of one second, the maximum IC11 - 7805 regulator +5V
D1-D5 - 1N4007 rectifier diode
known frequency is gated with the un- display will be 9999, which means that D6 - 1N4148 switching diode
known time period. The same instrument we cannot read a frequency of more than LED1 - Red LED
can also determine the time period of a 9999 Hz (≈10 kHz). However, if we re- T1-T5 - BC547B npn transistor
periodic waveform or the time elapsed be- duce the time base to 0.1 second, the fre- T6 - BS107 FET
Resistors (all ¼ watt, ±5% carbon, unless
tween two events. quency reading can go up by a factor of
stated otherwise)
In this circuit, the capacitance mea- ten to 99.99 kHz (≈100 kHz) as the time R1 - 2.2-kilo-ohm
surement is nothing but the measurement base virtually divides the input frequency R2, R5 - 1-mega-ohm
of the time between two events in a charg- by 10. For low-frequency measurement, R3, R8, R24 - 4.7-kilo-ohm
ing capacitor. An R-C (resistor-capacitor) we can increase the resolution by a factor R4, R20 - 10-kilo-ohm
R6, R7, R18
circuit works as a time generator and the of ten by increasing the time base period R21 - 1-kilo-ohm
time is directly proportional to capacitance to 10 seconds, which is equivalent to the R9-R16 - 220-ohm
value under suitable conditions. In the multiplication of the input frequency by a R17 - 20-kilo-ohm
present case the condition being satisfied factor of 10. R19 - 100-kilo-ohm
R22, R23 - 560-kilo-ohm
is that the time period (T) is equal to the
VR1 - 1-kilo-ohm preset
product RxC, where R is the value of the
charging resistor in ohms and C the ca-
Circuit and operation Capacitors:
C1 - 15µF, 25V electrolytic
pacitance value in farads. The capacitance measurement mode. C2 - 0.01µF ceramic disk
Capacitance measurement. One During the capacitance measurement C3 - 10nF ceramic disk
C4 - 10µF, 250V electrolytic
RxC time (seconds) is required to charge mode, switches S1 through S5 are kept C5 - 1000 µF, 25V electrolytic
a capacitor to 63 per cent (approximately slided towards position ‘C’. The unknown C6 - 100µF, 25V electrolytic
two-third) of its final value (applied volt- capacitor is placed across CUT terminals. C7, C8 - 22 pF ceramic
age). Ganged switches SR1 and SR2 are used C9 - 0.01µF ceramic
Miscellaneous:
Consider the following example: for capacitance measurement. Position 1
X1 - 230 AC primary to 9-0-9 volt,
If C = 470 pF and R = 1 mega-ohm, is used for capacitance range of 1 pF to 500mA secondary trans-
then one RC time period T = 470x10–6 9999 pF (≈10 nF), position 2 for capaci- former
seconds = 470 microseconds. tance range of 1 nF to 9999 nF (≈10 µF), XTL - 1MHz quartz crystal
If we select the external frequency for and position 3 for capacitance range of 1 S1-S5 - Slide switch
S6, S7 - Push-to-on switch
the counter as 1 MHz (time period = 1 µF to 9999 µF. SR1-SR2 - Ganged 3-way, 2-pole rotary
microsecond), the counter progresses by Switch SR1 selects 1 mega-ohm charg- switch
one count every microsecond and the ing resistor in its positions 1 and 2, while SR3-SR4 - Ganged 3-way, 2-pole rotary
counter reading is 470, as the gate will switch SR2 selects a frequency of 1 MHz switch
DIS1-DIS4 - LT543 common-cathode,
be open for 470 microseconds for the in position 1 and a frequency of 1 kHz in
7-segment display
above-mentioned R and C under testing. position 2 for the counter operation. In

ELECTRONICS FOR YOU ❚  AUGUST 2001

 CONSTRUCTION

ELECTRONICS FOR YOU ❚  AUGUST 2001

Fig. 1: Circuit diagram for digital capacitance-cum-frequency meter

Fig. 2: Internal block diagram and functional description for IC 74C925
‘off’ position for SR3/SR4 ganged rotary
switch.)
IC1 is a monostable multivibrator
based on timer NE555 and is meant for
capacitance measurement only. In normal
condition, the low output of the
monostable turns on the FET (BS107)
switch. So the capacitor under test gets
Fig. 3: Actual-size, single-sided PCB layout for digital capacitance-cum-frequency meter
CONSTRUCTION
shorted via the FET switch. As and when
triggered by the momentary push-to-on
operation of start switch S6, the
monostable provides a pulse of 15-second
duration. As soon as its output goes high,
it switches off FET switch. Simulta-
neously, it takes pin 5 of AND gate IC4A
high.
ELECTRONICS FOR YOU ❚  AUGUST 2001
Now let us examine the conditions at
IC2 and IC3 (both CA3140 op-amps). The
voltage across CUT, after being buffered
by IC2, is fed to the inverting input of
IC3 wired as a comparator. The non-in-
verting input of IC3 is biased at 0.63Vcc,
which is set accurately by 1-kilo-ohm pre-
set VR1. Now the capacitor begins to
charge. As soon as the voltage across the
capacitor crosses 0.63Vcc (i.e. 3.15 volts
with Vcc = 5 volts), the output of IC3
goes low. Thus the output of IC3 and also
that of AND gate IC4A remains high un-
til the capacitor charges to 63 per cent of
Vcc in one RC time.
Latch-enable (LE) pin 5 of counter IC5
(74C925) connected to pin 6 of IC4A re-
mains high to pass the clock selected via
rotary switch SR2 and coupled to CL
(clock) pin 11 of IC5 via AND gate IC4B.
It goes low after one CR time to latch its
count as the output of IC3 goes low. Thus
the number of cycles from the frequency
source passed over one CR time is re-
corded in the counter and gets displayed.
For precise generation of 1MHz fre-
quency, a 1MHz crystal oscillator is wired
around Schmitt inverter gates N3 and N4.
The oscillator output is routed via AND
gate IC4C to slide switch S2 and rotary
switch SR2 position 1. In capacitance (C)
position of switch S2, this signal, after
division by three decade counters IC7,
IC8, and IC9 (7490), which are common
to both frequency and capacitance meter
modes, provides 1kHz signal at pin 12 of
IC9, which, in turn, is extended to posi-
tions 2 and 3 of switch SR2. (Note. The
outputs of IC10 are not used during ca-
pacitance measurement. IC10 comes into
play only during the frequency measure-
ment as explained later.)
The NE555 timer used as a monoshot
ensures the capacitance measurement in
an easy and automatic manner. The LED
connected to AND gate IC4D glows dur-
ing the charging of the capacitor. During
the measurement of high-value capaci-
tances, it may take several seconds to
charge to 0.63Vcc. For low-value capaci-
tances, the LED glows for just a moment
after pressing start switch S6. If the LED
goes off after the start button is pressed,
it indicates that the measurement is over.
You can reset NE555 timer using
switch S7 if you want to make another
measurement. If this switch is not pro-
vided/operated, you would have to wait
for at least 15 seconds until NE555 timer
becomes normal. Alternatively, you will

Fig. 4: Component layout for the PCB
have to switch off the complete circuit
and then switch it on again.
Frequency counting. In place of
1MHz oscillator, a 100Hz full-wave recti-
fied (pulsating DC) after being shaped by
Schmitt inverter N2, is used as the mas-
ter clock to provide the required time
bases. The voltage divider network of re-
sistors R20 and R21 protects gate N2
CONSTRUCTION
against high voltage.
R21 is test selected to get proper 100
Hz rectangular wave form at the output
of gate N2. This 100Hz signal is divided
by decade counters IC7, IC8, and IC9 to
obtain 10Hz, 1Hz, and 0.1Hz frequencies.
The frequency selected via rotary switch
SR3 is then divided by 2 by JK flip-flop
7476 (IC10) so as to provide a gate time
ELECTRONICS FOR YOU ❚  AUGUST 2001
of 0.1 second, 1 second, or 10 seconds in
positions 1, 2, and 3, respectively, of
switch SR3. Q output of IC10 is used to
enable counter IC5.
The resetting of counter-cum-display
IC5 is accomplished by the narrow out-
put pulse from IC6 (74121), which is gen-
erated by the leading (rising) edge of Q
output of IC10 connected to its B input
(pin 5) via switch S5. Thus at the begin-
ning of each counting period, IC5 is reset.
IC5 (74C925) is TTL-compatible with
a multiplexed 4-digit, 7-segment display
driver. Its internal block diagram and
functions are described in Fig. 2. The
maximum frequency display in positions
1, 2, and 3 of ganged switches SR3 and
SR4 is limited to 99.99 kHz, 9.999 kHz,
and 999.9 Hz. The decimal point position
is fixed by switch SR4.
Calibration and testing. Connect a
multimeter to the non-inverting terminal
of IC3 and set the point at 0.63Vcc = 3.15
volts using 1-kilo-ohm preset VR1. To test
the capacitance meter, use a 470pF poly-
styrene capacitor with one per cent toler-
ance.
Precaution. Try to screen the mains
transformer from the input. Place the
transformer at a place where the chances
of its interference with the input are mini-
mal or nil. While measuring the fre-
quency, the frequency source under test
should not be touched or loaded to avoid
affecting its frequency due to stray ca-
pacitance associated with the test leads.
An actual-size, single-sided PCB for
the circuit of Fig. 1 is shown in Fig. 3,
with its component layout shown in
Fig. 4. ❏

FLUID-LEVEL CONTROLLER
WITH INDICATOR
BHASKAR BANERJEE
T
he fluid-level controller circuit pre-
sented here allows you to set the
lower and upper fluid levels at
the desired specific positions between two
extreme levels. The total fluid level is di-
vided into ten equal parts. Any two of
these ten positions may be defined as ‘low’
and ‘high’ level, respectively. The system
shows the preset levels on the two 7-seg-
ment displays and the current fluid level
at any instant on a 10-LED bar graph
indicator. The same circuit could also be
used for controlling temperature in a simi-
lar fashion.
Fig. 1: Schematic diagram of fluid-level controller with indicator
CONSTRUCTION
NA
ANJA
RUP
The circuit
The main part of the circuit as shown in
Fig. 1 is dot/bar graph driver LM3914
(IC1). This IC is linearly scaled and is
intended for use in LED voltmeter appli-
cation where the number of illuminated
LEDs indicates the value of input volt-
age. It contains a floating 1.2V reference
source between pins 7 and 8 that may be
used as the reference input for the IC.
The voltage from the sensor is fed to the
input of IC1 at pin 5.
The output of the sensor may vary
ELECTRONICS FOR YOU ❚  AUGUST 2001
from ground level (0V) to supply voltage.
Thus the reference voltage source should
be externally preset, which is feasible with
the help of IC1. This IC can also display
the input voltage on a linear scale using
ten LEDs in the bar graph or the dot
mode. Here we have used the bar graph
mode.
The outputs of IC1 are active-‘low’ and
hence they sink current to illuminate
LEDs. Inverters are used between the out-
puts of IC1 and the inputs of IC3 and IC4
to invert the active-‘low’ outputs of IC1.
There are ten outputs available from IC1,
of which only five are used here. One may
use up to eight outputs of IC1 since IC3
and IC4 (4051) are 1-of-8 data selectors.
(Note. If 4067 were used in place of 4051,
all the ten outputs could be used. It is
also possible to get more than ten out-
puts by cascading LM3941 ICs.)
Using this circuit, the maximum fluid
level can be divided into four equal parts
giving five different level readings from
 CONSTRUCTION

‘0’ (empty/
low level)
to ‘4’ (full/
high level).
Thus the
five levels
are empty,
one-fourth,
half, three-
fourth, and
full. This
division is
meant only
Fig. 2: Optical sensor for control-
ling the
level, while all levels
including the inter-
mediate levels are
constantly displayed
on LED bar graph.
The lower level
can be set anywhere
between 0 and 3 in
steps of 1 and high
Fig. 3: Sensor level can be set be-
using float tween 1 and 4. The
operated potmeter
fluid level can be
maintained between any two levels by us-
ing IC3 and IC4. IC3 selects the high level
and gets inputs of levels 1, 2, 3, and 4,
while IC4 selects the low level and gets
inputs of levels 0, 1, 2, and 3. All other
unused input pins of IC3 and IC4 are

PARTS LIST
Semiconductors: Fig. 4: Actual-size, single-sided PCB layout for fluid-level controller with indicator
IC1 - LM3914 bar/dot display
driver
IC2 - 4069 hex inverter grounded. levels are displayed by two 7-segment dis-
IC3, IC4, IC5 - 4051 8-channel analogue The selection takes place according to plays DIS1 and DIS2 that are controlled
multiplexer the binary word preset at the select input by two BCD-to-7-segment decoders 4511
IC6 - 4520 dual binary counter
IC7 - 555 timer pins (pin 9, 10, and 11) of IC3 and IC4. (IC9 and IC10, respectively).
IC8 - 4081 quad 2-input AND The required binary word is generated by The outputs of IC3 and IC4 are fed to
gate a dual divide-by-16 counter IC6 (4520). the select input pins of IC5 (4051). The
IC9, IC10 - 4511 BCD-to-7-segment (IC6 can be replaced by a divide-by-10 output of IC5 is fed back to one of its
latch/decoder/driver
LED1, 3, 5, 7, 9 - Green LED counter 4518, if desired.) Half of IC6 is select inputs through an inverter. IC5 de-
LED2, 4, 6, 8, used for high level and the other half for termines the control logic. The pump (or
10, 11 - Red LED low level. IC6 gets its counting pulse from the heater in temperature controller)
Resistors (all ¼-watt, ±5% carbon unless a 555 timer (IC7) used for generation of should be ‘on’ when the fluid (or tempera-
stated otherwise):
R1-R10, approximately 1Hz pulse train. ture) level is below the minimum level
R16-R31 - 470-ohm The high level is set by pressing and should remain ‘on’ until the maxi-
R11-R15 - 10-kilo-ohm switch S1, while the low level is set by mum level is reached. It must not start if
R32-R33 - 47-kilo-ohm
R34 - 1-kilo-ohm
pressing switch S2. IC6 is reset when the the fluid level falls below the maximum
VR1 - 10-kilo-ohm preset power is switched on. This power-on-re- level but remains above the minimum
Capacitors: set function is realised using capacitors level. This function is realised by IC5 that
C1, C2 - 22µF, 25V electrolytic C1 and C2, and resistors R12 and R13. can operate a pump (or an alarm, or a
C3, C4 - 10µF, 25V electrolytic
C5 - 1µF ceramic disk The part of IC6 connected to high-level flow valve, or a heater, as required) ac-
Miscellaneous: selector also gets reset when the count is cording to this control logic. For this, the
DIS1, DIS2 - Common-cathode 5 (101 binary). This reset pulse is gener- input lines of IC5 are set to appropriate
7-segment display ated using AND gates of IC CD4081. logic levels, which must not be disturbed.
S1, S2 - Push-to-on switch
The selected minimum and maximum Sensor. To control the fluid level (say,

ELECTRONICS FOR YOU ❚  AUGUST 2001

 CONSTRUCTION

water level in a tank), an optical sensor

as shown in Fig. 2 may be used. This
optical sensor consists of a small filament
lamp (generally used in torch or an IR
LED as light source) and an LDR or a
photodiode as the sensor. The filament
lamp may be powered using the same
step-down transformer that is used to
power the circuit. Alternatively, a sepa-
rate step-down transformer may be used
for the purpose, but taking into account
the voltage and current ratings of the
lamp.
One may also use the sensor described
in ‘Digital Water Level Meter’ in Circuit
Ideas section of the February 2000 issue
of EFY. Use that sensor (VR4) as part of
a voltage divider network as shown in
Fig. 3. If the circuit is used as a tempera-
ture controller, a temperature sensor us-
ing the popular LM35 IC may be built
(refer Circuit Ideas published in March
1993 issue of EFY).
Operation. The lower or the mini-
mum level is set by pressing switch S2
and the upper or the maximum level by
pressing switch S1. The two switches
should be kept pressed until the required
level is displayed. For example, if the
lower level is selected 1 and the upper
level 3, the pump (or heater or a flow
valve) will start when the fluid falls be-
low level 1 and will stop when the fluid
reaches level 3.
Assembly and testing. The circuit
may be built on a veroboard. However, Fig. 5: Component layout of PCB
an actual-size, single-sided PCB and its
component layout are shown in Figs 4 ied between ground and positive supply. of power failure, there should be proper
and 5, respectively. Switches used, should While testing, set preset VR1 to in- battery back-up. Otherwise, the system
be of good quality. After assembling, the crease or decrease the reference voltage will not behave as desired. Red and green
circuit may be tested using a voltage di- taking into account the maximum output LEDs are arranged in alternate fashion
vider (potentiometer) that could be var- available from the actual sensor. In case to make the bar display look attractive.❏

ELECTRONICS FOR YOU ❚  AUGUST 2001

September

2001
Circuit Ideas

2001
 CIRCUIT IDEAS

A HIERARCHICAL using eight XNOR gates as shown in the

figure. Let the output lines from XNOR

PRIORITY ENCODER SUN

IL KU
MAR
gates be N0 through N7. Consider inputs
Lp and Mp of the corresponding XNOR
gate. Since Mp = 0 and also Lp = 0, the
output of this XNOR gate is Np = comple-
DR BHASKARA RAO N. ment of Lp = 1. All other L’s are not changed
because the corresponding M’s are all 1’s.

A
normal priority encoder encodes
only the highest-order data line.
But in many situations, not only
the highest but the second-highest prior-
ity information is also needed. The cir-
cuit presented here encodes both the high-
est-priority information as well as the sec-
ond-highest priority information of an 8-
line incoming data. The circuit uses the
standard octal priority encoder 74148 that
is an 8-line-to-3-line (4-2-1) binary encoder
with active-‘low’ data inputs and outputs.
The first encoder (IC1) generates the
highest-priority value, say, F. The active-
‘low’ output (A0, A1, A2) of IC1 is inverted
by gates N9 through N11 and fed to a 3-
line-to-8-line decoder (74138) that requires
active-‘high’ inputs. The decoded outputs
are active-‘low’. The decoder identifies the
highest-priority data line and that data
value is cancelled using XNOR gates (N1
through N8) to retain the second-highest
priority value that is generated by the
second encoder.
To understand the logic, let the in-
coming data lines be denoted as L0 to L7.
Lp is the highest-priority line (active-‘low’)
and Lq the second-highest priority line
(active-‘low’). Thus Lp=0 and Lq=0. All
lines above Lp and also between Lp and
Lq (denoted as Lj) are at logic 1. All lines
below Lq logic state are irrelevant, i.e.
‘don’t care’. Here p is the highest-priority
value and q the second-highest-priority
value. (Obviously, q has to be lower than
p, and the minimum possible value for p
is taken as ‘1’.)
Priority encoder IC1 generates binary
output F2, F1, F0, which represents the
value of p in active-‘low’ format. The
complemented F2, F1, and F0 are applied
to 3-line-to-8-line (one out of eight out-
puts is active-‘low’) decoder 74138. Let the
output lines of 74138 be denoted as M0
through M7. Now only one line is active-
‘low’ among M0 through M7, and that is
Mp (where the value of p is explained as
above). Therefore the logic level of line
Mp is ‘0’ and that of all other M lines ‘1’.
The highest-priority line is cancelled

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001


Thus data lines N0 through N7 are same
as L0 through L7, except that the highest-
priority level in L0 through L7 is cancelled
in N0 through N7.
The highest-priority level in N0
through N7 is the second-highest priority
leftover from L0 through L7, i.e. Nq=0 and
Nj=1 for q<j≤7. Now these N lines are ap-
plied to priority encoder 2 (IC3) to gener-
CIRCUIT IDEAS
ate S2, S1, S0, which represent q. Thus
the second-highest priority value is ex-
tracted. Through cascading one can recover
the third-highest priority, and so on.
For example, let L0 through L7 = X X
X 0 1 1 0 1. Here the highest ‘0’ line is L6
and the next highest is L3 (X denotes
‘don’t care’). Thus p=6 and q=3. Now the
active-‘low’ output of the first priority en-
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
coder will be F2 F1 F0 = 0 0 1. The input
to 74138 is 1 1 0 and it outputs M0
through M7 = 1 1 1 1 1 1 0 1. Since
M6=0, only L6 is complemented by XNOR
gates. Thus the outputs of XNORs are
N0 through N7 = X X X 0 1 1 1 1. Now
N3=0 and the highest priority for ‘N’ is 3.
This value is recovered by priority en-
coder 2 (IC3) as S2 S1 S0 = 1 0 0.

DIGITAL MAINS
VOLTAGE INDICATOR
PRATAP CHANDRA SAHU
C
ontinuous monitoring of the mains
voltage is required in many ap-
plications such as manual volt-
age stabilisers and motor pumps. An ana-
logue voltmeter, though cheap, has many
disadvantages as it has moving parts and
is sensitive to vibrations. The solidstate
voltmeter circuit described here indicates
the mains voltage with a resolution that
is comparable to that of a general-pur-
pose analogue voltmeter. The status of
the mains voltage is available in the form
of an LED bar graph.
CIRCUIT IDEAS
S.C. DWIV
EDI
Presets VR1 through VR16 are used
to set the DC voltages corresponding to
the 16 voltage levels over the 50-250V
range as marked on LED1 through
LED16, respectively, in the figure. The
LED bar graph is multiplexed from the
bottom to the top with the help of ICs
CD4067B (16-channel multiplexer) and
CD4029B (counter). The counter clocked
by NE555 timer-based astable
multivibrator generates 4-bit binary ad-
dress for multiplexer-demultiplexer pair
of CD4067B and CD4514B.
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
The voltage from the wipers of pre-
sets are multiplexed by CD4067B and the
output from pin 1 of CD4067B is fed to
the non-inverting input of comparator A2
(half of op-amp LM358) after being buff-
ered by A1 (the other half of IC2). The
unregulated voltage sensed from rectifier
output is fed to the inverting input of com-
parator A2.
The output of comparator A2 is low
until the sensed voltage is greater than
the reference input applied at the non-
inverting pins of comparator A2 via buffer
A1. When the sensed voltage goes below
the reference voltage, the output of com-
parator A2 goes high. The high output
from comparator A2 inhibits the decoder
(CD4514) that is used to decode the out-

put of IC4029 and drive the LEDs. This
ensures that the LEDs of the bar graph
are ‘on’ up to the sensed voltage-level pro-
portional to the mains voltage.
The initial adjustment of each of the
presets can be done by feeding a known
AC voltage through an auto-transformer
CIRCUIT IDEAS
and then adjusting the corresponding pre-
set to ensure that only those LEDs that
are up to the applied voltage glow.
(EFY note. It is advisable to use ad-
ditional transformer, rectifier, filter, and
regulator arrangements for obtaining a
regulated supply for the functioning of
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
the circuit so that performance of the cir-
cuit is not affected even when the mains
voltage falls as low as 50V or goes as
high as 280V. During Lab testing regu-
lated 12-volt supply for circuit operation
was used.)
 CIRCUIT IDEAS

the truth table shown. Fig. 3 shows the

ELECTRONIC DICE RUP

ANJA
NA
Karnaugh Map simplification of minterms.
When the software program using ‘C’
language is run after compilation, it
VIJAYA KUMAR P. prompts you to press letter ‘T’ for simu-
lating an action equivalent to throwing of

H
ere is a small circuit of an elec- dice by generating/outputting a random
tronic dice to interface with your
PC. The circuit simulates a digi-
tal dice and uses the parallel-port LPT1
provided on the back of the PC. LPT em-
ploys a 25-pin ‘D’ type female connector.
‘C’ language provides a built-in
outportb() function to output binary data
to the hardware port. To understand this,
let us consider the following program:
#include <dos.h>
main()
{
int i;
printf(“Input a decimal number”);
scanf (“%d”,&i);
outportb(0x0378,i);
}
The above program is used to output
the binary equivalent of a decimal num- Fig. 2
ber entered via the keyboard. ‘Scanf’ func-
tion is used to take the input decimal
number from the keyboard. The
TRUTH TABLE
‘outportb()’ function directly outputs the
binary equivalent of decimal number to Throw Data pins State of LEDs Display
LPT1 (port ID is 0x0378). Logic state
D2 D1 D0 A B C D E F G
For example, after you convert the
above program into an executable file us- 1 0 0 1 OFF OFF OFF OFF OFF OFF ON
ing Turbo C compiler and run it, the pro-
gram prompts you to “Input a decimal 2 0 1 0 ON OFF OFF OFF OFF ON OFF
number”. Suppose you enter 15 , then its 3 0 1 1 ON OFF OFF OFF OFF ON ON
binary equivalent 00001111 is output
(written) to data pins D0 through D7 (pins 4 1 0 0 ON OFF ON ON OFF ON OFF
2 through 9) of the 25-pin parallel port.
5 1 0 1 ON OFF ON ON OFF ON ON
If LEDs are connected to the output pins
of the parallel port, along with resistors 6 1 1 0 ON ON ON ON ON ON OFF
of 220-ohm in series, they can be directly
driven to indicate the binary output num-
ber, as the parallel port can directly sup-
port the current required for driving the
LEDs.
The electronic dice program generates
a random decimal number that is output
through data-output lines D0 through D2
(pins 2 through 4) of the LPT port in the
form of a 3-bit binary number.
Fig. 1 shows the hardware interface
circuit of a BCD-to-decimal converter em-
ploying a 7-segment display driver IC 7447,
which directly converts the input BCD
number into 7-segment display. Fig. 2
shows the circuit simulating the electronic
Fig. 1
dice with dot pattern display that satisfies

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

 CIRCUIT IDEAS

outtextxy(175,20,“**ELECTRONIC DICE**”);
setcolor(GREEN);
settextstyle(DEFAULT_FONT,HORIZ_DIR,2);
outtextxy(x/5,180,“1.Press T to Throw Dice”);
outtextxy(x/5,230,“2.Press X to Exit”);
/* Actual program */
do
{
ch= getch();
ch= toupper(ch);
if(ch==‘T’)
{
randomize ();
ran=random(6); /* to generate random
number between 0&7 */
Fig. 3
ran=ran+1;
outport(PORT,ran); /* outputs BINARY no. to
number, or press letter ‘X’ to exit the pro- int gd=DETECT,gm,ch,x,y; LPT1 */
gram. The program is given below: initgraph(&gd,&gm ,“” ); /* initializes graphics }
#include <stdio.h> mode */ }
#include <dos.h> /* Decorating the screen */ while(ch!=‘X’);
#include <graphics.h> x = getmaxx(); closegraph();
#include <stdlib.h> y = getmaxy(); printf(“By Vijaya Kumar.p”);
main() setbkcolor(BLUE); exit(0);
{ rectangle(10,y-10,x-10,10); }
int ran,PORT = 0x0378; setcolor(YELLOW);
settextstyle(TRIPLEX_FONT,HORIZ_DIR,3);

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

 CIRCUIT IDEAS

LIGHT-OPERATED ORGAN SUN

IL KU
MAR

PRADEEP G.

H
ere is a circuit based on a tric bulb, a sharp and
unijunction transistor (UJT) pleasing audio tone
2N2646 or its equivalent that is heard from the
can be used as a light-operated organ. speaker. The intensity
Wired as a relaxation oscillator, it can of light falling on LDR
oscillate independently without a tank cir- can be varied by wav-
cuit or complicated RC feedback network. ing a hand to and fro
A light-dependent resistor (LDR) is in- between the lamp and
cluded in the emitter circuit of T1 as the LDR. As a result,
shown in the diagram. When LDR receives the frequency of the
light from a light source, such as an elec- output sound changes.

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

Construction

2001
 CONSTRUCTION

MGMA—A MIGHTY GADGET pin is low, output pin 3 is high and ca-

WITH MULTIPLE APPLICATIONS

pacitor C1 starts charging through
potmeter VR1.
When the voltage across capacitor
C1 reaches above half of the supply
EDI
voltage, input pin 1 of gate N1 goes high
A. JEYABAL DWIV and output pin 3 goes low. Now capaci-
S.C.
tor C1 discharges through potmeter
VR1. When the voltage across capacitor

M
GMA, pronounced as migma, is that is controlled by block 2. Block 2 con- C1 falls below half of the supply voltage,
a versatile and multi-purpose tains another oscillator whose frequency pin 1 of gate N1 goes low and the output
gadget. It can be used for a is much lower than that of the former. pin goes high. Now capacitor C1 starts
range of applications, from a simple toy The differentiator circuit in block 3 re- charging again and the cycle repeats
to domestic and workbench applications. sets the decade counters periodically. itself.
It measures time, compares light output, Blocks 4 and 5 count the pulses, which, The pulses from the output of gate
temperature, resistance and capacitance, in turn, are displayed by blocks 6 and N1 reach counter IC2 through resistor
etc. You can use this gadget in a number 7. Digit 9 in tens counter is decoded R1. Switch S1 is provided to stop the
of ways, depending on your imagination by block 8, and its output disables the counting manually by grounding the
and creativity. counting process and triggers the aural pulses through R1 when switch S1 is
Basically, MGMA is a resistance-ca- indicator in block 9. Block 10 comprises pressed.
pacitance-controlled oscillator that counts the regulated power supply to run the Counter and display. The output of
the pulses for a specific period. If any gadget.
transducer, such as light-dependent re- PARTS LIST
sistor (LDR) or heat-dependent resistor Semiconductors:
(thermistor), is connected to it, the dis-
Circuit IC1 - CD4093 quad 2-input
Schmitt trigger NAND gate
play shows the value corresponding to its Oscillator. In Fig. 2, Schmitt trigger in- IC2, IC3 - CD4033 decade counter/
resistance. Contact or break (normally put NAND gate N1 of IC1 (CD4093), ca- 7-segment decoder
open or closed) type transducers can also pacitor C1, and potmeter VR1 form the IC4 - 7805 +5V regulator
be used with MGMA. oscillator circuit. Let us presume that ca- T1 - BC557 pnp transistor
Fig. 1 shows the block diagram of the pacitor C1 is in discharged state and pin T2 - SL100 npn transistor
D1-D7 - 1N4148 switching diode
MGMA circuit. Block 1 is an oscillator 2 of gate N1 is in high state. As the input D8, D9 - 1N4001 rectifier diode
LED1 - Red LED
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise)
R1, R6-R9 - 100-kilo-ohm
R2 - 220-kilo-ohm
R3 - 470-kilo-ohm
R4 - 3.3-kilo-ohm
R5, R10, R11 - 330-ohm
VR1 - 1mega-ohm pot., linear
VR2 - 47-kilo-ohm pot., linear
Capacitors:
C1, C3 - 0.001µF ceramic disk
C2 - 4.7µF, 10V tantalum
C4 - 1000µF, 25V electrolytic
C5, C6 - 0.1µF ceramic disk
Miscellaneous:
X1 - 230V AC primary to 9-0-9V
AC, 100mA secondary
transformer
S1, S2 - Push-to-on switch
S3 - SPST switch, 230V AC
DIS1, DIS2 - LT543 7-segment, common-
cathode type LED display
SOC1 - SOC4 - Earphone socket
SOC5 - DC IN socket
PZ1 - Piezo-buzzer
- IC bases, knobs, mains
chord, cabinet
- Banana-type earphone plugs
Fig. 1: Block diagram of the MGMA circuit

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

 CONSTRUCTION

Fig. 2: Schematic diagram of MGMA

the oscillator is connected to clock input playing the number of pulses. count and ensure the proper operation of
pin 1 of IC2 (CD4033, a decade counter Lamp-test (LT) pin 14 of both IC2 and digit-9 decoder circuit.
for unit digits). The carry-out pin 5 of IC3 is grounded through 100-kilo-ohm re- Display controller and differen-
IC2 is connected to the clock input of de- sistor R8. The test-point (TP) may be used tiator. For accurate reading of the
cade counter IC3 that is meant for ten’s to check the display. When a high-level counter, it must be reset periodically
digits. The segment outputs of both IC2 voltage (5V) is applied to the test-point, and the pulses must be counted for a
and IC3 go to the respective seven seg- all segment outputs go high and the dis- specific period. For this an oscillator cir-
ments of DIS1 and DIS2 (LT543) for dis- play shows 88. cuit comprising gate N2, diodes D1 and
The display is blanked out D2, resistor R2, potmeter VR2, and ca-
TABLE when the number to be dis- pacitor C2 is used. This oscillator also
Count Decoded output of IC CD4033 played is 0, provided the ripple works like the previous one, but its charg-
a b c d e f g CO blanking input (RBI) pin 3 is ing and discharging paths are separated
0 1 1 1 1 1 1 0 1 held low. So on reset, only by diodes D1 and D2. Its ‘on’ time (high-
1 0 1 1 0 0 0 0 1 DIS1 (unit digit) will show zero level output) can be controlled by
2 1 1 0 1 1 0 1 1 as RBI pin 3 of IC3 is potmeter VR2.
3 1 1 1 1 0 0 1 1 grounded. When output pin 4 of gate N2 goes
4 0 1 1 0 0 1 1 1 Switch S2 is provided to from low to high state, the differentiator
5 1 0 1 1 0 1 1 0 reset the counter manually. circuit comprising capacitor C3 and resis-
6 1 0 1 1 1 1 1 0 Current-limiting resistors R5 tor R9 produces a sharp pulse that resets
7 1 1 1 0 0 0 0 0
and R10 provided with DIS2 counters IC2 and IC3. At the same time,
8 1 1 1 1 1 1 1 0
and DIS1, respectively, are gate N1 is enabled as output pin 4 of gate
9 1 1 1 1 0 1 1 0
used to reduce the component N2 is connected to input pin 2 of gate N1,

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001


Fig. 3: Actual-size, single-sided PCB pattern
the circuit in Fig. 2
Fig. 4: Component layout for the PCB
and it outputs clock pulses. These pulses
are counted by IC2 and IC3 and displayed
on DIS1 and DIS2, respectively. So the
CONSTRUCTION
oscillator around gate N1
is enabled and disabled
during the high and low
states, respectively, of the
output of gate N2.
The counters retain
their last count for read-
ing until the output goes
high once again. This
reading time is about 2
to 3 seconds, which is set
by resistor R2. Any in-
crease in the value of R2
will increase the reading
time and vice versa. Re-
sistor R3 connected in
parallel across capacitor
C3 is used to discharge it
quickly and diode D3 is
used to block the DC volt-
age (when switch S2 is
pressed) going to gates
N1 and N3, and other
parts of the circuit.
Digit 9 decoder and
aural indicator. It is
suggested for very useful to sound an
alarm for a certain read-
ing or otherwise, say, for
a particular temperature
or light output or resis-
tance value, etc. A perma-
nent number 90 is chosen
for simplicity of the de-
coding circuit. When the
display shows 90, the
counter must be disabled
and the buzzer enabled.
From the table of de-
coded outputs of IC 4033
it is found that for num-
ber 9, at least one of the
segment outputs is low (a,
b and f are high, while e
is low). For number 8,
segment e is inverted by
transistor T2. As RBI pin
3 of IC3 is grounded, all
the segment outputs go
low for 0. The clock-en-
able (CE) pin 2 of IC3 is
pulled up by resistor R7.
Pin 2 is also con-
nected to a, b, f and e seg-
ment outputs of IC3
through diodes D5, D6,
D7, and transistor T2, re-
spectively, that altogether act as AND
gate and bring the CE pin to ground for
numbers 0 through 8. When the number
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
is 9, the segment outputs a, b, and e are
high, except the segment output e, which
is inverted by transistor T2. As a result,
CE pin of IC2 goes high and the counters
are disabled.
Simultaneously, this high-level output
is inverted by gates N3 and N4. The in-
verted output from gate N4 forward bi-
ases transistor T1 to drive the piezo-
buzzer, while the inverted output from
gate N3 grounds the resetting pulses.
Diode D4 prevents the high output of
N3 from reaching the reset pins of IC2
and IC3.
Power supply. In 5V DC power sup-
ply shown at the bottom in Fig. 2, IC
7805 (IC4) is employed for better regula-
tion. DC input/output socket (SOC5) is
provided to operate the gadget with ex-
ternal 9V battery. LED1 acts as a power-
on indicator.
Construction
Figs 3 and 4 show suggested actual-size,
single-sided PCB layout and component
layout, respectively, for the circuit in Fig.
2. Solder the components in the order of
IC sockets, jumpers, resistors, capacitors,
diodes, LED, and transistors. Then con-
nect the rest of the components through
wires. Fig. 5 shows the proposed front-
panel layout of MGMA.
Before connecting VR1 and VR2 to the
PCB, mark the dials using a digital mul-
timeter. Both dial 1 and dial 2 (refer Fig.
5) are calibrated in terms of resistance
for the variable resistance values of 1
mega-ohm in case of VR1 and 47 kilo-
ohm in case of VR2, respectively, using a
digital multimeter. (Note. There may be
dead-ends on both ends of the potmeter,
and it may vary in construction from
manufacturer to manufacturer.) Mark the
dials for every ten units for easy reading
and setting.
Applications
For high-resistance and low-resistance
transducers, use earphone-type sockets
SOC1 and SOC3, respectively. For low-
capacitance and high-capacitance testing,
use earphone-type sockets SOC2 and
SOC4, respectively. For SOC1 and SOC2,
the reading will decrease for the increas-
ing value of resistance and capacitance,
and vice versa for SOC3 and SOC4.
Strength-0-meter. This game re-
quires two small rods or prods. Connect

Fig. 5: Proposed front-panel layout of MGMA
Fig. 6: Connections for water level monitor
them to an earphone plug using a pair of
wires half a metre long. Then insert the
plug into SOC1. Hold the rods in each
hand between forefinger and thumb. Ad-
just dials 1 and 2 such that the buzzer
beeps. Then rotate dial 1 slightly in the
anti-clockwise direction to read around 70,
a point where the buzzer is silent. Now
ask your friends one by one to grip the
rods firmly. The winner is the one who
sounds the buzzer or scores higher on the
meter. This depends on how hard one
holds the rod, the internal resistance of
the body, and dampness of the fingers.
Plant tender. You can use MGMA to
indicate the time of watering in order to
avoid excessive watering of plants. For
this, insert two metal strips on both sides
of the plant. Connect them to an earphone
plug using wires and insert the plug into
socket SOC3. Since soil-resistance in-
creases with loss of water, the alarm can
be set/activated for a specific moisture
level. Adjust dials 1 and 2 such that the
buzzer sounds when the plant needs to
be watered. The buzzer stops in a short
while on sprinkling water over the soil
supporting the plant. The next time the
buzzer will sound automatically when the
plant needs to be watered.
Game of quick hands. This game
CONSTRUCTION
requires an earphone plug with its two
terminals shorted. Inserting this plug into
SOC4 grounds input pins 5 and 6 of
Schmitt NAND gate N2 via the shorted
plug in SOC4. Since output pin 4 is al-
ways in high state, its periodic action of
disabling gate N1 is no longer there.
Connect a 0.1µF capacitor to SOC2
using an earphone plug. Since its capaci-
tance value is higher than that of capaci-
tor C1, the frequency of the oscillator de-
creases. The display shows a reading
on momentarily pressing start/reset
button S2 and then quickly depress-
ing stop button S1. Adjust the dial to
read 50 in the display. Now tell your
friends to press button S2 momen-
tarily and then S1. One who scores
less is more quicker than the others,
and hence the winner.
Water-level monitoring. Five re-
sistors R12 through R16 are con-
nected in series and the junctions of
the resistors are extended to the five
levels of the water tank using wires
(refer Fig. 6). A reference rod is also
fitted with its lower end just below
level 1.
Plug-in a dummy resistor of 100k
into SOC1 and rotate dial 1 to the zero-
resistance position. Adjust dial 2 to read
55 in the display. Cover the unit digit
with an opaque tape, so that only the
ten’s digit is visible. Now remove the
dummy resistor. Connect the other end
of five-resistor ladder and the reference
probe to SOC1. The display will show
the water levels from one-fifth to five-
fifth of the tank, depending on the actual
level at that time.
Measuring resistance. The idea is
simple. First, VR1 (dial 1) is excluded from
the circuit by rotating it to zero reading.
Then an unknown resistor is connected
to SOC1 and dial 2 is adjusted to read a
number just below 90. Now VR1 (dial 1)
is reinstated and rotated to display the
same reading. As dial 1 is marked for
resistance values, the position of dial 1
indicates the value of unknown resistor.
With MGMA, up to 2-mega-ohm re-
sistor can be measured. Connect the un-
known resistor to SOC1 using crocodile
clips. Rotate dial 1 to the zero-resistance
position without touching the resistor, oth-
erwise your body resistance will get in-
cluded in the measurement. Adjust dial 2
such that the display reads around 90.
The resistor is open if the display shows
0, and shorted if you’re unable to set the
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
reading near 90.
Remove the unknown resistor. With-
out disturbing dial 2, slowly rotate dial 1
to get the same reading. Now dial 1 shows
the value of unknown resistor.
If the resistor value is less than 40k,
use SOC3 and repeat the same procedure
with dial 2 instead of dial 1 for accurate
measurement. The resistance value can
be read from dial 2.
Checking and measuing capaci-
tance. Using MGMA you can measure
capacitances from 0.001 µF to 5 µF. First
check for the usability of the unknown
capacitor. Adjust dials 1 and 2 to read 50
in the display. Now check the unknown
capacitor using SOC2 for unipolar or
SOC4 for electrolytic/tantalum capacitors
with the inner and the outer terminals of
the socket for positive and negative ter-
minals of the capacitor. If there is no
change in the reading it means the ca-
pacitor is shorted and a higher reading
implies it is good.
To find the value of an unknown non-
electrolytic (unipolar) capacitor, connect
the same to SOC2. Adjust dials 1 and 2
to read a number around 80 in the dis-
play. Now, without disturbing the dials
insert the known capacitors one by one
in SOC2. The unknown capacitor value is
equal to the value of the known capacitor
for which the display shows the same
reading or near the number 80.
The procedure is same for electrolytic
and tantalum capacitors, except that
SOC4 is to be used in place of SOC2, en-
suring that the inner and the outer ter-
minals of the socket are used for positive
and negative terminals of the capacitor,
respectively.
Testing a diode. Rotate dial 1 to
high-resistance position and adjust dial 2
such that the display shows a flickering
45. Test the diode in SOC3 using an ear-
phone plug in the same manner as men-
tioned earlier. Interchange the leads and
test again. A shorted diode will not make
any change in the reading, while a good
one gives a reading of around 60 and 90
in both the tests. And for the open diode,
the display shows 90 in both the tests.
While checking the diodes, a parallel
resistance of 100k is required across the
diode. Our body resistance may also do.
Other utilities. Heat alarm, fire
alarm, security alarm, strain gauge, in-
truder alarm, rain alarm, number game,
timer, and many other circuits can be
realised using this MGMA circuit. ❏
 CONSTRUCTION

TRAFFIC AND STREET light mode (in daytime). Thus it decides

the mode of operation.

LIGHT CONTROLLER
NA
ANJA The circuit for four sides of traffic
RUP
lights (Part II) also controls the time al-
lowed for each side of traffic. It is further
classified into continuous traffic light
RAJESH GUPTA mode (for day) and blinking yellow light
mode (for night).
Part I Circuit. The block diagram of

T
his circuit of an adjustable traffic This circuit can also be adopted for the circuit for signal generation for
and street light controller can con- synchronisation with the signals of adja- streetlight and traffic light modes is
trol the timings of four sides of cent traffic lights by introduction of ap- shown above the dotted line in Fig. 1. A
traffic lights separately. It can also con- propriate delay in traffic light signals’ tim- natural light-dependent voltage and a ref-
trol the changeover from continuous traf- ings. erence voltage, which determines the
fic light mode to blinking yellow light evening and morning times are connected
mode (at night), and from blinking yellow
light mode to continuous traffic light mode
The circuit PARTS LIST
Semiconductors:
(during day). In addition, this circuit also The circuit has two parts—the first for IC1 - LM358 op-amp
controls the automatic switching off/on of generation of control signals for streetlight IC2 - 7404 Hex inverters
IC3, IC6, IC12 - NE555 timer
the streetlights in the mornings and eve- and traffic light modes and the second for IC4 - 74LS93 4-bit binary
nings with flexible settings—defining the generation of four sides of traffic light sig- counter
morning and evening time. In order to nals. IC5 - 74LS164 8-bit serial shift
prevent false triggering of streetlight cir- The circuit for streetlight and traffic register
IC7-IC9 - 7476 dual JK master-slave
cuitry due to some shadow or light on the light modes (Part I) controls the switching flip-flop
sensor, some time delay is taken into con- time of streetlights in evenings and morn- IC10 - 7400 Quad 2-input NAND
sideration before sending the control sig- ings and the time to changeover from con- gates
IC11 - 7410 Triple 3-input NAND
nal for streetlight operation. Its opera- tinuous traffic light mode to blinking yel- gates
tion does not require any software and low light mode (at night), and from blink- IC13 - 7408 Quad 2-input AND
hardware knowledge. ing yellow light mode to continuous traffic gates
IC14-IC17 - 7402 Quad 2-input NOR
gates
T1-T6 - SL100 npn transistor
D1-D14 - 1N4007 rectifier diode
LED1, LED3,
LED6, LED9,
LED12 - 3mm red LED
LED2, LED5,
LED8, LED11 - 3mm green LED
LED4, LED7,
LED10, LED13 - 3mm yellow LED
Resistors (all ¼-watt, 5% carbon, unless
stated otherwise):
R1, R2,
R18-R21 - 2.2-kilo-ohm
R3-R5, R8,
R12-R17,
R22-R25 - 100-kilo-ohm
R6 - 47-kilo-ohm
R7, R9, R11 - 10-kilo-ohm
R10 - 100-ohm
R26 - 47-ohm
R27 - 22-kilo-ohm
R28 - 6.8-kilo-ohm
VR1, VR2,
VR4-VR7 - 1-mega-ohm preset
VR3 - 100-kilo-ohm preset
VR8 - 10-kilo-ohm preset
Capacitors:
C1 - 220µ, 10V electrolytic
C2, C4, C6 - 0.01µ ceramic
C3, C5 - 6.8µ, 10V electrolytic
Miscellaneous:
LDR1
Fig. 1: Block diagram of traffic and street light controller S1 - Push-to-on switch

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

 CONSTRUCTION

Fig. 2: Schematic diagram for the traffic and street light controller

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001


individually to the two inputs of a com-
parator. Low and high states of the com-
parator output decide morning and
evening timings, respectively. The output
of comparator is properly delayed for ob-
taining the signals for streetlight and traf-
fic light modes.
In the detailed circuit diagram shown
above the dotted line in Fig. 2, a natural
light-dependent voltage is obtained at the
junction of light-dependent resistor LDR1
and resistor R7. Resistor R6 is used in
parallel with LDR1 to limit the variation
of the LDR. Light-dependent voltage and
variable reference voltage are connected
to the inverting and non-inverting termi-
nals respectively of comparator IC1(a).
In the evening, voltage at the invert-
ing terminal of the comparator decreases
with time due to the increasing resistance
of LDR1. At a particular natural light in-
tensity (determined by variable reference
voltage, which can be adjusted with the
help of preset VR8), it becomes less than
the voltage at the non-inverting termi-
nal. This drives the comparator into posi-
tive saturation region. Similarly, in the
morning the comparator goes into nega-
tive saturation region at the same natu-
ral light intensity. In this way, the com-
parator gives high voltage (logic 1) for
evening and low voltage (logic 0) for morn-
ing.
IC1(b), with the non-inverting termi-
nal biased at about 1/3rd Vcc, is simply
used as an inverter (though wired as com-
parator). The inverted output of compara-
tor IC1(a) is coupled to transistor T1
through resistor R4, while its direct out-
put is coupled to transistor T2 via resis-
tor R5.
It is observed that transistor T1 is
cut off in the evening and Vcc is applied
to pin 7 of timer IC3 (wired in astable
multivibrator mode) via resistor combi-
nation RA1 (=R2+R3+VR1), while in the
morning T2 is cut off and Vcc is applied
to pin 7 of IC3 via RA2 (=R1+R8+VR2).
In other words, the time period of IC3 is
dependent on RA1 from the evening and
RA2 from the morning.
The diode pair of D1 and D2 or D4
and D5 is used to effectively isolate pin 7
of IC3 from being pulled towards ground
via the conducting transistor (T2 in the
evening and T1 in the morning). Time
period of 555 clock in astable mode can
be determined from the following rela-
tionship:
T = RA (C/1.44) + 2 RB (C/1.44)
CONSTRUCTION
where RA = RA1 from the evening and
RA = RA2 from the morning, while RB =
R9 = 10 kilo-ohm and C = C1 = 220 µF.
Clock-1 output of IC3 is connected to 4-
bit negative-edge-triggered counter
74LS93 (IC4).
Period of output QD of IC4 is 16 times
the clock-1 time period. This QD output
(low for first eight clock-1 cycles and high
for the next eight clock-1 cycles, and re-
peating thereafter) of IC4 is connected to
the clock input of an 8-bit (positive-edge-
triggered) serial shift register 74LS164
(IC5).
The output of IC1(a) forms the data
(D) input for the shift register. The data
(D) at QA output is available after eight
clock-1 cycles, while that at QH is avail-
able after 120 clock-1 cycles. Thus morn-
ing/evening (low/high) data is available
at QA and QH outputs after 8 and 120
clock-1 cycles, respectively. Note that the
clock-1 period itself differs for morning
data and evening data.
Streetlight indicator (LED1) is con-
nected to QA output of shift register IC5.
The evening data (high) from comparator
IC1(a) passes to the streetlight after eight
clock cycles of clock-1. This delay is taken
into consideration in order to prevent false
signals to the streetlight due to some
shadow or light on the sensor.
The delayed high QH output provides
the control signal for night to the second
part of circuit and changes continuous
traffic light mode to blinking yellow light
mode. In this way the time at which night
functioning of traffic light starts can be
adjusted by choosing appropriate time pe-
riod for clock-1 by adjusting the value of
RA1. Similarly, the time at which day
TABLE I
Functional Summary of Part I Circuit
Time Output Output at Output at Activated RA Street Traffic
of IC1(a) QA of IC5 QH of IC5 Resistance Light Light
Evening HIGH LOW
After 8 cycles of clock-1 HIGH HIGH
(Delay time for streetlight)
After 120 cycles of clock-1 HIGH HIGH
(Delay time for night)
Morning LOW HIGH
After 8 cycles of clock-1 LOW LOW
(Delay time for streetlight)
After 120 cycles of clock-1 LOW LOW
(Delay time for day)
Evening HIGH LOW
Delay times and evening/morning times are adjustable.
A: Continuous traffic light mode B: Blinking yellow light mode
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
functioning of traffic light starts (stop
blinking yellow light mode and start con-
tinuous traffic light mode) can be adjusted
by RA2.
Low (delayed morning signal) and
high (delayed evening signal) QH outputs
go to the second part of circuit for select-
ing the mode of traffic light. Table I
summarises the functioning of the circuit
for signal generation for streetlight and
traffic light modes.
Part II Circuit. The block diagram
of the circuit for signal generation for four
sides of traffic lights is given below the
dotted line in Fig. 1. Here, the 4-bit and
2-bit counters are joined together to form
a 6-bit counter. Outputs of the 2-bit
counter, representing two MSB digits, are
connected to a decoder that has two con-
trol inputs and four outputs. The decoder
activates one of the four outputs depend-
ing upon the input (00 or 01 or 10 or 11)
of 2-bit counter.
Each output of the decoder can drive
clock-2 at a different frequency. These four
outputs are connected to the four sides of
traffic lights and select each side one af-
ter another. The time in which the pre-
ceding 4-bit counter counts from 0000 to
1111 (16 counts) is the time allowed for
each side of traffic lights.
First, when the 4-bit counter counts
from 0000 to 0001 (two counts), yellow
light of the selected side will turn ‘on’.
From count 0010 to 1101 (12 counts),
green light will turn ‘on’. Again from 1110
to 1111 count (two counts), yellow light
will turn ‘on’. Meanwhile, in the other
three sides of traffic lights that are not
selected by the decoder, red light will be
‘on’. Similar operation will repeat for each
(LED1) Mode
LOW RA1 OFF A
LOW RA1 ON A
HIGH RA1 ON B
HIGH RA2 ON B
HIGH RA2 OFF B
LOW RA2 OFF A
LOW RA1 OFF A
 CONSTRUCTION

Fig. 3: Actual-size, single-sided PCB for the circuit in Fig. 2

Fig. 4: Component layout for the PCB

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

Fig. 5: Connections for vehicular traffic lights and pedestrians’ signals
of the selected side in its turn.
Reset pin of clock-3 and clear pins of
the 6-bit counter are controlled by output
QH from IC5 of Part I. At night, QH will go
high and the 6-bit counter will clear, while
clock-3 becomes active. As a result, yel-
low lights of the four sides of traffic light
will blink simultaneously.
The detailed circuit diagram is given
below the dotted line in Fig. 2. The ac-
Fig. 6: The traffic and street light controller
CONSTRUCTION
tive-‘low’, clear input signal for the 6-bit
counter (formed by dual J-K flip-flops
inside IC7 through IC9) is provided
from the output of NOR gate E1, whose
one input is connected to QH output of
shift register IC5 of Part I and the other
input is connected to the output of in-
verter gate N3. The input of inverter
gate N3 is connected to push-to-on reset
switch S1.
ELECTRONICS FOR YOU ❚  SEPTEMBER 2001
Thus the 6-bit counter will clear when
QH output is high or the reset button is
pressed. The reset key, when pressed, also
causes counter IC4 and shift register IC5
of Part I to be cleared. QH output of IC5
is connected to reset pin 4 of clock-3
(IC12). The output of this clock is con-
nected to inverter gate N4. Low QH (dur-
ing day) activates the 6-bit counter and
deactivates clock-3. Due to this, the out-
put of inverter gate N4 will be high dur-
ing the day. This output is connected to
one of the inputs of four AND gates H1
through H4. Each of these AND gates is
a part of one side of traffic light circuit.
NAND gates B1, B2, and B3 are con-
nected to the outputs of flip-flops F2, F3,
and F4 of the 6-bit counter. The final out-
put of this circuit (the output of gate B2)
will be high whenever the first four bits
of the counter are 1110 or 1111 or 0000
or 0001 (14 or 15 or 0 or 1), otherwise it
will be low. Accordingly, inverter N5 out-
put will be low for the above contents of
the counter and high for the remaining
contents (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
or 13).
The output of NAND gate B2 and its
complement (the output of inverter N5)
are connected to NOR gates X2 (=E2, J2,
K2, and M2) and X3 (=E3, J3, K3, and
M3) of the each side of traffic light, re-
spectively. Other inputs of X2 and X3
NOR gates are common.
The last two flip-flops (F5 and F6) of
the 6-bit counter are connected to four
NAND gates G1 through G4 in such a
way that the output of G1, G2, G3, and
G4 will be low when last two counter bits
are 00 (0), 01 (1), 10 (2) and 11 (3), re-
spectively. For example, when last two
bits of counter contents are 01 (1), only
output of NAND gate G2 will be low and
others (G1, G3 and G4) will be high.
The complements of these four NAND
gate outputs (obtained from collectors of
transistors T3 through T6) are connected
to the four RA resistors of 555 clock-2.
Other terminals of these four resistors
are connected to the anodes of diodes D8,
D10, D12, and D14, while their cathode
terminals are all connected to pin 7 of
555 clock-2 (IC6). This is analogous to
the fashion in which RA1 and RA2 have
been connected in Part I in the clock-1
circuit.
When last 2-bit counter contents are
00, RA3 (=R21+R25+VR7) will become ac-
tive and other three resistors RA4, RA5,
and RA6 will become inactive. Therefore
 CONSTRUCTION

connected to NOR gate X2 of each side

TABLE II
and its complement is connected to NOR
Daytime Functions of Part II Circuit
gate X3 of all sides. Due to this, the out-
Counter Decoder output Activated RA Glowing LEDs put of NOR gate E3 will be high and those
contents G1 G2 G3 G4 resistance
of NOR gates E2 and E4 low. In short,
000000 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and
during the count period 000000 to 000001
000001 red light of other sides)
000010 - 0 1 1 1 RA3 2,6,9,12 (Green light of 1st side and
yellow light of the first side of traffic light
001101 red light of other sides) and red light of the other three sides will
001110 - 0 1 1 1 RA3 4,6,9,12 (Yellow light of 1st side and be ‘on’.
001111 red light of other sides) When the counter counts up further
010000 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and from 000010 to 001101, the output of the
010001 red light of other sides) three-NAND gate circuit will be low and
010010 - 1 0 1 1 RA4 3,5,9,12 (Green light of 2nd side and its complement will be high. Due to this
011101 red light of other sides)
reason, the output of NOR gate E2 will
011110 - 1 0 1 1 RA4 3,7,9,12 (Yellow light of 2nd side and
011111 red light of other sides)
go high and that of NOR gates E3 and E4
100000 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and low. Therefore, when counter contents in-
100001 red light of other sides) crement from 000010 to 001101, green
100010 - 1 1 0 1 RA5 3,6,8,12 (Green light of 3rd side and light of first side and red light of all the
101101 red light of other sides) other sides will be ‘on’.
101110 - 1 1 0 1 RA5 3,6,10,12 (Yellow light of 3rd side and Again from 001110 to 001111, the out-
101111 red light of other sides) put of three-NAND gate circuit will go
110000 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and high, due to which yellow light of first
110001 red light of other sides)
side and red light of the other sides will
110010 - 1 1 1 0 RA6 3,6,9,11 (Green light of 4th side and
111101 red light of other sides) turn ‘on’. The time in which the counter
111110 - 1 1 1 0 RA6 3,6,9,13 (Yellow light of 4th side and counts from 000000 to 001111 can be ad-
111111 red light of other sides) justed by RA3. The functioning of the
Note. The two MSB digits determine the side, while the next four digits determine the time for other three sides of the traffic light is
which the mentioned LEDs are ‘on’. similar.
Daytime functional summary of the
the time period of clock-2 of the 6-bit sides 1, 2, 3, and 4 will be the same as circuit for signal generation for four sides
counter will be dependent upon RA3. the output of NAND gates G1, G2, G3, of traffic light is given in Table II. Change
Similarly, when last 2-bit counter con- and G4, respectively. in RB resistance (VR3+R11) of clock-2,
tents are 01 or 10 or 11, the time period Let us suppose that initially the con- being common for all sides, will change
of clock-2 will be dependent upon RA4 tents of the 6-bit counter are 000000. the time allowed for each side of traffic
(=R20+R24+VR6), RA5 (=R19+R13+VR5), When the counter counts up from 000000 light by an equal amount.
and RA6 (=R18+R12+VR4), respectively. to 001111, the output of NAND gate At night, QH output of IC5 will be high,
The output of NAND gate G1 is con- G1 will be low and that of other NAND due to which the 6-bit counter will clear
nected to the common input of NOR gates gates G2, G3, and G4 high. Due to this, and clock-3 will start working. The out-
E2 and E3 of the first side of traffic light RA3 will be active and the time period of put of NOR gates J1, K1, and M1 and
and complements of the outputs of other clock-2 of the counter will be according NAND gate G1, and the complement of
three NAND gates G2, G3, and G4 are to RA3. the output of the three-NAND gate cir-
connected to one of the inputs of NOR The high output of NAND gates G2, cuit will be low. This forces the output of
gates J1, K1, and M1, respectively. The G3, and G4 forces the output from NOR NOR gate X3 of each side to high state.
other inputs of these NOR gates are con- gates J2, K2, M2 and J3, K3, M3 to low This high output will turn off all the red
nected to QH output of IC5. Red and green state. These low outputs are input to NOR lights and give high signal to one of the
lights are connected to the outputs of NOR gates J4, K4, and M4, due to which the inputs of AND gates H1 through H4. The
gates X4 (=E4, J4, K4, and M4) and X2 output of these gates will be high. It other input of these AND gates is con-
(=E2, J2, K2, and M2), and yellow light is means yellow and green lights will be ‘off’ nected to the complement of clock-3, due
connected to AND gate of each side of the and red light will be ‘on’ in the remaining to which all the four sides of yellow light
traffic light. three sides of the traffic light. will blink.
During daytime, the outputs of AND Due to the low output of NAND gate The four sides of traffic light signals
gates (which are connected to yellow G1 (which is connected to the common can be used for driving vehicular traffic
lights) will be the same as the outputs of input of NOR gates E2 and E3 of first signals for straight, right, and left turns
NOR gates X3(=E3, J3, K3 and M3) of side), the output of NOR gates E2 and E3 and pedestrian’s signals. Fig. 5 shows
each side, because one of the inputs of of first side will depend on the output of one of such possible connections of vehicu-
AND gates is high in daytime. Low QH the three-NAND gate circuit (comprising lar and pedestrian’s signals. The complete
(during daytime) forces NOR gates J1, gates B1, B2, and B3). circuit in model form is shown in Fig. 6.
K1, and M1 to work as the inverter gate When the 6-bit counter counts from Actual-size, single side PCB for the circuit
for the other inputs. Therefore the com- 000000 to 000001, the output of the three- shown in Fig. 2 is given in Fig. 3 with its
mon input of NOR gates X2 and X3 of NAND gate circuit will be high, which is component layout in Fig. 4.

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

 CONSTRUCTION

Calibration ing the dust over the light sensor during change the time of each side of traffic
night time. Control signal for this can be light according to the strength of traffic.
Set preset VR8 in such a position that the obtained from the shift register. Further, the present circuit being only
output of comparator IC1(a) switches from Also, time-controlling variable resis- a demonstration model uses LEDs for
one state to the other at a particular in- tors VR4 through VR7 of Part II can be lights. To drive high-wattage lights, one
tensity of natural light. Variable resistors replaced by LDRs with a small light can easily boost the signals used for driv-
VR1 and VR2 can be calibrated on a time source whose light intensity varies accord- ing the LEDs to operate solidstate or
scale using the following relationships: ing to the strength of traffic on each side. electomechanical relays. ❏
VR1 = (1/120) (1.44 TNight/220) 106 – Implementation of this system requires The author is an M.Tech. from IIT, Delhi,
(122.2) 103 traffic-sensing sensors. This system will and is currently pursuing his Ph.D studies.
VR2 = (1/120) (1.44 TDay/220) 106 –
(122.2) 103
where TDay and TNight are delay times in
seconds (time interval between switching
of comparator IC1(a) and when the traf-
fic light switches its mode) corresponding
to day and night, respectively.
Variable resistors VR4 through VR7
can be calibrated on a time scale by the
following relationship:
VR (4,5,6,7) = (1/16)(1.44 T/6.8) 106 –
(122.2) 103 – 2 VR3
where T is the time allowed (in seconds)
for the side of traffic light in which the
corresponding variable resistance is con-
nected.
Possible enhancements. Stepper
motor-driven wiper can be used for clean-

ELECTRONICS FOR YOU ❚  SEPTEMBER 2001

October

2001
Circuit Ideas

2001
 CIRCUIT IDEAS

DIGITAL FAN REGULATOR S.C.

DWIV
EDI
ured as an astable multivibrator to pro-
duce rectangular clock pulses for IC5,
while NAND gates N1 and N2 generate
the active-low count enable (CE) input us-
SUNIL P.B. ing either of push-to-on switches S1 or S2
for count up or count down operation, re-

T
he circuit presented here can be connected via different values of resistors spectively, of the BCD counter.
used to control the speed of fans using a multiplexer (CD4051). Optocoupler 4N33 electrically isolates
using induction motor. The speed The value of resistance selected by the the high-voltage section and the digital
control is nonlinear, i.e. in steps. The multiplexer depends upon the control in- section and thus prevents the user from
current step number is displayed on a put from BCD up-/down-counter CD4510 shock hazard when using switches S1 and
7-segment display. Speed can be varied (IC5), which, in turn, controls forward bi- S2. BCD-to-7-segment decoder CD4543 is
over a wide range because the circuit can asing of the transistor inside optocoupler used for driving both common-cathode and
alter the voltage applied to the fan motor 4N33. The same BCD outputs from IC5 common-anode 7-segment displays. If
from 130V to 230V RMS in a maximum are also connected to the BCD-to-7-seg- phase input pin 6 is ‘high’ the decoder
of seven steps. ment decoder to display the step number works as a common-anode decoder, and if
The triac used in the final stage is on a 7-segment display. phase input pin 6 is ‘low’ it acts as a
fired at different angles to get different NAND gates N3 and N4 are config- common-cathode decoder.
voltage outputs by
applying short-dura-
tion current pulses at
its gate. For this pur-
pose a UJT relax-
ation oscillator is
used that outputs
sawtooth waveform.
This waveform is
coupled to the gate of
the triac through an
optocoupler
(MOC3011) that has
a triac driver output
stage.
Pedestal voltage
control is used for
varying the firing
angle of the triac.
The power supply for
the relaxation oscilla-
tor is derived from
the rectified mains
via 10-kilo-ohm, 10W
series dropping/limit-
ing resistor R2.
The pedestal
voltage is derived
from the non-filtered
DC through
optocoupler 4N33.
The conductivity of
the Darlington pair
transistors inside
this optocoupler is
varied for getting the
pedestal voltage. For
this, the positive sup-
ply to the LED inside
the optocoupler is

ELECTRONICS FOR YOU ❚  OCTOBER 2001

 CIRCUIT IDEAS

Optocoupler 4N33 may still conduct to output pin 3. To avoid this problem, put at zero reading in the display.
slightly even when the display is zero, adjust preset VR1 as required using a
i.e. pin 13 (X0, at ground level) is switched plastic-handled screwdriver to get no out-

ELECTRONICS FOR YOU ❚  OCTOBER 2001


STEREO TAPE HEAD PREAMPLIFIER
FOR PC SOUND CARD
T.K. HAREENDRAN
H
ere is a stereo tape head pream-
plifier circuit for your PC sound
card that can playback your
favourite audio cassette through the PC.
Audio signals from this circuit can be di-
rectly connected to the stereo-input (line-
input) socket of the PC sound card for
further processing.
The circuit is built around a popular
stereo head preamp IC LA3161. Weak
electrical signals from the playback heads
are fed to pins 1 and 8 of IC1 via DC
decoupling capacitors C1 and C6, respec-
tively. Components between pins 2 and 3
and pins 6 and 7 provide adequate
equalisation to the signals for a normal
tape playback.
CIRCUIT IDEAS
SUN
IL KU
MAR
The amplified and equalised signals
available at output pins 3 and 6 of IC1
are coupled to the inputs of line amplifier
circuit built around transistors T1 (via ca-
pacitor C5, potmeter VR1, resistor R8, and
capacitor C12) and T2 (via capacitor C10,
potmeter VR2, resistor R19, and capaci-
tor C16), respectively. Left and right play-
back levels can be adjusted by variable
resistors VR1 and VR2. The audio signals
are finally available at the negative ends
of capacitors C13 and C17.
The circuit wired around relay driver
transistor T3 serves as a simple source
selector. This is added deliberately to help
the user share the common PC sound card
line-input terminal for operating some
ELECTRONICS FOR YOU ❚  OCTOBER 2001
other audio device as well.
When the preamplifier is in ‘off’ state,
switching relay RL1 is off and it allows
connection of external signals to the sound
card. When the preamplifier is turned ‘on’,
the relay is energised by transistor T3
after a short delay determined by the val-
ues of resistor R21 and capacitor C23. On
energisation, the relay contacts
changeover the signals to internal source,
i.e. the head preamplifier.
After constructing the whole circuit
on a veroboard, enclose it in a mini me-
tallic cabinet with level controls and sock-
ets at suitable points. Use a regulated
1A, 12V DC power supply for powering
the whole circuit including the tape deck
mechanism. (A 1A, 18V AC secondary
transformer with 4700µF, 40V electrolytic
capacitor and 78M12 regulator is suffi-
cient.)
You can use any kind of tape deck
mechanism with this circuit. Use of good-
quality playback head and well-screened
wires are recommended.
 CIRCUIT IDEAS

RUNNING LIGHTS AND S.C. DWIV

EDI
XOR gate that can be used both as an

RUNNING HOLES
inverting and a non-inverting gate by ty-
ing any one of the XOR gate inputs high
and low, respectively (refer the table).
For every fourth clock to IC2, its pin
7 goes high, which, in turn, clocks IC4.
VIJAYA KUMAR P.
Since the first five outputs of IC4 are
connected together (wired ORed) using

T
his four-channel, two-mode light
chaser circuit produces effects of
running holes and running lights.
Each effect, i.e. running lights or running
astable multivibrator for generating clock diodes D3 through D7, the output at
signals for decade counter CD4017 (IC2). the tied end remains high for every five
The speed of running lights can be varied clock pulses at IC4. This output is coupled
using preset VR1. CD4030 (IC3) is a quad to one of the inputs of all the four XOR

holes, is repeated five times. Applications

include decorating photographs using
LEDs or driving 230V bulbs via triacs.
Fig. 1 shows the circuit for driving
the bulbs using triacs, while Fig. 2 is a
modification of Fig. 1 for driving LEDs
without using triacs.
In Fig. 1, timer 555 is used as an

ELECTRONICS FOR YOU ❚  OCTOBER 2001

 CIRCUIT IDEAS

gates. produce the running hole effect. And when IC2 remain as original and produce the
When the output of IC4 (Q) goes the output of IC4 (Q) goes low, XOR gates running light effect.
high, the outputs of IC2 get inverted and act as non-inverters and the outputs of

ELECTRONICS FOR YOU ❚  OCTOBER 2001

 CIRCUIT IDEAS

HEART BEAT MONITOR S.C. DWIV

EDI
used in the power output stage are freely
available. In case you use AC188/128 ger-
PRADEEP G.
manium transistors in place of BEL188
silicon transistors, replace 220-ohm resis-

H
ere is a simple and low-cost cir- beat notes as audible sound. tors with 47-ohm resistors and 680-ohm
cuit of heart beat monitor using The two BEL188 silicon transistors resistors with 1-kilo-ohm resistors.
readily available components. It
uses the piezo-electric plate of audible
piezobuzzers as the sensing device, which
can be purchased for around Rs 2 only
from component vendors.
The sensor is pressed against human
body near the heart region. It should make
a solid contact with your palm to convert
heart beat sound into low-frequency elec-
trical variations. These electrical varia-
tions are amplified by transistor T1 that
is configured as a common-emitter ampli-
fier. Amplified signals are coupled to tran-
sistor T2 for driving the audio power am-
plifier stage. The speaker reproduces heart

ELECTRONICS FOR YOU ❚  OCTOBER 2001


12V, 3A POWER SUPPLY
D. PRABAKARAN
T
his circuit provides a 12V regu-
lated power supply with output
current up to 3 amperes. It is spe-
cially designed for use with 2m handheld
rigs with linear power amplifier and CB
CIRCUIT IDEAS
S.C. DWIV
EDI
portable QRP rigs.
The circuit uses monolithic IC CA3085
voltage regulator in 8-lead TO-5 package.
Its salient features include good load and
line regulation, output current up to 100
ELECTRONICS FOR YOU ❚  OCTOBER 2001
mA (which can be increased to several
amperes with additional pass transistors),
output short-circuit protection, and lower
input voltage.
A low power dissipation is achieved
by driving external series-pass transistor
2N4241 (T1) from pin 2 of CA3085. Nor-
mal output pin 8 is returned to ground
via diodes D3 and D4 to ensure error am-
plification operation in the linear region.
Ripple rejection is approximately 50 dB
on no load and 35 dB on full load.
A 2x2x2.5cm aluminium heat sink fas-
tened onto a 1.5mm blackened aluminium
sheet of 12.5cm2 area on 2N4241 helps
the circuit in dissipating heat without ex-
ceeding maximum device ratings.
CA3085 can dissipate up to 650mW
power in free air, without any heat sink.
AFCO-make C-05-4 heat sink is suitable
for this IC. An improper heat sink may
cause device junction temperature to ex-
ceed the limit, resulting in progressive
deterioration of the device.
 CIRCUIT IDEAS

A SIMPLE TRANSISTOR S1 as per base current requirement for

the transistor. Two different coloured
(green and red) LEDs are used for indi-

TESTER
EDI cation.
DWIV
S.C. Green LED glows if the npn transis-
tor under test is good, otherwise not. Like-
wise, when a pnp transistor is tested, the
J. BALAJI glowing of red LED indicates that the

T
his simple-to-construct circuit is
useful for testing both npn and
pnp low-power transistors. It com-
prises a few resistors, LEDs, diodes, and
a mains step-down transformer.
The 230V mains voltage is stepped
down to about 6 volts before application
to the circuit. The leads of transistor un-
der test are inserted in the test terminals
(sockets) marked E, B, and C (for emit-
ter, base, and collector, respectively) ap-
propriately, i.e. the emitter of the
transistor is to be inserted in terminal E,
the base of the transistor in terminal B,
and the collector of the transistor in ter-
minal C. with the base terminal is selected with transistor is good and no glowing indi-
The resistor to be connected in series the help of a 6-position rotary switch cates that the transistor is bad.

ELECTRONICS FOR YOU ❚  OCTOBER 2001

Construction

2001

LEAD-ACID BATTERY CHARGER
WITH ACTIVE POWER CONTROL
M.K. CHANDRA MOULEESWARAN
H
igh-power lead-acid battery char-
gers usually employ constant
voltage charging method. In such
chargers the charging is monitored
against the battery terminal voltage. Con-
stant voltage at a constant current re-
sults in a very large initial current in a
‘flat’ battery and a very low current in a
partially charged battery. To overcome
this problem, the charger should be made
to vary the charging current in accordance
Fig. 1: Schematic diagram of lead-acid battery charger
CONSTRUCTION
is automatically selected at successive dif-
ferent battery terminal voltages. And when
the battery gets fully charged, the charger
switches over to trickle-charge mode.
The circuit consists of the following
sections:
1. The DC power supply section.
MAR
IL KU
SUN
with the existing terminal voltage
of the battery.
In the circuit presented here
the charging current is adjusted
against the terminal voltage in such
a way that any battery with any
level of charge can be connected to
the charger without requiring any
manual adjustment. The charging
voltage is held constant, while an Fig. 2: Charging current versus battery terminal
appropriate charging current range voltage
ELECTRONICS FOR YOU ❚  OCTOBER 2001

2. The series DC voltage regulation
section.
3. The battery status indication-cum-
charge current regulation section.
The DC power supply section. The
230V AC mains supply is connected to a
step-down transformer with a secondary
rating of 24V AC, 5A through DPDT toggle
switch S1. When switch S1 is in ‘off’ posi-
tion, the availability of mains supply is
indicated by green LED1. When switch S1
is toggled to ‘on’ position, red LED2 glows
to indicate that the charger is ‘on’. The
Fig. 3: Actual-size, single-sided PCB for battery charger
Fig. 4: Component layout for the PCB
CONSTRUCTION
four 15-kilo-ohm resistors R1, R2 and R3,
R4 in the path of LED1 and LED2, respec-
tively, are rated at 1 watt each.
The output from the secondary of
transformer X1 is rectified by the bridge
rectifier comprising 1N5408 diodes D3
through D6, rated at 800V, 3A. The recti-
fied output is smoothed by three capaci-
tors C1, C2, and C3 before being applied
to the rest of the circuit. The 4.7-kilo-ohm
resistor R6 acts as a bleeder resistance.
LED7 indicates that DC is available at
the output of this section.
ELECTRONICS FOR YOU ❚  OCTOBER 2001
The series DC voltage regulation
section. This section is configured around
power Darlington transistor TIP142 (T1)
that functions in conjunction with tran-
sistor T3 (BC549) and preset VR2 to regu-
late the output voltage from the DC volt-
age regulator section.
Since zener diode ZD1 conducts only
after the output voltage reaches 15 volts,
the output voltage needs to be adjusted
in the vicinity of 15 volts with the help of
preset VR2. When transistor T3 conducts
fully, the base of transistor T1 is pulled
towards ground via resistor R8 and
it stops conducting after the output
voltage exceeds a specific value.
Transistor T2 (also a BC549)
helps in current limit adjustments.
Low-value, high-wattage resistors
R15 (shunted by R14) through R19
connected in series form a current-
limiting resistor network at the out-
put of transistor T1. This resistor
network limits the charging current
depending on the energisation/de-
energisation state of relays RL1
through RL4 that select the cur-
rent range. The resistors are either
shorted or added by respective re-
lay contacts RY1 through RY4 de-
pending on the charging current re-
quirement from the regulator.
The battery status indica-
tion-cum-charge current regula-
tion section. In this circuit, a quad
op-amp LM324 (IC1) is wired as a
four-stage comparator to indicate
the battery voltage with the help of
four LEDs (LED3 through LED6),
while at the same time selecting
and driving corresponding relays to
set the charging current range.
The 6.8V reference voltage de-
veloped across zener diode ZD2 is
proportionately applied to the in-
verting terminals of comparators A1
through A4, while the sampled bat-
tery voltage is proportionately ap-
plied to the non-inverting terminals
of all the comparators.
Preset VR3 may be adjusted to
obtain the reference voltages as
shown in Fig. 1. Preset VR4 may be
adjusted by applying an external
fixed voltage of 10.5V, 11.5V, 12.5V,
or 13.5V across the battery’s screw
terminals, ensuring that the corre-
sponding LEDs (and relays) light
up (energise) in accordance with the
table.
 CONSTRUCTION

PARTS LIST R26-R28 - 1.2-kilo-ohm selected only when the battery has
Semiconductors: R29 - 1.5-kilo-ohm reached a safe level of terminal voltage.
IC1 - LM324 quad op-amp VR1-VR2 - 2.2-kilo-ohm preset Later, as the battery starts charging
T1 - TIP142 power Darlington VR3 - 10-kilo-ohm preset
VR4 - 15-kilo-ohm preset
and its terminal voltage starts rising, the
transistor
T2, T3 - BC549 npn transistor Miscellaneous: charging current is decreased in proper
T4-T7 - 2N2222A npn transistor RL1-RL4 - 24V DC, 500-ohm relay steps. Upon reaching the full voltage of
D1, D2, contacts at 10A DC 13.5 volts, the charger switches to the
D7-D11 - 1N4007 rectifier diodes X1 - 230V AC primary to 0-24V,
D3-D6, D12 - 1N5408 rectifier diodes 5A secondary transformer trickle charge mode with resistor R19
LED1 - Green LED S1 - DPDT toggle switch coming into the charging path. Option-
LED2 - Red LED F1 - 750mA cartridge glass fuse ally, one can switch off the charger on
LED3 - Bright yellow LED energisation of relay RL4 by just remov-
LED4, LED5 - Bright green LED
LED6, LED7 - Bright red LED In the charge characteristic curve of ing resistor R19 from the circuit. When-
ZD1 - 15V, 1W zener diode Fig. 2, it can be seen that the terminal ever the terminal voltage level of the bat-
ZD2 - 6.8V, 1W zener diode voltage is compared by the comparators tery goes low, the charger automatically
Capacitors:
C1, C2 - 2200µF, 40V electrolytic TABLE
C3 - 1000µF, 40V electrolytic LED/Relay Operation and Charging Resistance
C4 - 470µF, 25V electrolytic
C5 - 100nF ceramic Battery LED/Relay status Charging Preset
Resistors (all ¼-watt, ±5% carbon unless voltage LED3 LED4 LED5 LED resistance current
stated otherwise) /RL1 /RL2 /RL3 /RL4
R1-R4 - 15-kilo-ohm, 1W
<10.5V Off Off Off Off 1 ohm 1A
R5 - 2.2-kilo-ohm
R6 - 4.7-kilo-ohm, 0.5W 10.5V On Off Off Off 0.33 ohm 3A
R7, R10, R12 - 1-kilo-ohm 11.5V On On Off Off 0.53 ohm 2A
R8 - 100-ohm 12.5V On On On Off 1 ohm 1A
R9 - 470-ohm 13.5V On On On On 2 ohms 0.5A*
R11 - 4.7-kilo-ohm * 0.5A is taken as the trickle charging current.
R13 - 47-ohm
R14-R15 - 0.66-ohm, 3W wirewound or against the preset values and the charg- resumes charging.
fusible ing current is selected accordingly. Thus Figs 3 and 4 show the actual-size,
R16 - 0.67-ohm, 3W wirewound or a battery of any charge level can be con- single-sided PCB and the component lay-
fusible
R17 - 0.20-ohm, 3W wirewound or nected and left unattended under the con- out, respectively, of the charger circuit.
fusible trol of this charger circuit. Note. To ensure proper functioning
R18 - 0.47-ohm, 3W wirewound or When the battery is flat with termi- of the circuit, use good-quality relays and
fusible
R19 - 1.0-ohm, 1W wirewound nal voltage below 10.5 volts, the initial precise-value resistors (R14 through R24)
R20-R23 - 470-ohm, MFR 0.5% or 0.1% charging current is selected at just one with tolerance as mentioned in the Parts
R24 - 820-ohm, MFR 0.5% or 0.1% ampere because a higher initial charging List. Connect the metal housing of the
R25 - 10-kilo-ohm, MFR 0.5% or
0.1%
current may cripple both the battery and charger circuit to the earth line of the AC
the charger. A higher charging current is mains supply for personal safety. ❏

ELECTRONICS FOR YOU ❚  OCTOBER 2001


MICROCONTROLLER-BASED
DIGITAL CLOCK
A.P. PHATAK AND P.W. DANDEKAR
I
n most applications, a microcontroller
unit (MCU) can satisfy all system
requirements with no additional
integrated circuits. Due to their low
cost and a high degree of flexibility, new
powerful MCUs are finding way into
Fig. 1: The microcontroller-based digital clock circuit
CONSTRUCTION
NJA
R UPA
many applications that were previously
accomplished by mechanical means or
by combinational logic. One such applica-
tion is digital clock using Motorola’s
MC68HC705P6A that has been described
here.
ELECTRONICS FOR YOU ❚  OCTOBER 2001
Hardware
Motorola’s 4MHz 68HC705P6A (IC1) has
NA 21 input/output lines, including eight lines
of port A (PA0 through PA7), eight lines
of port C (PC0 through PC7), three lines
of port B (PB5 through PB7), and two
lines of port D (PD5 and PD7).
Fig. 1 shows the complete clock cir-
cuit. The 12V DC power supply is provided
to the input of 3-terminal LM7805 (IC2)
regulator using external AC/DC adaptor.
IC2 converts any unregulated DC voltage
between +9V and +12V to stable +5V,
which is fed to all the ICs on the board.
The +5V Vdd supply to 28-pin DIP

Fig. 2: Flow-chart for timer interrupt
IC1 is given at pin 28 and pin 14 is
grounded. A 4MHz crystal is connected
to the internal oscillator across pins 26
and 27. R4-C1 combination provides the
necessary slowly rising power-on-reset sig-
nal. It is double buffered through two in-
verter gates of 7406 (IC4) connected in
cascade to generate an active-low power-
on-reset (PONRST) signal that is con-
nected to pin 1 of IC1.
PA0 through PA7 lines form an 8-bit
bidirectional data bus that is routed to
the following destinations:
• LCD data lines D0 through D7.
• Latch 74LS374 (IC3) inputs D0
through D7 (only PA1 from IC1 is pres-
ently made use of).
• Scan columns for switch matrix
(only PA0 is presently made use of).
Port-B lines PB6 and PB7 are used
as control lines. PB6 goes to register-se-
lect (RS) input. PB6 and PB7 control sig-
nals decide the data transfer from IC1 to
LCD module and whether destination of
D0 through D7 inside the module is data
register or control register.
Since pin 5 (R/W) is connected to
ground, LCD module is always in ‘write’
mode. Thus whenever E line goes from
low to high, data present at D0 to D7
input lines is stored in the designated reg-
ister inside the display module. (EFY Lab
note. For more information and instruc-
tion set of LCD module, refer the article
CONSTRUCTION
Time signal generation
MC68HC705P6A doesn’t have any stan-
dard clock output. Therefore we are gen-
erating an interrupt every 125 ms using
the inbuilt capture/compare capabilities
of timer inside MC68HC705P6A.
The 16-bit free running counter (FRC)
rolls over every 262,144 internal clock
cycles. Its resolution with a 4MHz crystal
is 2 µs. Whenever the value of FRC matches
the value written in output compare regis-
ter (OCR), an interrupt is generated.
On entry to relevant interrupt service
routine (ISR), timer registers are re-initia-
lised so that the timer will generate the
next interrupt after current time+125 ms.
To generate a timer interrupt every
125 ms, we need to have a count differ-
on page 47 in April ’97 and caller-ID
project in April ’99 EFY issues.)
Port-D line PD5 is connected to strobe
(/clock) input pin 11 of latch 74LS374.
Whenever PD5 line makes a low to high
transition, the contents on data input pins
3, 4, 7, 8, 13, 14, 17, and 18 are latched to
output pins 2, 5, 6, 9, 12, 15, 16, and 19 of
octal latch IC3. The output of the latch
corresponding to PA1 input available at
pin 5 of IC3 is fed to open-collector in-
verter gate N3 of IC4. The output of N3
drives a piezobuzzer to provide an audio
indication. Thus the buzzer can be
switched on or off by the software. (Note.
Octal latch IC3 was originally intended
for operating a number of relays. How-
ever, since we are presently using IC3 for
latching only a single input (PA1 signal
from MCU) by taking strobe pin 11 from
low to high, readers may replace IC3 by
any simpler latch circuit, if desired).
Key switches S1 through S3 are con-
nected between scan column line PA0 and
three scan return rows PC0 through PC2
as follows:
Time key (S1) Between PA0 and PC0
Store/up key (S2) Between PA0 and PC1
Down key (S3) Between PA0 and PC2
Each of the three inputs PC0, PC1,
and PC2 has a 33-kilo-ohm pull-up resis-
tor connected between these pins and Vcc,
continued...
which ensures that the input to the port
is set to 1 when not in use. Fig. 3(a): System flow-chart
ELECTRONICS FOR YOU ❚  OCTOBER 2001

contd...
Fig. 3(b): System flow-chart
ence of 62,500 between the OCR and the
FRC, so that this count multiplied by 2 µs
per count produces a delay of 125,000 µs
or 125 ms. This is achieved by capturing
the current value of the FRC and adding
62,500 to it. The carry is ignored and the
sum is stored in the OCR. The FRC rolls
over and hence the sum without carry
ensures that the difference is maintained.
The ISR maintains four different
counters as follows:
Name Range Frequency of increment
TIME 0-7 Every 125 milliseconds
SS 0-59 Every second
MM 0-59 Every minute
HH 0-23 Every hour
In case ‘Time’ counter has become 8,
it rolls over to 0 and seconds counter (SS)
is incremented. In case, SS becomes 60,
it rolls over to 00 and minutes counter
(MM) is incremented. When MM reaches
60, it rolls over to 00 and hours counter
(HH) is incremented. When HH becomes
24, it is reset to 00. If the outcome is NO
in any of these four comparisons for limit
checking, the control exits from the ISR.
Fig. 2 shows the flow-chart for inter-
rupt subroutine called ISR_OCR.
The ISR sets four flags, namely,
125ms time over, 1-second time over, 1-
minute time over, and 1-hour time over,
CONSTRUCTION
Fig. 4: Actual-size, single-sided PCB layout for the circuit in Fig. 1
Fig. 5: Component layout for the PCB
in ‘Flagloc’ memory location. These flags
are set when the corresponding time pe-
riod is over, as indicated by rolling over
of the previous counter in the chain. These
may be used in background programs like
Main routine to test and initiate periodic
time-triggered functions.
System flow-chart (Fig. 3). Imme-
diately after switching on the equipment,
the system is initialised and the LCD
starts showing time in HH:MM:SS for-
mat. Since no time is set, the display
will start from 00:00:00. The user can set
any time by pressing ‘time’ key.
On pressing ‘time’ key, the display
shows ‘SET MIN HH:MM:SS,’ where
HH:MM:SS will normally be 00:00:00 on
power-on-reset that start incrementing.
You can set the value of minutes by us-
ELECTRONICS FOR YOU ❚  OCTOBER 2001
ing ‘up’ and ‘down’ keys.
Every closure (followed by release) of
‘up’ key causes the minutes’ value to be
incremented by one, while the closure of
‘down’ key (followed by release) causes
the minutes’ value to be decremented by
one. After you are satisfied with the value
of minutes, press ‘time’ key once again.
The unit responds by showing ‘SET
HOUR HH:MM:SS’ on the LCD. Just like
minutes, you can now set the value of
hours using ‘up’ and ‘down’ keys. After
you’re satisfied, press ‘time’ key once again.
This causes the unit to display ‘TIME
SET HH:MM:00,’ where the seconds are
automatically set to 00.
In all key closures, it is the key re-
lease operation that acts as the working
edge or trigger. Thus the actions are un-
 CONSTRUCTION

PARTS LIST dertaken by the unit when a key is of program which is used by the WINIDE
Semiconductors: pressed and then released, and not im- for programming the OTPROM/EPROM
IC1 - 68HC705P6A Motorola mediately after the key is pressed. inside the microcontroller.
microcontroller After one minute, the ‘TIME SET’ The WINIDE has an inbuilt simulator
IC2 - LM7805 regulator +5V message is cleared and only the time is that can be used to test various sub-rou-
IC3 - 74LS374 octal latch displayed. tines and logic. After testing the software
IC4 - 7406 hex inverter (open- The program shown in the flow-chart offline, hardware tests are carried out.
collector)
is an infinite loop, as the system is de- Source code. The complete code along
D1 - 1N4001 rectifier diode
Resistors (all ¼-watt, ±5% carbon unless signed to work continuously. with detailed comments is given in
stated otherwise): digclock.asm file. (EFY note. The
digclock.asm file, along with .Lst and
R1
R2, R3
- 4.7-mega-ohm
- 10-kilo-ohm
Software .S19 extensions, will be included in the
R4-R7 - 33-kilo-ohm The complete software is assembled and next month’s EFY-CD.)
VR1 - 2-kilo-ohm preset tested using WINIDE (Windows-based in- The software routines to convert bi-
Capacitors:
tegrated development environment) that nary numbers to binary-coded decimal
C1, C6 - 10µF, 16V electrolytic
C2 - 0.22µ ceramic disk
allows seamless integration of several dif- (BCD) numbers and activate LCD and au-
C3 - 1µF, 16V tantalum ferent program modules into one devel- dio indicators are included in the code,
C4, C5 - 33pF ceramic disk opment environment. Its ‘edit’ utility is but have not been explained as these are
C7 - 10µF, 35V electrolytic used to create the assembly file (.Asm) in beyond the scope of this article.
Miscellaneous: text mode. The actual-size, single-sided PCB for
LCD - LCD module (16 characters The .Asm file is created only when the digital clock is shown in Fig. 4 with
x 1 row) there are no errors and produces two files its component layout in Fig. 5. ❏
Pz1 - Piezobuzzer with extensions, namely, .Lst and .S19.
S1-S3 - Tactile switch The .Lst is a listing file in text mode that
XTL - 4MHz quartz crystal Col.(Retd.) A.P. Phatak is professor in
includes variable, addresses, code, etc. The electronics & telecommunications and P.W.
- 9 -12V, 200mA supply Dandekar is vice pesident at Impetus
source .S19 file contains information relating to
Computing, Indore
address, code/data, start and termination

ELECTRONICS FOR YOU ❚  OCTOBER 2001

November

2001
Circuit Ideas

2001

SPELLER EFFECT
SIGN DISPLAY
VIJAYA KUMAR P.
T
he circuit described here uses low-
cost and easily available IC
CD4017 to produce a speller type
light display. In such displays, each let-
ter of the sign sequentially lights up, one
after the other, until all letters are glow-
ing. After a few seconds, the letters switch
off and the cycle repeats. This circuit pro-
vides a maximum of nine channels and
therefore can be used to spell a word or
sign having up to nine characters.
Timer IC1 (555) is configured in
astable mode to produce clock signal for
triggering IC2 (CD4017). Speed of switch-
ing on the display can be controlled by
varying preset VR1.
CIRCUIT IDEAS
EDI
DWIV
S.C.
CD4017 is a decade counter having
ten outputs, of which one output is high
for each clock pulse. However, this pro-
duces running lights effect. To change this
sequence to get the speller effect, pnp
transistors T1 through T9 are wired as
shown in the figure. Nine triacs (triac 1
through triac 9) are used to drive 230V
bulbs. (In place of 230V bulbs, miniature
lamps connected in series in the form of
characters or letters can also be used, pro-
vided the voltage drop across the series
combination is 230 volts.)
When any of the outputs of IC2 goes
high, the corresponding transistor con-
nected to the output goes off. When Q0 is
ELECTRONICS FOR YOU ❚  NOVEMBER 2001
high, transistor T1 goes off and its out-
put at the collector goes low. Since the
emitter of transistor T2 is connected to
the collector of transistor T1, and collec-
tor and emitter terminals of transistors
T1 through T9 are connected in series,
all transistors next to transistor T1, i.e.
transistors T2 through T9, do not get sup-
ply and hence all their outputs go low.
Next, when Q1 output goes high, tran-
sistor T2 goes off. Thus outputs of tran-
sistors T2 through T9 remain low. Since
Q0 output at this instant is low, transis-
tor T1 is forward biased and its output
goes high to light up the first character.
Similarly, when Q2 output goes high,
Q0 and Q1 outputs are low and therefore
outputs of transistors T1 and T2 go high
to light up the first and second characters.
This process continues until all tran-
sistors turn on, making all the characters
to light up. The cycle repeats endlessly,
producing the speller type light effect.

DARKROOM TIMER
D. PRABAKARAN
T
he timer circuit described here pro-
vides a pleasant musical tone in
your darkroom at 1-second inter-
vals. The circuit takes up very little space
and can be easily converted into a metro-
nome.
Unijunction transistor (UJT) T1 func-
tioning as a relaxation oscillator triggers
CIRCUIT IDEAS
SUN
IL KU
MAR A tone signal is generated by transis-
tor T2 and R-C coupled phase-shift oscil-
lator. Part of the signal taken from the
collector of transistor T2 is coupled to a
small speaker through a transistor-radio
the phase-shift audio oscillator circuit type output transformer.
built around transistor T2, turning it on The 22-kilo-ohm value of resistor R3
and off. As capacitor C1 is charged represents a compromise between tone du-
through preset VR1 and resistor R1, the ration and intensity. You can use resis-
emitter voltage of UJT rises toward the tors having a value anywhere between 10
supply voltage. kilo-ohms and 25 kilo-ohms for different
When the durations and intensities of the output
emitter voltage signals.
becomes suffi- Since the unijunction transistor is
ciently positive, functioning as the oscillator trigger,
the emitter be- changing the values of one or more com-
comes forward bi- ponents in the UJT circuit will change
ased and dis- the rate of the tone burst. The tone fre-
charges capacitor quency can be varied by changing the
C1 through the value of any or more of capacitors C2
emitter-base 1 through C4 and resistors R5 and R6 in
(B1) junction and the phase-shift network.
resistor R2. The The primary winding of transformer
voltage drop X1 can be tuned for a slight increase in
across R2 forward the output, using capacitor values be-
biases transistor tween 0.05 and 0.25 µF for C5 by trial-
T2 and turns it and-error method. Tone pulses should be-
on. As capacitor gin about ten seconds after the unit is
C1 becomes dis- turned on. After a minute or so, adjust
charged, the cur- preset VR1 for 1-second beats by compar-
rent through re- ing the timing of the beats with the sec-
sistor R2 drops and transistor T2 is cut onds needle on your wristwatch.
off.
ELECTRONICS FOR YOU ❚  NOVEMBER 2001
 CIRCUIT IDEAS

LONG-RANGE EDI

TARGET SHOOTER
.C. DWIV
S

PRATAP CHANDRA SAHU

P
racticing target shooting using a
real gun is both expensive and
risky. Also, it is not possible for
everybody to have a gun. The circuit pre-
sented here makes you feel the excite-
ment of shooting a target situated at a
distance of more than 100 metres with-
out any risk or much expenditure.
The circuit simply uses a laser pointer
(also referred to as laser torch) as the
transmitter at the gun end. Laser point-
ers can reach a maximum of 1 kilometre
distance but it is advisable to limit the
range within, say, 200 metres.
While constructing the gun no change
has to be made in the readymade pointer.
Just tightly fit the pointer inside the toy
gun, so that the triggering switch can ac-
tivate the press-to-on button of the laser
pointer, as shown in Fig. 1.
The receiver comprises a counter-cum-
7-segment display driver IC (CD4033)
with a debouncer formed by 555 timer
and an LDR sensor at the input. The
counter works as a scoreboard and directly
shows the number of successful hits.
The LDR senses the pointer’s laser
beam and activates the monostable
multivibrator wired around 555 timer IC.
To increase the sensitively of the receiver,
the LDR current is amplified by transis-
tors T1 and T2. The timer pulse-width is
set at around 100 milliseconds so as to
work as a debouncer. The timer output is
coupled to IC CD4033.
CD4033 is a serial decade counter-
cum-7-segment decoder/driver. With ev-
ery output pulse from monostable IC1,
the count in CD4033 gets incremented by
one. Thus the output of IC2 reflects the
latest score by a competitor. Pressing re-
set switch resets the display too.
You can increase the size of the
display board manyfolds using the addi-
tional circuit shown in Fig. 3. This mul-

ELECTRONICS FOR YOU ❚  NOVEMBER 2001

 CIRCUIT IDEAS

tiplexed board avoids higher power

consumption and is necessary if you are
using the module for long-range shoot-
ing.
For each segment, you can wire up to
ten LEDs in parallel. Short the anodes of
LEDs of all segments as it is a common-
anode type display. (The output from
ULN2003 will be active-low.)
For proper functioning of the receiver,
the LDR should be kept covered in such
a way that no external light falls on it.
Further, the receiver should be fixed
at least two metres from the ground so
that the laser beam is accidentally not
directed towards anybody’s eyes. The
game can be played both in daylight as
well as at night.
Caution. Never look or stare at the
beam source and do not bounce the beam
on a mirror.

ELECTRONICS FOR YOU ❚  NOVEMBER 2001

 CIRCUIT IDEAS

ACTIVE SHORTWAVE ANTENNA ries with positive supply rail, along with
a bypass capacitor to the ground, is rec-
ommended for reducing signal loss in the
PRAVEEN SHANKER EDI power supply.
DWIV
S.C. The current consumption is well be-
low 10 mA. The transistor works well at

T
he circuit presented here boosts
weak shortwave signals so that
these can be heard with enhanced
clarity over a shortwave receiver. Further,
the receiver doesn’t require any physical
connection as its placement in the vicin-
ity (within 6 to 7 cm) of the circuit will
suffice. The circuit works well over a wide
range of supply voltage from 3 volts to 12
volts.
Low-noise transistor T1 (BF494 or
BF495) is connected as shown in the fig-
ure. Resistor R1 gives the DC bias to T1.
R1’s value may lie anywhere between l00
kilo-ohms and 22 kilo-ohms; it determines
the quiescent base-emitter current for
transistor T1. Resistor R2 limits the cur-
rent flowing through transistor T1 and,
in conjunction with capacitor C2, deter-
mines the operating point for its stable
operation.
The number of turns in inductor L1
would have to be reduced as operation
area shifts towards the upper end of the
high-frequency band. A 180µH RFC in se-
maximum supply and so reduction of re-
sistor R1’s value below 22 kilo-ohm is not
recommended, as otherwise the transis-
tor may burn off.
This circuit works satisfactorily for
boosting signals in 13m-49m band. How-
ever, as the frequency increases, its per-
formance deteriorates. The same happens
when the frequency decreases below that
of the shortwave range. For input use a
long wire as the antenna, while the out-
put antenna wire may be limited to about
30 cm.
Note. The circuit is prone to self-
oscillations if the aerial (input) wire picks
up stray radiations from the power sup-
ply wires or from the output. So keep the
power supply and output wires well iso-
lated from the input.

ELECTRONICS FOR YOU ❚  NOVEMBER 2001

 CIRCUIT IDEAS

POWER SUPPLY FOR S.C. DWIV

EDI

WALKIE-TALKIES
PRADEEP G.

H
ere is a simple power supply cir-
cuit that can be used for citi-
zen-band and VHF walkie-talk-
ies of power rating up to 10 watts. The
circuit uses a step-down transformer, fol-
lowed by bridge rectifier, filter, regula-
tor, and current booster stages.
A pnp power transistor is added to
the circuit to increase its current sourc-
ing capabilities. Regulator 7812 can sup-
port around 100 mA current. When the
current flowing through R1 nears 100mA
value, the voltage (>0.65V) across the
emitter-base junction makes transistor T1
to conduct and provide a path for addi-
tional current.
The circuit can source around one am-
pere of current at 12+1.4 volts=13.4 volts. Both the regulator IC and the power tran- sistor must be mounted on heat sinks.

ELECTRONICS FOR YOU ❚  NOVEMBER 2001


HIGH-PERFORMANCE
INTERRUPTION DETECTOR
JUNOMON ABRAHAM
T
he circuit presented here detects
interruption in security systems.
Its features include no false trig-
gering by external factors (such as sun-
light and rain), easy relative positioning
of the sensors and alignment of the cir-
cuit, high sensitivity, and reliability.
The circuit comprises three sections,
namely, transmitter, receiver, and power
supply. The transmitter generates modu-
lated IR signals and the receiver detects
the change in IR intensity. Power supply
provides regulated +5V to the transmit-
ter and the receiver.
The power supply and the speaker are
kept inside the premises while the trans-
mitter and the receiver are placed oppo-
site to each other at the entrance where
the detection is needed. Three connections
(Vcc, GND, and SPKR) are needed from
the power supply/speaker to the receiver
section, while only two connections (Vcc
and GND) are required to the transmit-
ter.
The transmitter is basically an astable
multivibrator configured around NE555
(IC3). Its frequency should match the fre-
quency of the detector/sensor module (36
kHz for the module shown in figure) in
the receiver. The transmitter frequency
CIRCUIT IDEAS
S.C.
DWIV
EDI
is adjusted by preset VR2. For making
the duty cycle less than 50 per cent, di-
ode 1N4148 is connected in the charging
path of capacitor C7.
The output of astable multivibrator
modulates the IR signal emitted from IR
LEDs that are used in series to obtain a
range of 7 metres (maximum). To increase
the range any further, the transmitted
power has to be raised by using more
number of IR LEDs. In such a case, it is
advisable to use another pair of IR LEDs
and 33-ohm series resistor in parallel with
the existing IR LEDs and resistor R5
across points X and Y.
The receiver unit consists of a
monostable multivibrator built around
NE555 (IC2), a melody generator, and an
IR sensor module. The output of the IR
sensor module goes high in the standby
mode or when there is continuous pres-
ence of modulated IR signal.
When the IR signal path is blocked,
the output of the sensor module still re-
mains high. However, when the block is
removed, the output of the sensor mod-
ule briefly goes low to trigger monostable
IC3. This is due to the fact that the sen-
sor module is meant for pulsed operation.
Thus interruption of the IR path for a
ELECTRONICS FOR YOU ❚  NOVEMBER 2001
brief period gives rise to pulsed operation
of the sensor module.
Once monostable IC2 gets triggered,
its output goes high and stays in that
state for the duration of its pulse width
that can be controlled by preset VR1.
The high output at pin 3 of the monostable
makes the musical IC to function. Volt-
age divider comprising R2 and R3 reduces
the 555 output voltage to a safer value
(around 3V) for UM66 operation. The du-
ration of the musical notes is set by pre-
set VR1 as stated earlier.
For proper operation of the circuit,
use 7.5V to 12V power supply. A battery
back-up can be provided so that the cir-
cuit works in the case of power failure
also. Potmeter VR3 serves as a volume
control.
The transmitter, receiver, and power
supply units should be assembled sepa-
rately. The transmitter and the receiver
should have proper coverings (booster) for
protection against rain. The length of the
wire used for connecting the IR sensor
module and IR LEDs should be minimum.
Note. The heart of the circuit is the
IR sensor module (usually used in VCRs
and TVs with remote); the circuit works
satisfactorily with various makes of sen-
sors. The entire circuit can be fixed in
the same cabinet if the connection wires
to the sensors are smaller than 1.5
metres. The reflection property of IR sig-
nals can also be used for small-distance
coverage.
Construction

2001
 CONSTRUCTION

AMPLITUDE MEASUREMENT OF receive input pulses greater than 100 mV

(which is the same as the reference volt-

SUB-MICROSECOND PULSES
age set for comparator IC3, LM319) but
less than or equal to 10 volts.
With switch S1 closed, the input pulse
amplitude may be anywhere between 1
NA volt and 100 volts. The closure of the
ANIL KUMAR MAINI ANJA
RUP switch causes division of the input volt-
age by a factor of 10 due to the arrange-

A
pulse or a repetitive train of
pulses is one of the most fre-
quently encountered electronic
signals, and the conventional way to de-
termine its peak amplitude is to have an
oscilloscope display of the waveform. An
oscilloscope that has the required band-
width to correctly display sub-microsec-
ond-wide pulses is an expensive instru-
ment, and is often beyond the reach of
most electronics enthusiasts, hobbyists,
and small-scale units. The circuit pre-
sented here allows you to measure the
peak amplitude of a single pulse as well
as of a repetitive train of pulses with a
conventional multimeter.
The circuit is capable of measuring
peak amplitude of pulses as narrow as
100 nanoseconds (ns) up to a maximum
of 100V amplitude. There is practically
no limit on the maximum value of the
pulse width. It can also be used to mea-
sure the peak amplitude of a repetitive
pulsed waveform as long as the time in-
terval between two successive pulses is
greater than 100 microseconds (µs).

The circuit
The pulse under measurement is fed to
the input of a cascaded arrangement of
two unity-gain peak detection stages built
around IC1 and IC2 using high-speed op-
amps AD829, as shown in Fig. 1. The op-
amp has a guaranteed unity-gain band-
width of 120 MHz and a slew rate of 230
V/µs, and it is capable of driving highly
capacitive loads. This makes it ideal for
receiving input pulses as narrow as 100
ns. D1 and D2 (1N914) are high-speed
switching diodes having a response time
of the order of 2 ns to 3 ns.
The input pulse gets stretched to
about 10 µs at the output of the first peak-
detection stage built around IC1 and to
about 100 µs at the output of the second
peak-detection stage built around IC2.
With switch S1 open, the circuit can Fig. 1: Circuit for measuring sub-microsecond pulses

ELECTRONICS FOR YOU ❚  NOVEMBER 2001

 CONSTRUCTION

feeding the
same to the
analogue in-
put of IC5
(ADC-type
AD0808). This
ensures that
for the maxi-
mum input
pulse ampli-
tude of 100
volts, the ADC
analogue in-
put is limited
to 5 volts,
which is the
maximum am-
plitude it can
accept.
The out-
put of the first
peak detector
stage after a
division by a
factor of 2 by
the arrange-
ment of resis-
tors R11 and
R12 feeds
Fig. 2: Waveforms at various points of the circuit comparator
LM319 (IC3).
ment of resistors R1 through R3. The leading edge of the pulse output from
The peak amplitude of the stretched the comparator coincides with the lead-
pulse at the output of the second peak ing edge of the input pulse. The leading-
detector is the same as the input pulse edge comparator output triggers monoshot
peak amplitude. This output amplitude is 74121 (IC4) to produce a 1µs pulse (as
halved by resistors R9 and R10 before determined by timing components R17-

Fig. 3: Actual-size, single-side PCB layout for the circuit

ELECTRONICS FOR YOU ❚  NOVEMBER 2001

 CONSTRUCTION

PARTS LIST
Semiconductors:
IC1, IC2 - AD829 op-amp
IC3 - LM329 comparator
IC4 - 74121 monostable
multivibrator
IC5 - AD0808 analogue-to-digital
converter
IC6 - DAC0808 digital-to-
analogue converter
IC7 - LF356 op-amp
IC8 (N1-N3) - 74HCT04 hex inverter
IC9 (N4-N7) - 7400 NAND gate
D1, D2 - 1N914 high-speed switch-
ing diode
ZD1 - 2.5V zener diode
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1, R2 - 18-kilo-ohm
R3, R16 - 1-kilo-ohm
R4 - 12-kilo-ohm
R5, R6 - 22-kilo-ohm
R7, R8 - 15-kilo-ohm
R9-R12 - 100-kilo-ohm
R13 - 470-ohm
Fig. 4: Component layout for the PCB R14 - 220-kilo-ohm
R15, R18, R19,
C10) at its Q-output, with its leading edge DAC output, which is a latched DC cur- R24, R25 - 10-kilo-ohm
R17 - 2.2-kilo-ohm
coinciding with the leading edge of the rent, is converted into a proportional volt- R20, R21 - 2.7-kilo-ohm
input pulse. age in the current-to-voltage circuit built R22 - 4.7-kilo-ohm
The monoshot output is passed around op-amp LF356 (IC7). This DC volt- R23 - 33-kilo-ohm
through an appropriate NAND gate logic age is connected to the multimeter for VR1 - 50-kilo-ohm preset
circuit built around 7400 (IC9) and it acts indication of peak amplitude of the input Capacitors:
as the start-of-conversion pulse for ana- pulse to the circuit. Potentiometer VR1 is C1, C2, C4, C5,
logue-to-digital converter IC5 (ADC0808). meant for calibration. C7-C9, C11-C17
C19 - 0.1µF ceramic disk
The NAND logic is used here to incorpo- C3, C10 - 0.001µF ceramic disk
rate the reset feature.
The clock generator circuit for IC5 is
Operation C6
C18
- 0.01µF ceramic disk
- 56 pF ceramic disk
built around 74HCT04 (IC8) to provide Every time there is a pulse at the input, Miscellaneous:
1MHz clock. The clock frequency is de- there is a stretched pulse appearing at S1, S2 - On/off switch (SPST)
cided by R24, R25, and C18. The latched the analogue input of the ADC, with its Meter - Multimeter
digital output from IC5 feeds the corre- leading edge coinciding with the leading
sponding inputs of DAC0808 (IC6). The edge of the input pulse. Fig. 2 shows wave- the analogue input is already present on
forms available at vari- the relevant input at the start of conver-
ous test points marked A, sion.
B, C, D, and E in the cir- The latched digital output from the
cuit shown in Fig. 1. ADC feeds the corresponding inputs of the
Also, there is a start-of- DAC0808 (IC6) as stated earlier. The out-
conversion pulse appear- put of the DAC, after conversion into the
ing at the relevant input proportional voltage by LF356 (IC7), is
of the ADC. The conver- fed to the multimeter (set to appropriate
sion starts at the trail- DC voltage scale) for measurement of
ing edge (test point E) of peak pulse amplitude. Potentiometer VR1
this pulse 1 µs after the is used for calibration.
leading edge of the input The display holds the peak amplitude
pulse. of the last pulse until it is reset using
Since the stretched switch S2 or it is updated by another pulse
pulse is about 100µs at the input. The accompanying photo-
wide, the peak amplitude graph shows the assembled circuit that
of the pulse 1 µs later is the author used for performance evalua-
almost the same as the tion.
actual peak amplitude. An actual-size, single-side PCB for the
At the same time, this circuit is shown in Fig. 3 and its compo-
Photograph of author’s prototype small delay ensures that nent layout in Fig. 4. ❏

ELECTRONICS FOR YOU ❚  NOVEMBER 2001


AUTOMATIC SUBMERSIBLE
PUMP CONTROLLER
K.C. BHASIN
A
number of construction projects as
well as circuit ideas for water-/
fluid-level control have appeared
in EFY over the years, but so far no dedi-
cated project has appeared for automat-
ing the control of submersible water
pumps. Looking into the demand for such
a project from readers, we present here a
circuit for automating the operation of an
electrical submersible pump (ESP) based
on the minimum and the maximum lev-
els in the overhead tank (OHT). This cir-
Fig. 1: Line diagram of control panel for manual operation of ESP motor
cuit can be interfaced to the existing
manual control panel of an ESP and can
also be used as a standalone system after
minor additions.
ESP basics
Electrical submersible pumps are single-
or multiple-stage radial-flow pressure se-
ries impeller pumps that are close coupled
to the motor for low and medium heads.
These find applications in domestic, in-
dustrial, irrigation, air-conditioning, and
various other systems.
The ESPs are classified by the bore
diameter (which generally varies from 100
mm to 200 mm), horse-power (from about
0.5 HP to 40 HP), and discharge rate (typi-
cally 120 litres per minute for 0.5 HP to
about 2000 litres per minute for 40 HP).
These are run at a fixed speed, which is
CONSTRUCTION
MAR
IL KU
SUN
2850 rpm typically.
The ESP body is made of cast iron or
stainless steel. For low and medium
range, one can use 3-phase or split-phase
(also referred to as 2-phase) supply. ESPs
of 3 HP or higher rating invariably use 3-
phase supply.
Let us consider a typical case of 1.5HP
ESP with 100mm bore diameter, using a
split-phase motor. The motor draws a run-
ning current of 10 to 11 amp, while the
starting current is around 2.5 to three
times the running current value.
To obtain a higher initial torque, the
run winding is connected in series with a
parallel combination of 120-150µF, 230V
AC bipolar paper electrolytic capacitor and
72µF, 440V AC run-mode capacitor. Af-
ter two or three seconds of running, when
the motor has picked up sufficient speed,
the start capacitor goes out of the circuit
because of the opening of the
centrifugal switch inside the TRUTH TABLE FOR RELAY OPERATION
motor, while the run capaci- Water level
tor stays in the circuit per- in tank
manently. For ESPs that Below
don’t have an integral cen- low level
trifugal switch arrangement, Above
a dual-section start switch low level
(explained later) can be used but below
to perform the function of the high level
centrifugal switch. Reaches
high level Yes
For the split-phase mo-
ELECTRONICS FOR YOU ❚  NOVEMBER 2001
tor, the run capacitor value can be calcu-
lated using the simple thumb rule (70 µF
per HP), while the start capacitor value
may be determined from Table I.
Manual operation of ESP motor
(Fig. 1). The control panel comprises an
isolator switch, push-to-on single-/dual-sec-
tion ‘start’ button, push-to-off ‘stop’ but-
ton, a triple-pole moulded case circuit
breaker (MCCB) for motor protection with
magnetic trip and resetting facility (with
an adjustable current range of 12 to 25
amperes), start and run capacitors, am-
pere-meter, voltmeter, neon indicators, etc.
(Note. The MCCBs used for motor
control are termed as motor circuit pro-
tectors (MCPs). These are classified/cata-
logued by number of poles, continuous
ampere rating, and magnetic trip range
(current). For details, you may visit Cut-
ler-Hammer’s Website or contact Bhartia
Cuttler-Hammer dealers.)
Fig. 1 shows a simplified control panel
diagram, along with ESP motor wiring.
The ‘start’ pushbutton (green), which is
normally open, and the ‘stop’ pushbutton
(red), which is normally closed, are in se-
ries with the live or phase line.
The isolator switch is normally in ‘on’
position. When ‘start’ button is momen-
tarily pressed, the contactor energises via
the closed contacts of ‘off’ button. One of
the contact pairs of the contactor is used
as the hold contact to shunt ‘on’ button
and provide a parallel path to the
Motor rating Start capacitor value (µF)
in HP 230V AC (working)
275V AC (surge)
1/6 20-25
1/5 30-40
1/4 40-60
1/3 60-80
1/2 80-100
3/4
1
100-120
120-150
1½ 150-200
2 200-250
Relay operation (2.5 – 3 sec.) Pump motor
RL1 (stop) RL2 (Start) operation
No Yes Starts
No No Remains on
No Stops

Fig. 2: Circuit diagram for automatic control of ESP motor via control panel (Fig. 1)
contactor coil, which thus latches.
The supply to the motor gets completed
via the other N/O contacts of the contactor
and the pump motor starts. When the mo-
tor gains sufficient speed (around 80 per
cent of the normal running speed), the
centrifugal switch opens to take the start
capacitor out of the circuit and only the
run capacitors (2x36 µF) permanently stay
in series with one of the two stator wind-
ings of the ESP motor.
In case the ESP is not provided with
an integral centrifugal switch, a second
Fig. 3: Actual-size, single-sided PCB layout for Fig. 2
CONSTRUCTION
section in ‘start’ button (shown in light
shade in Fig. 1) can be used to shunt
points ‘E’ and ‘F’. Since this switch sec-
tion has no hold on contacts, the start
capacitor will go out of circuit as soon as
‘start’ button is released. The motor can
be switched off by momentarily depres-
sion of ‘off’ button, which interrupts the
supply to the contactor coil.
To interface the control circuit shown
in Fig. 2, we use circled points A and B
(in parallel with ‘on’ button) and C and D
(formed by disconnecting one of the wires
ELECTRONICS FOR YOU ❚  NOVEMBER 2001
going to ‘off’ button terminal, i.e. in se-
ries with ‘off’ button). Points E and F will
be used if the ESP does not have an inte-
gral centrifugal switch.
It may be recalled, by referring to Fig.
1 of the project ‘Auto Control for 3-phase
Motor’ published in EFY’s June issue, that
wiring of ‘on’ and ‘off’ buttons of 3-phase
(4-wire system) and split-phase motors are
identical. Hence the control circuit de-
scribed here can equally be used for 3-
phase motors of up to about 10 HP. For
motors of higher HP, one must use star-
delta type starter configuration.
The circuit
As shown in Fig. 2, the 230V AC mains
(tapped from the same points from which
it is fed to the control panel of Fig. 1) is
stepped down to 12V-0-12V by trans-
former X1. The rectified output smoothed
by capacitor C1 is used for operation of
heavy-duty 24V, 250-ohm relays RL1 and
RL2 having contact rating of 30 amp. The
relay contacts identified by letters ‘A’
through ‘F’ in Fig. 2 are to be connected
to identically marked points in Fig. 1.
Note that point C in Fig. 1 is created

by breaking the connection going to point
D on the ‘stop’ switch. We have used re-
lay RL1 with single changeover contacts.
If you need higher current rating, use re-
lays with double changeover contacts by
interconnecting N/C, N/O, and pole of one
set to the corresponding terminals of the
other set. The circuit, except for the relay
drivers, is operated with regulated +12V
supply developed across capacitor C2.
The +12V supply is fed to the com-
mon probe in the overhead tank/storage
tank via 10-kilo-ohm resistor R1 and di-
ode D9. Low-level and high-level probes
are connected to the input of CMOS in-
verter gates N3 and N1, respectively, via
10-kilo-ohm resistors.
The final low-level output at pin 10 of
gate N5 goes high when the water level
in the overhead/storage tank is below the
low-level probe. The final high-level out-
put at pin 4 of gate N2 goes high as soon
as the water touches the high-level probe.
Both IC1 and IC2 have been config-
ured as monostables with a pulse width
of about 2.5 to 3 seconds. This period is
found to work optimally for ‘start’ and
‘stop’ switch operation of the manual con-
trol panel. The respective monostables for
low level (IC2) and high level (IC1) get
triggered via transistors T2 and T1 when
the final output at pin 10 of gate N5 or
pin 4 of gate N2, respectively, goes high.
The connection of reset pins of IC2
and IC1 to the outputs of gates N1 and
N2, respectively, ensures that no false
triggering of monostables takes place due
to the noise generated during changeover
of relay contacts, and also that the two
relays never operate simultaneously.
In the case of mains failure, the pump
stops if it was already running. When the
mains supply resumes, the pump starts
only when the water goes below the low
Fig. 4: Component layout for the PCB
CONSTRUCTION
level. In such a situation, you can restart PARTS LIST
the motor by manual operation of ‘start’ Semiconductors:
button on the control panel. IC1, IC2 - NE555 timer
The connections for the ammeter and IC3 - CD4049 hex inverter/buffer
the voltmeter, not shown in Fig. 1, can be T1, T2 - BC548 npn transistor
T3, T4 - BD139/SL100 npn transistor
made easily. Connect the voltmeter across D1-D4, D7-D9 - 1N4007 rectifier diode
the incoming live and neutral lines, and D5, D6 - 1N4001 rectifier diode
insert the ammeter in series with the stop ZD1 - 12V, 1W zener diode
switch by breaking the live line connec- Resistors (all ¼-watt ±5% carbon unless
tion after the stop switch. stated otherwise)
Transformer, relays, switches, fuse, R1, R3, R5,
R7, R9, R12,
and neon indicator (with integral resis-
R14 - 10-kilo-ohm
tor) are to be mounted on the cabinet. R2, R6, R11,
R15-R17 - 1-kilo-ohm
R4, R13 - 220-kilo-ohm
Precautions R8, R10 - 330-kilo-ohm
R18 - 330-ohm
The following are the vital points to be
Capacitors:
borne in mind during wiring, assembly,
C1 - 470µF, 63V electrolytic
and installation: capacitors
1. One-watt resistor R18 should be C2 - 470µF, 25V electrolytic
mounted leaving some space below it. capacitors
2. Use multistrand insulated copper C3, C7 - 47µ, 25V electrolytic
capacitors
wires of 15-amp rating for taking connec-
C4, C6 - 0.01µF ceramic disk
tions from relay terminals and terminate C5, C8 - 10µF, 25V electrolytic
them on a tag block, marking each termi- capacitors
nal properly. Similarly, terminate the Miscellaneous:
points to be extended to the OHT/storage X1 - 230V AC primary to 12V-0-
tank on a tag block (TB) using 25-28SWG 12V, 1amp
wire, marking them suitably. Secondary transformer
L1 - NE2 (neon bulb with inbuilt
3. Mount the relays inside the body of resistor)
a suitable metallic enclosure. The enclo- S1 - On/off switch
sure should be properly earthed via the F1 - 3amp fuse
earth lead of the mains. Also mount the RL1 - 24V, 250-ohm, 1 c/o relay,
step-down transformer inside the same 30A contact rating
enclosure/cabinet. Use a TB for incoming
live, neutral, and earth connections from rect ratings.
the mains (to be taken from the manual 5. For probes, use stainless steel rods
control panel of ESP motor). of about 10cm length and 5 to 8 mm di-
4. After assembly, position the cabi- ameter with arrangement for screwing the
net as close to the manual control panel telephone-type 25/26 SWG wire to be used
of ESP motor as possible and extend con- for extending the probes’ connections to
nections from tag blocks for relay and the circuit. Teflon-insulated wires are,
power supply to the corresponding points, however better as they would last longer.
as explained earlier, using cables of cor- The joint may be covered by epoxy.
6. The probes can be hung from the
lid of the tank to appropriate levels using
the same wire. Make sure that the com-
mon probe goes up to the bottom of the
tank/storage tank.
7. All the wires from tank to the TBs
in the cabinet should be routed in such a
way that they do not interfere with any
mains wiring. The length of the wires
hardly matters as the CMOS gates used
for terminating the wires from probes
have very high input impedance.
EFY note. The above circuit is being
used with ESP motor control panel at EFY
head office and is performing satisfacto-
rily for over two months now. ❏
ELECTRONICS FOR YOU ❚  NOVEMBER 2001
December

2001
Circuit Ideas

2001

DIGITAL RELAY TESTER
FOR RAX AND MAX
KRISHNA SHARMA
T
his high-speed relay tester is in-
tended for testing 12V DC 2C/O
(changeover) and 4C/O PCB-
mounted relays used in RAX (small-
capacity rural automatic exchange) and
MAX (main automatic exchange) of C-
DOT origin. It is a reliable tool for test-
ing relays in bulk. For other than 2C/O
and 4C/O contact relays, slight modifica-
tion in the circuit is required.
As soon as the relay is inserted in 28-
pin ZIF socket and test pushbutton S2 is
pressed, the tester displays ‘pass’ or ‘fail’
on 7-segment display. If the relay coil is
open or N/O and N/C contacts are not
CIRCUIT IDEAS
DWIV
EDI
S.C.
functioning as they should during oper-
ate and release conditions, the tester im-
mediately displays ‘fail’ on 7-segment dis-
play. If the relay under test is good, the
display shows ‘pass’ on 7-segment display.
When the mains supply is connected
to the circuit by closing switch S1, 5V DC
supply goes to the ICs, transistors (collec-
tors), and common points (poles) of the
relay under test, and 12V DC supply goes
to one of the terminals of the coil of relay
under test. The outputs from four N/C
and four N/O contacts are alternately ap-
plied to N1 and N2 gates, respectively, of
dual 4-input AND gate IC3 (74LS21).
ELECTRONICS FOR YOU ❚  DECEMBER 2001
The high output of gate N1 goes to
pin 1 of gate N3 of IC4 (7400), while the
low output of gate N2 goes to pin 2 of
gate N3 of IC4. As a result, the output of
gate N3 becomes high and transistor T1
conducts to complete the path for supply
to the coil of the relay under test.
For a good relay, the output of gate
N4 is high before its energisation. After
energisation of the relay, the output of
gate N3 remain high whereas the output
of gate N4 goes low. This signal is in-
verted by gate N5 to display ‘pass’. The
output of gate N5 is further inverted by
gate N6 to display ‘fail’.
The common segments of ‘pass’ and
‘fail’ characters are illuminated by OR gat-
ing via diodes D5 and D6, while exclusive
‘pass’ and ‘fail’ segments are illuminated
directly through resistors R12 and R13
(whichever is high), respectively.
For testing 2C/O relays, keep the knob
of push switch S3 (wiring of S3 to relay
socket is shown separately) pressed to by-
 CIRCUIT IDEAS

pass two C/O contacts out of four C/O tester. pressed.

contacts. 2. Insert the relay to be tested into 4. Press test switch S2 and observe
The test procedure is summarised be- ZIF socket and lock it. the display for ‘pass’/ ‘fail’.
low: 3. For 4C/O relay leave knob S3 re- 5. Unlock ZIF socket and segregate
1. Switch on the power supply to the leased, and for 2C/O relay keep the knob the relay as per the result.

ELECTRONICS FOR YOU ❚  DECEMBER 2001


DECORATIVE SIGNBOARD
PRATAP CHANDRA SAHU
T
his eye-catching signboard can be
used for special occasions such as
birthdays and marriage ceremo-
nies. The characters in the display board
are illuminated one by one, each for one
second. After the last character is illumi-
nated, the entire board gets illuminated
for 4 to 5 seconds. The above two se-
quences are repeated continuously.
Timer 555 (IC1) generates 1Hz pulses,
which are applied to decade-counter
CIRCUIT IDEAS
EDI
DWIV
S.C.
CD4017B (IC5). The output from pin Q9
of IC5 triggers 4- to 5-second (pulse width)
monostable multivibrator IC2. The out-
put of IC2 is ANDed in gate A1 with
100Hz stepped down/pulsating DC sup-
ply available at the output of the bridge
rectifier comprising diodes D1 through D4.
The output of AND gate A1 drives second
decade counter IC4, whose outputs (Q1
through Q8) are ORed with the corre-
sponding outputs of first counter IC5.
ELECTRONICS FOR YOU ❚  DECEMBER 2001
(Note. Only eight of the ten outputs of
CD4017s have been used.)
Driving characters at 1 Hz ensures
that the characters are illuminated one
by one for one second each. Similarly,
100Hz signal driving IC4 ensures that the
characters are refreshed rapidly for a con-
tinuous glow effect due to persistence of
vision. AND gate A2 is used to block 1Hz
signal reaching the first counter (IC5)
while the second counter (IC4) is active,
i.e. when the output of IC2 is high. When
IC2 output goes low after 4-5 seconds, it
enables gate A2 to pass 1Hz clock to the
first counter (IC5) and disables the sec-
ond counter (IC4) via its reset pin 15.
Transistor T1 acts as an inverter.

For illuminating more than one mes-
sage, use two rows of characters wired
reverse to each other. This sequence of
characters in opposite directions gives a
special effect.
The characters can be made by wiring
CIRCUIT IDEAS
LEDs/torch bulbs (6V, 200mA type) in se-
ries/parallel combination or densely
painted glass or transparent plastic illu-
minated by torch bulbs. The bulbs should
be placed behind each painted character.
Each of the eight outputs of ULN2803
ELECTRONICS FOR YOU ❚  DECEMBER 2001
can sink a maximum of 500 mA at supply
voltage of up to 50 volts.
Note. The supply for ULN2803 can be
a separate one or the same as used for the
rest of the circuit. However, ensure the
ground reference is same in both the cases.
 CIRCUIT IDEAS

OVERLOAD PROTECTOR IL KU
MAR
ward voltage drop at the base-emitter
junction of transistor T1), it causes for-
SUN

WITH RESET BUTTON

ward biasing of transistor T1. This re-
sults in the collector of transistor T1 to
be pulled down to ground and trigger
IC555, which is connected in bistable
VIJAY KUMAR P. mode.
The output of IC1 causes overload in-

I
n applications like inverters and transistor inside the optocoupler senses dicating LED1 to glow and forward bi-
UPS, the load must not exceed the this voltage and its collector current in- ases transistor T2 to energise relay RL1.
rated output power since it can cause creases proportionally. When the current Once the output of bistable IC1 goes high,
excess heating of output transformer reaches the required designed value, volt- it continues to remain high, unless reset
windings and active driving devices and age drop across resistor-preset combina- pushbutton S1, which is connected be-
thereby damage them.
The circuit presented here can
be used as overload protector for
inverters or as an electronic fuse
in AC mains supply. The mains
supply to the load is routed via
the the N/C (normally closed) con-
tacts of relay RL1. In an inverter,
the relay contacts could be used
as ‘inverter oscillator’ on/off con-
trol. Whenever overload occurs, it
inhibits inverter oscillator circuit,
which, in turn, stops generation
of power.
Resistor R1 is used as the
overload sensing element. When
the load exceeds the maximum
rated value, it draws current in
excess of its rated value. This
causes the potential drop across resistor tion R3-VR1 also increases. (Note. The tween Vcc and threshold terminal (pin 6)
R1 to increase. An optocoupler is used to power dissipated in 1-ohm resistor for of timer 555, is pressed. On pressing S1,
sense this voltage drop. The optocoupler, 500W load is just 2.1 watts, which is neg- a high pulse is applied to the threshold
in addition, isolates the AC mains part ligible compared to the maximum power pin that resets the flip-flop output to low
from the rest of the circuit physically. rating of the load. To use this circuit for state. The circuit can be reset after re-
Resistor R1 is selected as 1 ohm for 1kW load, select R1 as 0.5-ohm, 10W.) moving unwanted loads.
230V, 500 watts (max.) load capacity. Overload limiting point can be set by Note. Since the circuit is very sensi-
When the load just exceeds 500 watts, preset VR1. When the potential at wiper tive, fluctuations in AC mains can also
the current through R1 is approximately of preset VR1 becomes greater than trigger the circuit undesirably. This ef-
2.1 amperes, producing a potential differ- VZ+VBE (where VZ is the breakdown volt- fect can be eliminated by using 4.7µF by-
ence of 2.1 volts across R1. The inbuilt age of zener diode ZD1 and VBE the for- pass capacitor C1 as shown in the figure.

ELECTRONICS FOR YOU ❚  DECEMBER 2001


FASTEST FINGER
FIRST INDICATOR
P. RAJESH BHAT
Q
uiz-type game shows are increas-
ingly becoming popular on tele-
vision these days. In such games,
fastest finger first indicators (FFFIs) are
used to test the player’s reaction time.
The player’s designated number is dis-
played with an audio alarm when the
player presses his entry button.
The circuit presented here determines
as to which of the four contestants first
pressed the button and locks out the re-
maining three entries. Simultaneously, an
audio alarm and the correct decimal num-
ber display of the corresponding contes-
tant are activated.
CIRCUIT IDEAS
DWIV
EDI
S.C.
When a contestant presses his switch,
the corresponding output of latch IC2
(7475) changes its logic state from 1 to 0.
The combinational circuitry comprising
dual 4-input NAND gates of IC3 (7420)
locks out subsequent entries by produc-
ing the appropriate latch-disable signal.
Priority encoder IC4 (74147) encodes
the active-low input condition into the cor-
responding binary coded decimal (BCD)
number output. The outputs of IC4 after
inversion by inverter gates inside hex in-
verter 74LS04 (IC5) are coupled to BCD-
to-7-segment decoder/display driver IC6
(7447). The output of IC6 drives common-
ELECTRONICS FOR YOU ❚  DECEMBER 2001
anode 7-segment LED display (DIS.1,
FND507 or LT543).
The audio alarm generator comprises
clock oscillator IC7 (555), whose output
drives a loudspeaker. The oscillator fre-
quency can be varied with the help of
preset VR1. Logic 0 state at one of the
outputs of IC2 produces logic 1 input con-
dition at pin 4 of IC7, thereby enabling
the audio oscillator.
IC7 needs +12V DC supply for suffi-
cient alarm level. The remaining circuit
operates on regulated +5V DC supply,
which is obtained using IC1 (7805).
Once the organiser identifies the con-
testant who pressed the switch first, he
disables the audio alarm and at the same
time forces the digital display to ‘0’ by
pressing reset pushbutton S5.
With a slight modification, this cir-
cuit can accommodate more than four con-
testants.

CONDENSER MIC
AUDIO AMPLIFIER
D. PRABAKARAN
T
he compact, low-cost condenser
mic audio amplifier described here
provides good-quality audio of 0.5
watts at 4.5 volts. It can be used as part
of intercoms, walkie-talkies, low-power
CIRCUIT IDEAS
SUN
IL KU
MAR
transmitters, and packet radio receivers.
Transistors T1 and T2 form the mic
preamplifier. Resistor R1 provides the nec-
essary bias for the condenser mic while
preset VR1 functions as gain control for
ELECTRONICS FOR YOU ❚  DECEMBER 2001
varying its gain. In order to increase the
audio power, the low-level audio output
from the preamplifier stage is coupled via
coupling capacitor C7 to the audio power
amplifier built around BEL1895 IC.
BEL1895 is a monolithic audio power
amplifier IC designed specifically for sen-
sitive AM radio applications that delivers
1 watt into 4 ohms at 6V power supply
voltage. It exhibits low distortion and
noise and operates over 3V-9V supply volt-
age, which makes it ideal for battery op-
eration. A turn-on pop reduction circuit
prevents thud when the power
supply is switched on.
Coupling capacitor C7 deter-
mines low-frequency response of
the amplifier. Capacitor C9 acts
as the ripple-rejection filter. Ca-
pacitor C13 couples the output
available at pin 1 to the loud-
speaker. R15-C13 combination
acts as the damping circuit for
output oscillations. Capacitor C12
provides the boot strapping func-
tion.
This circuit is suitable for low-
power HAM radio transmitters to
supply the necessary audio power
for modulation. With simple modi-
fications it can also be used in
intercom circuits.

SMOKE ALARM
PRADEEP G.
T
he smoke alarm circuit presented
here is based on the readily avail-
able photon-coupled interrupter
CIRCUIT IDEAS
SAN
I TH
EO
module and timer IC NE555. The photo
interrupter module is used as the smoke
detector, while timer 555 is wired in
astable configuration as an
AF oscillator for sounding
alarm via a loudspeaker.
In the absence of any
smoke, the gap of photo in-
terrupter module is clear
and the light from LED However, when smoke is present in
falls on the phototransistor the gap of the photo interrupter module,
through the slot. As a re- the light beam from LED to the
sult, the collector of phototransistor is obstructed. As a result,
phototransistor is pulled to- the phototransistor stops conducting and
wards ground. This causes pin 4 (reset) of IC 555 goes high to acti-
reset pin 4 of IC 555 to go vate the alarm.
low. Accordingly, the timer Note. The unit must be housed inside
is reset and hence the an enclosure with holes to allow entry of
alarm does not sound. smoke.
ELECTRONICS FOR YOU ❚  DECEMBER 2001
Construction

2001

TRANSISTOR CURVE TRACER
A. SARAVANAN
T
ransistor is the basic component
of all electronic equipment. A good
design of electronic circuitry re-
quires proper knowledge of the charac-
teristics and parameters of transistors.
Due to such factors as changes in doping
level of impurities and physical dimen-
sions, production imperfections, and en-
vironmental (ambient temperature, hu-
midity, etc) changes, no two transistors
can have the same characteristics.
Transistor is an active device and even
a very small change in its parameters
causes a large drift in its operation. This
affects the overall efficiency and the reli-
ability of an equipment. Hence for an ef-
ficient, reliable, and trouble-free design/
operation of the electronic equipment, the
designer must know the characteristics
and parameters of each transistor used
in the equipment.
The manufacturer provides
generalised family characteristics of tran-
sistors bearing specific part numbers.
These characteristics are drawn under
specific test conditions such as 25oC tem-
perature and 10mA collector current IC.
Fig. 1: Block diagram for tracing transistor output characteristics
Fig. 2: Block diagram for tracing transistor input characteristics
CONSTRUCTION
MAR
IL KU
SUN
But as the circuit designed may need to
be operated at different conditions (for ex-
ample, at an ambient temperature of 40oC
and collector current of 10 mA), the
manufacturer’s data is no longer adequate.
The manual procedure to draw the char-
acteristics of a transistor is tedious and
cumbersome. Further, using the manual
procedure, it is not feasible to draw the
dynamic characteristics of a transistor.
The transistor curve tracer circuit pre-
sented here enables one to draw the in-
put and output characteristics of npn tran-
sistors in common-emitter configuration
on a cathode ray oscilloscope (CRO). It
can be constructed and calibrated by the
designer himself. This circuit costs around
Rs 1500 and is designed to satisfy the
requirements of most circuit designers.
The circuit can be upgraded to draw
the characteristics of both npn and pnp
transistors, field effect transistors (FETs),
metal-oxide semiconductor field effect
transistors (MOSFETs), unijunction tran-
sistors (UJTs), silicon-controlled rectifiers
(SCRs), TRIACs, etc. In general, it can be
upgraded for any two- or three-terminal
ELECTRONICS FOR YOU ❚  DECEMBER 2001
analogue electronic device that has a
single control terminal unlike op-amps.
Block diagram
The transistor curve tracer is built around
the ramp generator and the current-to-
voltage converter. The ramp generator
produces a linear ramp that is applied to
the transistor under test either as the
collector-emitter voltage (VCE) or the base-
emitter voltage (VBE). The ramp is also
used to deflect the electron beam hori-
zontally (along x-axis) on the screen of
the CRO. Similarly, the current-to-volt-
age converter converts either the collec-
tor current (IC) or the base current (IB)
into a proportional voltage that is used to
deflect the electron beam vertically (along
y-axis) on the screen.
The signal conditioning and switch-
ing circuits, along with the ramp genera-
tor and current-to-voltage converter, make
a complete curve tracer for the input and
output characteristics of an npn transis-
tor.
Output characteristics (Fig. 1). The
ramp and clock generator generates a lin-
ear ramp and 1 kHz clock pulses. The
ramp is amplified by the ramp buffer am-
plifier to 0 to 5 volts. This amplified ramp
is applied to the collector of the transis-
tor under test as the collector-emitter volt-
age (VCE) through the current-to-voltage
converter.
The current-to-voltage converter gives
an output voltage proportional to collec-
tor current IC that is applied to the CRO
to deflect the beam in y-axis. The 0-5V
ramp output is applied to the CRO to de-
flect the beam in x-axis. Hence we can
trace the output characteristics of the
transistor with the collector-emitter volt-
age (VCE) on x-axis and IC on y-axis.
To trace the output characteristic
graph for various base current (IB) val-
ues, the generator’s clock output fed to
the counter is incremented for each clock
pulse. The count sequence is 000, 001,
010, 011, 100, 101, 110, and 111 (0 to 7
decimal). After 111, the counter resets au-
tomatically to 000 and the sequence re-
peats. The lower three bits of the counter
are applied to the base-current control cir-
cuit.
The base-current control circuit sets
IB in eight discrete 100µA steps, i.e. 0 µA,

Fig. 3: Circuit diagram of transistor curve tracer
100 µA, 200 µA, 300 µA, 400 µA, 500 µA,
600 µA, and 700 µA. Adjust the step width
(100 µA) using a potentiometer such that
the output characteristics of various npn
transistors with various current gains (α)
are traced/accommodated.
Input characteristics (Fig. 2). Here
again, the ramp and clock generator gen-
erates a linear ramp and 1kHz clock
pulses. The ramp is amplified by the ramp
buffer amplifier to 0-5V. This amplified
ramp is attenuated and amplified as re-
quired to get 0-1V ramp and applied to
the base of the transistor under test as
the base-emitter voltage (VBE) through the
current-to-voltage converter.
The current-to-voltage converter gives
an output voltage proportional to base cur-
rent IB that is applied to the CRO to de-
flect the beam in y-axis. The 0-1V ramp
output is applied to the CRO to deflect
the beam in x-axis. Hence we can trace
the input characteristics of the transistor
with VBE on x-axis and IB on y-axis.
To trace the input characteristics
graph for various VCE values, the clock
output of the generator is fed to the
counter and switching circuit. The counter
CONSTRUCTION
counts the number of pulses in the bi-
nary form. Q0 output of the counter is
used as the collector-emitter voltage con-
trol that toggles VCE with 0 volt and 10
volts for every clock pulse. Thus we can
trace the input characteristics for VCE = 0
volt and VCE = 10 volts.
The circuit
The transistor curve tracer circuit (Fig.
3) comprises power supply, ramp and clock
generator, ramp buffer and offset null,
current-to-voltage converter, counter, base
current control, and switching sections.
1. The power supply section. The
circuit operates on ±12V regulated power
supply. The input AC mains supply is
stepped down by transformer X1 to de-
liver a secondary supply of 15-0-15V AC
at 1 ampere. The output of the trans-
former is rectified by a bridge rectifier.
The 1000µF, 35V capacitors act as filters
to eliminate ripples and provide unregu-
lated DC output voltage.
The unregulated dual DC voltage is
converted by three-terminal ICs AN7812
and AN7912 into ±12V regulated power
ELECTRONICS FOR YOU ❚  DECEMBER 2001
supply. (Note. Connect 0.1µF decoupling
capacitors between the supply terminals
and ground of every IC in order to sup-
press unwanted noise signals in the sup-
ply voltage.)
2. The ramp and clock generator
section. The ramp and clock generator
uses a constant current source (LM334)
and a capacitor, in conjunction with timer
NE555 (IC3) wired as an astable
multivibrator, to generate a linear ramp.
The control terminal of timer 555 (pin 5)
is held at a reference voltage of 5 volts by
a zener diode so that the upper threshold
(VUTP) is at 5 volts and the lower thresh-
old (VLTP) at 2.5 volts.
The output current from IC LM334
can be controlled with the help of poten-
tiometer VR1. This current charges the
capacitor linearly in the form of a linear
ramp. As soon as the voltage across the
capacitor exceeds the upper threshold volt-
age (VUTP), the output of timer 555 changes
its state and goes low. This activates the
discharge terminal (pin 7) of timer 555
and hence the capacitor quickly discharges
through the timer.
As the voltage across the capacitor
 CONSTRUCTION

Fig. 4: Actual-size, single-side PCB layout for transistor curver tracer

Fig. 5: Component layout for the PCB

ELECTRONICS FOR YOU ❚  DECEMBER 2001


Fig. 6: Waveforms at various points in the circuit
drops below the lower threshold voltage
(VLTP), the output of timer 555 changes
its state and goes high to disable the dis-
charge terminal and further discharging
of capacitor stops. Once again the capaci-
tor gets charged linearly through the con-
stant current source and the sequence re-
peats. Thus the potential across the ca-
pacitor is a positive linear ramp between
2.5 volts and 5 volts. The ramp frequency
can be controlled by varying the charging
current using potentiometer VR1. (EFY
CONSTRUCTION
Lab note. During lab testing, we used
AD590 temperature transducer in place
of LM334H as the constant current source,
and the method of using the same is
shown in Fig. 3 within dotted lines.)
3. The ramp buffer and offset null
section. Since the output impedance of
the ramp source is very high, we cannot
load it. Also, a DC offset voltage equal to
the lower threshold voltage (VLPT = 2.5V)
is present in the ramp output. In order to
nullify the offset voltage of the ramp and
ELECTRONICS FOR YOU ❚  DECEMBER 2001
to source the current from the ramp, use
a buffer amplifier. An op-amp in non-in-
verting amplifier configuration is used to
achieve this function.
As the input impedance of the non-
inverting amplifier is very high, it will
not load the ramp source. Also, it is pos-
sible to nullify the DC offset voltage
present in the ramp output with the help
of ramp offset adjustment preset VR2.
By adjusting feedback preset VR3, the
output of ramp buffer can be set to de-
liver a linear 0-5V ramp. This output is
used as VCE for the transistor under test
to source the collector current (IC).
To draw the input characteristics of
the transistor, the base-emitter voltage
(VBE) should be varied linearly. For this
we require a linear 0-1V ramp with suffi-
cient current sourcing capability. In or-
der to achieve this, a ramp attenuator
(voltage divider) and an amplifier are
used.
The 0-5V ramp output of ramp buffer
is attenuated by the potential divider net-
work (comprising resistors R4 and R5) fol-
lowed by an op-amp (IC5) connected in
non-inverting configuration. The gain of
the op-amp can be adjusted using preset
VR5 connected in the feedback path.
In order to nullify the offset voltage
of the op-amp, balancing preset VR4 is
connected between the offset null termi-
nals of the op-amp. The output of the op-
amp is 0-1V linear ramp, which is used
as the base-emitter voltage (VBE) for sourc-
ing the base current (IB) of the transistor
under test.
4. The current-to-voltage converter
section. The spot on the CRO screen is
deflected in proportion to the potential
applied to its input. Hence in order to
deflect the beam along y-axis, which is
the current axis (collector current IC in
the transistor output characteristics and
base current IB in the transistor input
characteristics), the current component is
to be converted into a proportional volt-
age.
The current to be measured is passed
through series resistor R7 of 10-ohm, ±1%
MFR (metal film resistor). Potential drop
Vout across the resistor, according to the
Ohm’s law, is proportional to current I
through it and is given by the following
relationship:
V = IR
where Vout = 10xI
Hence, there is a potential drop of 10
mV per mA of the current through the

Fig. 7: Actual output curves on CRO (shown
without retrace)
Fig. 8: Actual input curves on CRO (shown
without retrace)
circuit. We cannot apply this small float-
ing potential directly to the CRO for a
significant deflection. Therefore we use a
differential amplifier to have an output
voltage with respect to the ground that is
proportional to the current though the cir-
cuit. The differential amplifier has a gain
of 100 that can be fine-tuned with the
help of gain adjust preset VR7 in the feed-
back path.
The current-to-voltage converter con-
verts the current of 1 mA into a poten-
tial difference of 1 volt that can be ap-
plied to the CRO to deflect the beam in
vertical axis. In order to nullify the off-
set voltage of the op-amp, connect a bal-
ancing preset to the offset null terminals
of the op-amp.
5. The counter section. The base cur-
rent (IB) is to be changed in discrete steps
for every ramp to enable the transistor’s
output characteristics for various IB val-
ues simultaneously on the CRO screen.
In the counter circuit, the output of
timer 555 (IC3) from pin 3 is a square
wave that intimates the end of ramp. This
output is used as clock pulse for the
counter wired around CMOS binary/de-
cade, up/down IC MC14029B or CD4029B
(IC7).
IC7 is wired as a 3-bit binary up-
counter so that the output of the counter
(Q2, Q1, and Q0) is incremented by bi-
CONSTRUCTION
nary 1 for every clock pulse. The count
sequence is 000, 010, 011, 100, 101, 110,
and 111, i.e. 0 through 7 decimal. After
111, the counter is automatically reset to
000, and once again the count sequence
repeats. Hence we get eight discrete logic
levels, and accordingly we can set the base
current (IB) using a base current control
circuit.
Similarly, to draw the input charac-
teristics of the transistor under test for
various collector-emitter voltage (VCE) val-
ues, the collector-emitter voltage (VCE) is
to be changed for each ramp. The least
significant bit (Q0) of the counter is used
to toggle the collector-emitter voltage (VCE)
from 0 volt to 10 volts. Thus we can view
the input characteristics of the transistor
for VCE= 0 volt to VCE= 10 volts simulta-
neously on the screen of the CRO.
6. The base current control section.
This section receives the input from the
counter circuit and varies the base cur-
rent (IB) of the transistor. The output of
counter IC7 in series with a high-value
resistor acts as the constant current
source. The high-level outputs of the
counter are fairly constant at 10 volts.
When we connect a resistor of 100
kilo-ohms in series with Q0 output of the
counter, it supplies a constant current of
100 µA during its logic 1 state. Similarly,
when we connect a resistor of 50 kilo-
ohms (two 100 kilo-ohm resistors in par-
allel) in series with Q1 output of the
counter, it supplies a constant current of
200 µA during its logic 1 state. Using 25-
kilo-ohm resistor in series with Q2 out-
put we can get a constant current source
of 400 µA.
When more than one current source
are connected in parallel, the result is
similar to having a current source equal
to the sum of individual source currents.
If we use the base current (IB) setting
as it is for a transistor with large current
amplification factor (α), its collector cur-
rent (IC) gets saturated for much smaller
values of IB and only two or three traces
appear on the screen of the CRO. To get
the maximum number of traces, reduce
the base current by increasing the series
resistor values through IB SET potenti-
ometer VR8. With the help of VR8, we
can adjust the base current in incremen-
tal steps from 10 µA to 100 µA.
(Note. Connect two 100-kilo-ohm re-
sistors in parallel to get 50-kilo-ohm re-
sistor. Similarly, connect four 100-kilo-
ohm resistors in parallel to have 25-kilo-
ELECTRONICS FOR YOU ❚  DECEMBER 2001
ohm resistor. This method has been shown
in Fig 3.)
7. The switching section. Certain
circuits are common in tracing both the
output characteristics and input charac-
teristics. The ramp and clock generator,
ramp buffer and amplifier, and counter
circuits are retained at their places for
both output and input characteristics. But
to trace the output characteristics the cur-
rent-to-voltage converter is to be con-
nected in the collector of the transistor
under test and to trace the input charac-
teristics it is to the connected in the base
of the transistor (refer Figs 1 and 2 for
output and input characteristics, respec-
tively).
To have minimum complexity, the col-
lector and the base circuits of the transis-
tor are switched suitably using a
changeover switch on the front panel. The
switching details are obvious from the cir-
cuit diagram in Fig. 3.
Construction
Wire the circuit on a 2.5mm, IC-type gen-
eral-purpose printed circuit board (PCB)
as shown in Fig. 3. The use of glass-ep-
oxy PCB is recommended. An actual-size,
single-side PCB for the circuit is shown
in Fig. 4, with its component layout shown
in Fig. 5.
Carefully solder all the components
and use sockets for ICs. All range resis-
tors used should be stable, close-tolerance
type (preferably MFRs). Preferably use
linear-type IB SET potentiometer and
mount it on the front panel of the instru-
ment. Enclose the circuit board, power
transformer, and other circuit components
in a metal box having approximate di-
mensions of 22x17x7.5 cm. Extend input
and output leads to the corresponding
points in the circuit. Terminate the out-
puts for connection to the CRO in BNC(F)
connectors.
Calibration
After construction, check the circuit thor-
oughly for short circuits, breaks, and open
circuits on the PCB. After switching on
the instrument, let it warm up for a few
minutes before commencing with the cali-
bration. Calibration procedure of the cir-
cuit is as follows:
1. Check and ensure ±12V regulated
voltage with respect to ground.
2. Connect a CRO to shorted pins 2
 CONSTRUCTION

and 6 of timer 555 (ramp output). A lin- screen of the CRO, nullify DC offset volt- tom of the screen ((0,0) position in the
ear ramp with positive slope is observed age using preset VR6 and adjust the am- graph).
on the screen of the CRO. By adjusting plitude of the observed ramp waveform 10. Set the inputs for DC coupling to
frequency control potentiometer VR1, set to 0-5 volts with the help of preset VR7. the CRO.
the frequency of the ramp at 1 kHz (refer Calibrate the current-to-voltage converter 11. Connect the transistor whose char-
waveform 1 in Fig. 6). to convert 1 mA of current into 1 volt acteristics are to be traced to the transis-
3. Connect the CRO to the output of (refer waveform 4 in Fig. 6). Then check tor curve tracer, ensuring correct pin con-
ramp buffer. Adjust preset VR2 to nullify the clock output by connecting the CRO figuration.
the DC offset voltage in the output of to pin 3 of timer 555 (refer waveform 5 in 12. Set the selector switch for input/
ramp buffer. Adjust preset VR3 to set the Fig. 6). output characteristics to the output char-
amplitude of ramp output to 0 to 5 volts 6. Verify the outputs of the counter acteristics position.
(refer waveform 2 in Fig. 6). by using a dual-trace oscilloscope. Con- 13. Release the CRO inputs from
4. Connect CRO at the output of ramp nect one input channel of the CRO with ground and switch them over to connect
attenuator and amplifier. Adjust preset clock pulses at pin 3 of IC3 and the out- inputs.
VR4 to nullify the DC offset voltage in puts at pins 6, 11, and 14 of counter IC7 14. Now view the output characteris-
the output of ramp buffer. Adjust preset to the other input of the CRO sequen- tics of the transistor. Fine-tune the IB set
VR5 to set the amplitude of ramp output tially (refer waveforms 5, 6, 7, and 8 in potentiometer to get eight traces on the
to 0 to 1 volt (refer waveform 3 in Fig. 6). Fig. 6). screen of the CRO.
5. Calibrate the current-to-voltage con- 7. Short-circuit the base-emitter ter- 15. To trace input characteristics of
verter by connecting a 1-kilo-ohm. 1% minals of the transistor under test. Se- the transistor, change the input/output
metal film resistor between the collector lect input/output characteristics switch S2 characteristics selector switch to the in-
and emitter terminals of the transistor to output characteristics position and con- put characteristics position.
under test. Connect the output of the cur- nect the CRO to the output of the cur- 16. Set the volts/div control of x-axis
rent-to-voltage converter to a CRO. By rent-to-voltage converter. By adjusting IB to 0.1 volt/div and observe the input char-
observing the ramp waveform on the SET potentiometer VR8 on the front panel acteristics likewise.
of the instrument, check proper opera- Figs 7 and 8 show a typical transistor’s
PARTS LIST tion of the base-current section by observ- output and input characteristics, respec-
Semiconductors: ing stair-case ramp of varying amplitude tively, on the CRO screen (without re-
IC1 - 7812, +12V regulator on the screen of the CRO (refer wave- trace).
IC2 - 7912, – 12V regulator
form 9 in Fig. 6).
IC3 - NE555 timer
IC4, IC6 - µA741 op-amp (IC OP-07
op-amps can be used in
Conclusion
place of µA741 with Operation To draw the characteristics of pnp tran-
advantage) After calibration, the instrument is ready sistors, insert an inverter circuit in the
IC7 - MC14029B/CD4039 binary/
decade up-/down-counter for use to trace the input and output char- ramp path of collector-emitter voltage VCE
IC8 - LM334H/AD590 tempera- acteristics of npn transistors. Follow the and base-emitter voltage VBE, and invert
ture sensor operating procedure given below every the output of the current-to-voltage con-
ZD1 - 1N4007 rectifier diode time to get correct traces of input and verter.
Resistors (all ¼-watt, ±1% MFR, unless stated output characteristics of the transistor: By using a potential divider and
otherwise): 1. Connect the x-axis and y-axis BNC buffer amplifier circuit in place of the
R1, R5, R6,
pins of the transistor curve tracer to the base-current control circuit you can draw
R8, R9 - 1-kilo-ohm
R2, R4 - 22-kilo-ohm corresponding inputs of the CRO. the characteristics of FETs and
R7 - 10-ohm 2. Plug in the AC cord of both the MOSFETs.
R3, R10, R11 CRO and the transistor curve tracer and To trace the forward characteristics
(A,B), R12(A-D) - 100-kilo-ohm switch them on. of diodes, connect the anode of the diode
VR1 - 1-kilo-ohm potmeter
VR2 - 2.2-kilo-ohm preset 3. Set the CRO inputs to ground. to the base terminal and the cathode to
VR3, VR4, 4. Allow warm-up time of at least 10 the emitter terminal. Set the transistor
VR5, VR6 - 10-kilo-ohm preset minutes for the circuit components to get curve tracer to draw input characteris-
VR7 - 150-kilo-ohm stabilised. tics, and the CRO screen displays the
VR8 - 1-mega-ohm potmeter
5. Set the CRO for X-Y mode of op- forward characteristics of the diode.
Capacitors: eration. Similarly, with simple add-on circuits
C1-C4, C9 - 0.1µF ceramic disk 6. Adjust intensity and focus controls to the motherboard, you can draw the
C5, C6 - 1000µF, 35V electrolytic
C7, C8 - 100µF, 25V electrolytic to get a sharp spot on the screen of the characteristics of UJTs, SCRs, TRIACs,
C10 - 0.01µF ceramic disk CRO. etc.
Miscellaneous: 7. Set the volts/div control of x-axis to Thin and faint retrace lines visible
X1 - 230V AC primary to 0.5 volt/div. along with the characteristic traces can
15V-0-15V AC, 500mA 8. Set the volts/div scale of y-axis to 2 be removed by connecting a retrace blank-
secondary transformer volts/div. ing circuit to the Z-mod input of the CRO.
S1 - On/off switch
S2 - DPDT switch
9. Adjust the position controls of the Almost all CROs exceeding 30MHz band-
CRO to position the spot on the left bot- width have the Z-mod input facility. ❏

ELECTRONICS FOR YOU ❚  DECEMBER 2001


TRIPPING SEQUENCE
RECORDER-CUM-INDICATOR
R.G. THIAGRAJ KUMAR AND S. RAMASWAMY
I
n applications like power stations and
continuous process control plants, a
protection system is used to trip
faulty systems to prevent damages and
ensure the overall safety of the personnel
and machinery. But this often results in
multiple or cascade tripping of a number
of subunits.
Looking at all the tripped units doesn’t
reveal the cause of failure. It is therefore
very important to determine the sequence
of events that have occurred in order to
exactly trace out the cause of failure and
revive the system with minimal loss of
time.
The circuit presented here stores the
tripping sequence in a system with up to
eight units/blocks. It uses an auxiliary re-
lay contact point in each unit that closes
whenever tripping of the corresponding
unit occurs. Such contact points can be
identified easily, especially in systems us-
ing programmable logic controllers (PLCs).
This circuit records tripping of up to
eight units and displays the order in
which they tripped. A clock circuit, how-
ever fast, cannot be employed in this cir-
cuit because the clock period itself will be
a limiting factor for sensing the incidence
of fault. Besides, it may also mask a num-
ber of events that might have occurred
during the period when the clock was low.
Hence the events themselves are used as
clock signals in this circuit.
Fig. 1 shows the block diagram of the
tripping sequence recorder-cum-indicator.
Fig. 1: Block diagram of tripping sequence recorder-cum-indicator
CONSTRUCTION
MAR
IL KU
SUN
The inputs derived from auxiliary relay
contacts (N/O) of subunits or push-to-on
switches are latched by RS flip-flops when
the corresponding subunits trip, causing
the following four actions:
1. The latch outputs are ORed to acti-
vate audio alarm.
2. The latch outputs are differentiated
individually and then ORed to provide
clock pulses to the counter to increment
the output of the counter that is initially
preset at 1 (decimal).
3. Each individual latch output acti-
vates the associated latch/decoder/driver
and 7-segment display set to display the
number held at the output of the counter,
which, in fact, indicates the total number
of trips that have taken place since the
last presetting.
4. LEDs associated with each of the
latch, decoder, and driver sets remain lit
to indicate the readiness of the sets to
receive the tripping input. LEDs associ-
ated with the tripped unit go off.
The circuit
IC1 and IC2 (CD4043) Quad NOR RS flip-
flops in Fig. 2 are used to capture and
store the information pertaining to the
tripping of individual units. Reset pins of
all the eight flip-flops and sub-parallel en-
able (PE) pin 1 of BCD up-/down-counter
CD4510 (IC3) are returned to ground via
10-kilo-ohm resistor R22, while set pins
of all RS flip-flops are returned to ground
ELECTRONICS FOR YOU ❚  DECEMBER 2001
via individual 10-kilo-ohm resistors R14
through R21.
Initially, all the eight Q outputs of
IC1 and IC2 are at logic 0. The auxiliary
relay contacts of the subunits, which are
depicted here by push-to-on switches S1
through S8, connect the set terminal of
the corresponding stage of RS flip-flop to
+12V whenever tripping of a specific sub-
unit occurs. This makes the output of the
associated flip-flop go high. Thus when-
ever a sequence of tripping of subunits
occurs, the corresponding outputs (1Q to
8Q) go high in the order of the tripping of
the associated subunits.
All the eight Q outputs are connected
to the corresponding latch-enable inputs
of BCD latch-cum-decoder-driver ICs
(CD4511). These Q outputs are also ORed
using diodes D1 through D8 to activate
an audible alarm and also routed to a set
of differentiator networks (comprising ca-
pacitors C1 through C8 and resistors R2
through R9).
A differentiator provides a sharp pulse
corresponding to the tripping of a sub-
unit. All such differentiated pulses are
ORed via diodes D9 through D16 and
coupled to the counter stage formed by
IC3 (CD4510, a synchronous up-/down-
counter with preset) after amplification
and pulse shaping by transistor amplifier
stages built around transistors T2 and T3.
These pulses serve as clock to count the
number of trippings that occurred after a
reset.
PARTS LIST
Semiconductors:
IC1, IC2 - CD4043 quad NOR RS latch
IC3 - CD4510 BCD up-/down-
counter
IC4-IC11 - CD4511 BCD-to-7-segment
latch/decoder/driver
T1-T11 - BC547 npn transistor
T12-T19 - BC557 pnp transistor
D1-D16 - 1N4007 rectifier diode
DIS1-DIS8 - LT543 common-cathode
7-segment display
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1-R11,
R13-R38 - 10-kilo-ohm
R12, R39-R46 - 1-kilo-ohm
R47-R102 - 470-ohm
Capacitors:
C1-C8 - 0.01µF ceramic disk
Miscellaneous:
S1-S8 - Push-to-on switch or relay
contacts (N/O)
S9 - Push-to-on switch
PZ1 - Piezobuzzer
- 12V, 500mA power supply
 CONSTRUCTION

Fig. 2: Schematic diagram of tripping sequence recorder-cum-indicator

Operation
Let us assume that three units,
say, E, H, and A (fifth, eighth,
and first), tripped in that order
following a fault.
When the system is reset (be-
fore any tripping), the outputs of
all RS flip-flops (1Q through 8Q)
are low. This LE* active-low
makes latches IC4 through IC11
transparent and as the counter
is preset to 1 (since P1 input is
high while P2, P3, and P4 are
low) with the help of switch S9,
all the latches hold that ‘1’ and
their decoded ‘b’ and ‘c’ segment
outputs go high.
However, the common-cath-
ode drive is absent in all the 7-
segment displays because driver
transistors T4 through T11 are Fig. 3: Actual-size, single-side PCB of the main control portion of tripping sequence controller-cum-
cut off due to the low outputs of indicator circuit

ELECTRONICS FOR YOU ❚  DECEMBER 2001


Fig. 4: Component layout for Fig. 3
Fig. 5: Actual-size, single-side PCB for
latch decoder/driver and display circuit of
one subunit
all RS flip-flops and hence the displays
are blank. At the same time, the low out-
puts of all RS flip-flops (1Q through 8Q)
forward bias pnp transistors T12 through
T19 associated with LED1 through LED8
of each of the displays. As a result, all
these LEDs glow, indicating no tripping.
Now when unit E trips, output 5Q of
RS flip-flop IC2 goes high to provide the
base drive to common-cathode drive tran-
sistor T8. This, in turn, activates DIS5
(fifth from left in Fig. 2) to display ‘1’,
CONSTRUCTION
Fig. 6: Component layout for Fig. 5
indicating that unit E tripped first. The
corresponding LED5 goes off as transis-
tor T16 is cut off. Also, latch IC8 is dis-
abled due to logic 1 on its pin 5 and there-
fore it does not respond to further changes
in its BCD data input. Simultaneously,
the buzzer goes on to sound an audible
alarm, indicating the emergency situation
at the plant.
The differentiator formed by C5 and
R6 responds to the low-to-high transition
of 5Q and generates a short pulse. This
pulse passes through diode D13 and tran-
ELECTRONICS FOR YOU ❚  DECEMBER 2001
sistors T2 and T3 and reaches
clock pin of counter IC3. The
counter counts up and its output
becomes 0010 (decimal 2).
As mentioned earlier, all the
display units other than E have
the drive signal on segments a,
b, g, e, and c now but are off
because of the missing common-
cathode drive. When the next
subunit H trips, output 8Q expe-
riences a low-to-high transition
and the corresponding display
(DIS8) shows digit ‘2’. The above
sequence of operation holds true
for any further subunit tripping—
with the displayed digit
incrementing by one for each se-
quential tripping.
In the prototype, LEDs D17
through D24 were fixed below the
corresponding 7-segment displays
pertaining to subunits A through H to
provide a visual indication that these units
are ready to respond to a tripping.
The circuit works satisfactorily with
twisted-pair wires of length up to 5 metres.
In electrically noisy environments, the
length of the cable has to be reduced or a
shielded twisted-pair cable can be used.
An actual-size, single-side PCB lay-
out for the main control portion of the
tripping sequence recorder-cum-indicator
circuit is shown in Fig. 3 and its compo-
nent layout in Fig. 4. The PCB layout for
the indicator set comprising IC4, DIS1,
transistors T4 and T12, LED1, etc is
shown in Fig. 5 and its component layout
in Fig. 6. The indicator set of Fig. 5 can
be connected to the main PCB of Fig. 3
using Bergstrip type SIP (single-inline-
pin) connectors as per requirements.
This tripping sequence recorder-cum-
indicator circuit can also be used in quiz
games to decide the order in which the
teams responded to a common question.
For this, provide push-to-on switches on
the tables of individual teams and a mas-
ter reset to the quiz master. Modify the
alarm circuit suitably with a retriggerable
monostable stage so that the audible
alarm stops after a short interval. ❏
The End