[CprE 381] Computer Organization and Assembly-

Level Programming, Fall 2018

Project B - Report
Name(s) _Ben Gonner and Nathan Nordling___________________

Section/Lab Time ___D_____

Refer to the highlighted language in the Project B instruction for the context of the following questions.

a. [Part 1] Explain the conflict and how it relates to assumption that we will be making for forwarding and
hazard detection (Hint: It has to do with the fact that we assume an instruction in the ID stage will get
the data being written by the WB stage).
The Writeback stage outputs our data on the rising edge and there are no logic gates between the dmem
and the register file. Our register file, therefore needs to read on the falling edge to avoid timing errors.
This also allows us to write to the register file on the falling edge, then write the same data immediately
on the next rising edge, reducing the turn over time of the reg file from a whole cycle to a half cycle.

Give an example sequence of instructions that the processor we are designing will not be able to properly
handle without additional logic or another change.

LW $t0, 0($t3)
Addi $t1, $t0, 6

b. [Part. 4] Provide a description of a few test cases (at least one test case for each of the six instructions)
and clear screenshots depicting your functioning test cases.
 ADD

1|Page
2|Page
 ADDI

3|Page
4|Page
 LW

5|Page
6|Page
7|Page
 SW

8|Page
 BEQ

 J

9|Page
c. [Part 5] Implement ID stage branch resolution and provide a legible simulation-screenshot of a taken-
branch instruction correctly executing.

d. [Part 6a] Implement a forwarding unit (using VHDL) to support the following data dependent cases.
Give simulation screenshots of correct forwarding for each case, make sure to provide an explanation of
the instructions you ran to show the below hazards:
i) ALU producer to ALU consumer at distance 1 (e.g. ADD $1, $2, $3; ADD $4, $1, $2)

At first, all the register selects have their own value. Then, the IdEx_rs_sel changes to match the
ExMem_rd_sel, and the rs_data_sel changes to 1, signaling that we should forward from the ExMem register
into the Alu. Then, IdEx_rt_sel changes to match ExMem_rd_sel, and the rt_data_sel changes to 1.

ii) ALU producer to ALU consumer at distance 2 (e.g. ADD $1, $2, $3; <INST>; ADD $4, $1, $2)

First, all the register selects have their own value. Then, the IdEx_rs_sel changes to match the
MemWB_rd_sel, and the rs_data_select changes to 2, signaling that we should forward from the MemWB
register into the Alu. Then, IdEx_rt_sel changes to match the MemWB_rd_sel, and the rt_data_select changes
to 2.

iii) Load producer to ALU consumer distance 2 (e.g. LW $1, 0($10); <INST>; ADD $5, $1, $r2)

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 Our Forwarding unit doesn’t distinguish between a load producer to alu consumer and an alu producer
to alu consumer at distance two, so the test is exactly the same.

iv) ALU producer to BEQ consumer at distance 2 (e.g. ADD $1, $2, $3; <INST>; BEQ $1, $2, label)

First, all the register selects have their own values. Then, IfId_rs_sel changes so that it matches
ExMem_rd_sel, and the branch_rs_data_select sets to 1. Then, the IfId_rt_sel changes so that it matches the
ExMem_rd_sel, and the branch_rt_data_select sets to 1.

e. [Part 6b] Implement a hazard detection unit (using VHDL) to support the following data dependent cases.
Give simulation screenshots of correct forwarding for the cases described in the lab manual, provide an
explanation.

Jump instruction flush:

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When the instruction entering the ID stage changes to a jump instruction, the If/Id Flush turns to one.

Branch on Equal flush:

When the Instruction entering ID changes, nothing happens, but when the branch taken flag changes to
one while the instruction is branch, the If/Id flush sets to one.

Load-Add stall:

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When the instruction entering EX changes to load word, nothing happens. But, when If/ID_rs_sel
changes to match ID/EX_rd_sel and the reg_write_enable sets to 1, the PC stall signal, If/ID stall signal,
and the Id/Ex flush signal all set to one.

ADD-BEQ stall:

When the instruction entering ID changes to branch, nothing happens, but when the ID_rs_sel is changed
to match the EX_rd_sel and the reg_write_enable sets to 1, the PC stall, IF/ID stall, and Id/Ex flush
signals all set to one. Then, we show that the signals set for both rs and rt.

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f. [Part 6c] Connect your forwarding and hazard detection units to your pipelined processor and provide a
simulation screenshot showing that your pipeline correctly executes the given test program.

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Extra Credit (5 points) (This is not required):
 Explain the potential impact that the falling edge trigger register fill has on the critical path for the
processor we are designing (2.5 points).

Changing the register file to a falling edge component increases the length of the critical path by a half
of a clock cycle. This is because it takes an extra half cycle to complete the register write for the
WriteBack stage.

 Implement a fix (in VHDL) to the issue we have caused that will allow the register file to continue
to write on the rising edge. Draw (or screenshot) the change that you have made and explain how
it solves the potential issue.

The solution is to set the register file to write data in on the falling edge, but to read out data on the rising
edge.

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