2014 Fourth International Conference on Advanced Computing & Communication Technologies
4-2 Compressor Design with New XOR-XNOR Module
Sanjeev Kumar
Department of Electronics and Communication
Engineering, Guru Jambheshwar University of
Science and Technology, Hissar (Haryana)
sanjeev.kumar191@gmail.com
Abstract—In this paper, a low-power high speed 4-2
compressor circuit is proposed for fast digital arithmetic
integrated circuits. The 4-2 compressor has been widely
employed for multiplier realizations. Based on a new exclusive
OR (XOR) and exclusive NOR (XNOR) module, a 4-2
compressor circuit has been designed. Proposed circuit shows
power consumption variation in the range of 718.72 pW to
3357.40 pW. Maximum output delay of the circuit presents
variation in the range of 43.83 ps to 27.74 ps. Further, power-
delay product (PDP) of circuit is varying from 315.01×10-22(J)
to 931.34×10-22(J) with change in supply voltage from 1.8V to
3.3V. Power consumption, delay and PDP of proposed 4-2
compressor circuit have been compared with earlier reported
circuits and proposed circuit is proven to have the minimum
power consumption and the lowest delay. Simulations have
been performed by using SPICE based on TSMC 0.18m
CMOS technology.
Keywords- 4-2 compressor, CMOS, full adder, power delay
product (PDP).
I. INTRODUCTION
Multipliers are one of the most significant blocks in
computer arithmetic and are generally used in different
digital signal processors. There is growing demands for high
speed multipliers in different applications of computing
systems, such as computer graphics, scientific calculation,
image processing and so on. Speed of multiplier determines
how fast the processors will run and designers are now more
focused on high speed with low power consumption. The
multiplier architecture consists of a partial product
generation stage, partial product reduction stage and the final
addition stage. The partial product reduction stage is
responsible for a significant portion of the total
multiplication delay, power and area. Therefore in order to
accumulate partial products, compressors usually implement
this stage because they contribute to the reduction of the
partial products and also contribute to reduce the critical path
which is important to maintain the circuit’s performance [1].
This is accomplished by the use of 3-2, 4-2, 5-2 compressor
structures. A 3-2 compressor circuit is also known as full
adder cell [2]. As these compressors are used repeatedly in
larger systems, so improved design will contribute a lot
towards overall system performance. The internal structure
of compressors are basically composed of XOR-XNOR
gates and multiplexers. The XOR-XNOR circuits are also
building blocks in various circuits like arithmetic circuits,
978-1-4799-4910-6/14 $31.00 © 2014 IEEE
DOI 10.1109/ACCT.2014.36
Manoj Kumar
University School of Information and Communication
Technology. Guru Gobind Singh Indraprastha
University, New Delhi
manojtaleja@yahoo.com
multipliers, compressors, parity checkers, etc. Optimizied
design of these XOR-XNOR gates can improve the
performance of multiplier circuit [3]-[7]. In present work, a
new XOR-XNOR module has been proposed and 4-2
compressor has been implemented using this module. Use
proposed circuit in partial product accumulation reduces
transistor count as well as power consumption. This paper is
organised as follows: In section II building blocks of
compressor circuit are described and a new XOR-XNOR
circuit has been proposed. In section III a 4-2 compressor
has been designed with new XOR-XNOR module. Sections
IV discuss the results. Finally section V concludes the work.
II. COMPRESSOR CIRCUIT BUILDING BLOCKS
There are different architectures and designs of 4-2
compressor circuits reported in literature. These are mainly
composed of two types of circuits: XOR-XNOR circuits and
multiplexers (MUX). Complementary CMOS uses the dual
networks to implement a given function. One part consists
of complementary pull-up PMOS network while other part
consists of pull-down NMOS networks. This technique
requires more numbers of transistors and large layout area.
Static CMOS XOR and XNOR [3] gate is shown in figure
1(a). Another implementation of XOR-XNOR circuit with
12 transistors is shown in figure 1(b) [4]. Further in figure
1(c) two pull-up PMOS-transistors and two pull-down
NMOS–transistors are added to restore full swing operation.
The circuit performs successfully at low supply voltages but
this comes at the expense of increased area and number of
transistors. Another disadvantage of the circuit is that each
of the inputs drives four gates instead of two gates doubling
the input load. This will cause slow response when this
circuit is cascaded [5].
(a)
106
 (b)
(c)
Fig.1: Different implementation of XOR-XNOR
Multiplexer module produces an output that accurate
reflects state of one of the number of data inputs, based on
value of one or more control inputs. Two data inputs
multiplexer is named as 2-1 multiplexer. The carry
generator module in compressor produces the signals
generated by multiplexer. Figure 2(a) shows the multiplexer
implemented in standard CMOS logic style. Figure 2(b) by
adding an output buffer improves the driving capability but
consumes more power. Multiplexer in figure 2(c) is also
widely used in low power full adder cells. When buffers are
not used at the output, this design of the multiplexer is faster
than the CMOS design. This design consumes lesser power
than the CMOS design [7].
(a)
107
(b)
(c)
Fig.2: Different implementation of multiplexer
Proposed design of XOR-XNOR circuit using eight
transistors has been shown in figure 3(a). This circuit
provides good driving capability as it uses static CMOS
inverter and can operate at low supply voltages. In this
circuit when X1=X2=0 output is low because P1, P2 and N3
transistors are on and logic 0 is passed to output. With input
combination of X1=0 and X2=1 circuit show high output as
transistor P1, N2 and N3 transistors are on while transistors
P2, P3 and N1 are off and high logic is passed to output
node. In another case when X1=1 and X2=0, transistor P2,
P3 and N1 are on and high logic is passed to output node. In
last case when X1=X2=1, output node show low logic as
transistor P3, N1 and N2 are on, so proposed circuit works
as XOR gate. XNOR operation has been obtained with
addition of inverter. Figure 3(b) shows the input and output
waveforms for XOR-XNOR circuit.
(a)
 (b)

Fig.3: (a) Design of proposed XOR-XNOR (b) Input and

output waveform for XOR-XNOR
III. DESIGN OF 4-2 COMPRESSOR
A compressor is a device which is mostly used in
multipliers to reduce the operands while adding terms of
partial products. A typical M-N compressor takes M equally
weighted input bits and produces N-bit binary number. The
simplest and the most widely used compressor is the 3-2
compressor which is also known as a full adder [8]. It has
three inputs to be summed up and provides two outputs.
Similarly, a 4-2 compressor can also be built from two
cascaded 3-2 compressor circuits. The conventional
implementation of a 4-2 compressor is composed of two
serially connected full adders, as shown in figure 4 [9]-[11].
Different structures of 4-2 compressors are reported in
literature and these are governing by the basic equation as
follows:
X1 + X2 + X3 + X4 + Cin = Sum + 2·(Carry + Cout)
 X1 X2 X3 X4
Fig. 4: (a) Block diagram (b) Full adder representation (c)
Logic decomposition of 4-2 compressor
The 4-2 compressor has five inputs and three outputs, where
the four inputs X1, X2, X3, X4 and the output Sum have the
same weight. On the other hand, the outputs Carry and Cout
have one bit order higher, thus presents a higher
compression ratio and a more regular interconnection
arrangement. One vital point to be emphasized in this
compressor is the independence of the input carry Cin in the
output carry Cout [12]-[14]. The 4-2 compressor optimized
at gate level with XOR-XNOR modules and carry
generators by 2:1 multiplexers (MUX) reduces the critical
path delay as shown in figure 4(c) [15]. The multiplexer
block at the SUM output takes the select bit prior to the
inputs obtain and thus the transistors are already switched
by the time they come. This minimizes the delay to a
(1) significant level. The complete circuit diagram of proposed
4-2 compressor is shown in figure 5.

Cout 4-2 Compressor Cin

Carry Sum

(a)
 X1 X2 X3 X4

FULL ADDER
Cin

Cout
FULL ADDER

Carry Sum

(b) Fig. 5: Proposed 4-2 compressor circuit

108
The equations determine the outputs of the circuit (figure 5) 3.18

Maximum output delay (ns)

are given below. The critical path delay of the compressor
3.17 XOR Delay (ns)
circuit is -XOR + 2*-MUX.
3.16
Sum= X1† X2 x X3† X4+ X1† X2 x X3† X4 x Cin+
3.15
X1† X2 x X3† X4+ X1† X2 x X3† X4 x Cin 3.14
Carry= X1† X2† X3† X4 x Cin+ X1† X2† X3† X4 x X4 3.13
Cout= (X1† X2)x X3+ (X1† X2) x X1 3.12
1.8 2 2.2 2.4 2.6 2.8 3 3.3
IV. RESULTS AND DISCUSSIONS
Supply voltage(V)
In this work an improved 4-2 compressor circuit has been
designed with new XOR-XNOR module and 2:1
multiplexer in 0.18m CMOS technology. The results of (b)
power consumption, maximum output delay of proposed 1.94

Maximum output delay (ns)

XOR-XNOR circuit has been obtained as shown in table I. XNOR Delay (ns)
1.935
TABLE I. POWER AND DELAY OF XOR-XNOR CIRCUIT
1.93
Supply Power
voltage consumption
XOR Delay XNOR Delay 1.925
(ns) (ns)
(V) (pW) 1.92
1.8 180.89 3.1702 1.9342
2.0 231.11 3.1618 1.9294 1.915
2.2 290.78 3.1564 1.9257 1.91
2.4 361.81 3.1505 1.9232
1.905
2.6 444.37 3.1468 1.9215
1.8 2 2.2 2.4 2.6 2.8 3 3.3
2.8 541.42 3.1437 1.9202
3.0 653.05 3.1410 1.9194 Supply voltage (V)
3.3 861.82 3.1375 1.9178
(c)
Power consumption varies from 180.89 pW to 861.82 pW Fig. 6: (a) Power consumption of XOR-XNOR (b) XOR
with variations in voltage from 1.8 V to 3.3 V. Delay of delay (c) XNOR delay
XOR shows variation from 3.1702 ns to 3.1375 ns. Further
the delay of XNOR circuit variation from 1.9342 ns to Figure 6(a) shows the power consumption variation of XOR-
1.9178 ns with varies in supply voltage from 1.8 V to 3.3 V. XNOR module with variation in supply voltage. Power
consumption of XOR-XNOR circuit is increasing with rise
in supply voltage. Figure 6(b) and 6(c) shows that the
1000 maximum output delay of XOR and XNOR circuit decreases
Power consumption (pW)
Power consumption (pW)

with increase in supply voltage. Table II shows the

800 configuration of simulated 4-2 compressor circuits in 0.18m
CMOS technology. Proposed 4-2 compressor uses 40
600
transistors and also works with supply voltage less than 1V.
400 TABLE II. CONFIGURATION OF SIMULATED 4-2 COMPRESSORS

200
4-2 compressor XOR- No. of
MUX
Designs XNOR transistors
0
Static CMOS Fig. 1(a) Fig. 2(a) 76
1.8 2 2.2 2.4 2.6 2.8 3 3.3
Ref. [15] Fig. 1(b) Fig. 2(a) 62
Supply voltage (V)
Ref. [16] Fig. 1(c) Fig. 2(b) 60

(a) Proposed circuit Fig. 3(a) Fig. 2(c) 40

109
 TABLE III. POWER, DELAY AND PDP OF PROPOSED 4-2 consumption of proposed and earlier reported 4-2
COMPRESSOR CIRCUIT
compressor circuits with variation in supply voltage. From
Supply Power Maximum
figure 8(a) it has been observed that power consumption of
PDP proposed 4-2 compressor circuit is least among the
voltage consumption output delay
× 10-22(J)
(V) (pW) (ps) compared circuits.
1.8 718.72 43.83 315.01
2.0 919.00 38.67 355.37 5000 Static CMOS [15]

Power consumption (pW)

2.2 1155.10 35.45 409.48 [16] Proposed
4000
2.4 1433.30 33.15 475.13
2.6 1758.30 31.38 551.75 3000
2.8 2136.40 30.22 645.62
3.0 2573.50 29.00 746.31 2000
3.3 3357.40 27.74 931.34
1000
Table III shows the power consumption, maximum output
delay and power delay product (PDP) of proposed 4-2 0
compressor. Power consumption varies from 718.72 pW to 1.8 2 2.2 2.4 2.6 2.8 3 3.3
3357.40 pW with variation of supply voltage from 1.8V to
3.3V. Maximum output delay and power delay product Supply voltage (V)
(PDP) of 4-2 compressor shows variations from 43.83 ps to (a)
27.74 ps and 315.01× 10-22 J to 931.34 × 10-22 J respectively.
Figure 7 shows the input and output waveforms for 120 Static CMOS [16]
proposed 4-2 compressor circuit. [15] Proposed
Output delay (ps) 100
80
60
40
20
0
1.8 2 2.2 2.4 2.6 2.8 3 3.3
Supply voltage (V)
(b)

3000 Static CMOS

[15]
2500 [16]
Proposed
2000
PDP (J)

1500
1000
500
0
Fig. 7: Input and output waveform for proposed 4-2 1.8 2 2.2 2.4 2.6 2.8 3 3.3
compressor circuit
Supply voltage (V)
Compressor circuit design using static CMOS and circuits
given in [15],[16] are also simulated in 0.18m technology (c)
and results of power consumption, delay and power delay
Fig. 8: (a) Power consumption (b) Maximum output delay
product have been obtained at supply voltage of 3.3V with
(c) PDP of 4-2 compressor circuits
100MHz frequency. Figure 8(a) shows the power

110
Figure 8(b) compares the maximum output delay of [6] Manoj Kumar “Design of Novel 9-Transistor Single Bit Full
Adder,” International Conference on Computational Science,
proposed and earlier reported 4-2 compressor circuits. It has Engineering and Information Technology (CCSEIT-2012),
been observed that proposed compressor circuit show Avinashilingam University, Coimbatore, India. pp. 334-337, Oct.
minimum delay. Further, power delay product (PDP) has 26-28, 2012.
also been computed for proposed and previously reported [7] M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance
circuits and it has been observed that the PDP of proposed 4- analysis of low-power 1-bit CMOS full adder cells,”IEEE Trans.
2 compressor is lowest. Comparison of performances of 4-2 VLSI Syst., vol. 10, pp. 20–29, Jan. 2002.
[8] Manoj Kumar, Sujata Pandey and Sandeep K. Arya, “Design of
compressor circuits is shown in table IV. It has been noticed
CMOS Energy Efficient Single Bit Full Adder,” Book Chapter of
that the present circuit shows less power consumption, Communications in Computer and Information Science, Springer-
output delay and power delay product as compared to earlier Verlag Berlin Heidelberg, CCIS 169, pp. 159-168, Jul. 2011.
reported circuits. [9] S.F. Hsiao, M.R. Jiang, J.S. Yeh, “Design of high low power 3-2
counter and 4-2 compressor for fast multipliers”, Electronic Letters,
TABLE IV. COMPARISON OF 4-2 COMPRESSORS AT 3.3V Vol. 34, No. 4, pp. 341-343, 1998.
[10] K. Prasad, K.K. Parhi, “Low power 4-2 and 5-2 compressors”,
Power Maximum Proceedings of 35th Asilomar Conference on Signals, Systems and
Compressor PDP
consumption output Computers, Vol. 1, pp. 129-133, 2001.
circuits × 10-22(J)
(pW) delay (ps) [11] A. Weinberger, “4:2 Carry-Save Adder Module”, IBM Technical
Static CMOS 4312.22 38.30 1651.58 Disclosure. Bulletin, Vol.23, January 1981.
[12] J. Gu and C. H. Chang, “Ultra Low-voltage, low-power 4-2
Ref. [15] 3830.90 57.24 2192.80 compressor for high speed multiplications,” in Proc. 36th IEEE Int.
Symp. Circuits Systems, Bangkok, Thailand, May 2003.
[13] D. Radhakrishnan, A.P. Preethy, “Low Power CMOS pass logic 4-2
Ref. [16] 3821.60 72.84 2783.65
compressor for high speed multiplication”, Proceedings of 43rd
Proposed 4-2 IEEE Midwest Symposium on Circuits and Systems, Vol. 3, pp.
3357.40 27.74 931.34
compressor 1296-1298, 2000.
[14] M. Margala and N. G. Durdle, “Low-power low-voltage 4-2
compressors for VLSI applications,” in Proc. IEEE Alessandro
V. CONCLUSIONS Volta Memorial Workshop Low-Power Design, pp. 84–90, 1999.
[15] S. Veeramachaneni, K. M. Krishna, L. Avinash, S. R. Puppala, and
A 4-2 compressor circuit based on a new XOR-XNOR M. Srinivas, “Novel architectures for high-speed and low-power 3-
design has been proposed which provide better 2, 4-2 and 5-2 compressors,” in VLSI Design, 2007. Held jointly
with 6th International Conference on Embedded Systems., 20th
performance. The proposed XOR-XNOR design shows International Conference on, pp. 324–329, Jan. 2007.
power consumption of 180.89 pW with supply voltage of [16] Jorge Tonfat, Ricardo Reis, “Low Power 3-2 and 4-2 Adder
1.8V. The XOR provide maximum output delay of 3.1702 Compressors Implemented Using ASTRAN”, IEEE Third Latin
ns and XNOR shows delay of 1.9342 ns at 1.8 V. The American Symposium on Circuits and Systems (LASCAS), Feb. 29,
2012-March 2, 2012.
proposed 4-2 compressor circuit shows power consumption
of 718.72 pW with maximum output delay of 43.83 ps.
Further, circuit shows PDP of 315.01× 10-22(J) at 1.8 V. The
performance of this circuit have been compared to earlier
reported circuits in terms of power consumption, maximum
output delay and power delay product (PDP). The proposed
circuit result shows better performance than existing circuits
in all aspect.
REFERENCES
[1] Z. Wang, G. A. Jullien, and W. C. Miller, “A new design technique
for column compression multipliers,” IEEE Trans. Comput., vol. 44,
pp. 962–970, Aug. 1995.
[2] Manoj Kumar, Sandeep K. Arya, Sujata Pandey, "Single bit full
adder design using 8 transistors with novel 3 transistors XNOR
gate," International Journal of VLSI Design & Communication
Systems, vol. 2, pp. 47-59, Dec. 2011.
[3] N. Weste, K. Eshranghian, Principles of CMOS VLSI Design: A
System Perspective, Reading MA: Addison-Wesley, 1993.
[4] R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS
versus pass-transistor logic,” IEEE J. Solid- State Circuits, vol. 32,
pp. 1079–1090, July 1997.
[5] M. Zhang, J. Gu, and C. H. Chang, “A novel hybrid pass logic with
static CMOS output drive full-adder cell,” in Proc. IEEE Int. Symp.
Circuits Syst., pp. 317–320, May 2003.

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