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input capacitance of an inverter delivering the same output current. Below given figure
represents the NOR-NOR implementation of Boolean expression Y = (T1+T2).(T3+T4).T5.
Having a total of 4 stages. We have introduced 2 inverters at the end to stabilize the delay
occurring in the output waveform.
Cout g
Cin
(GH )1/ N
Where,
N = number of stages
Bit0-
Bit1-
Bit2-
Bit3-
Bit4-
Transient Analysis-
X0 v/s out0-
X1 v/s out1-
X2 v/s out2-
X3 v/s out3-
X4 v/s out4-
Propagation Delay-
Out1-
tpHL = 9.44067-9.045 = 0.39567ns
tpLH = 6.40723-6.015 = 0.39223 ns
t pHL t pLH
tdelay 0.394ns
2
Out2-
tpHL = 12.42412-12.03 = 0.39412 ns
tpLH = 7.399047-7.01 = 0.389047 ns
t pHL t pLH
tdelay 0.3916ns
2
Out3-
tpHL = 7.42542-7.03 = 0.39542 ns
tpLH = 10.41187-10.01 = 0.40187 ns
t pHL t pLH
tdelay 0.3986ns
2
Out4-
tpHL = 6.538078-6.015 = 0.52307 ns
tpLH = 3.511302-3.045 = 0.466302 ns
t pHL t pLH
tdelay 0.4947ns
2